CN109964404B - 高线性度相位内插器 - Google Patents
高线性度相位内插器 Download PDFInfo
- Publication number
- CN109964404B CN109964404B CN201780068625.3A CN201780068625A CN109964404B CN 109964404 B CN109964404 B CN 109964404B CN 201780068625 A CN201780068625 A CN 201780068625A CN 109964404 B CN109964404 B CN 109964404B
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- CN
- China
- Prior art keywords
- capacitor
- phase
- current
- period
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
- H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311206443.1A CN117240261A (zh) | 2016-11-08 | 2017-11-08 | 高线性度相位内插器 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/346,524 US10855294B2 (en) | 2016-11-08 | 2016-11-08 | High linearity phase interpolator |
| US15/346,524 | 2016-11-08 | ||
| PCT/US2017/060658 WO2018089509A1 (en) | 2016-11-08 | 2017-11-08 | High linearity phase interpolator |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311206443.1A Division CN117240261A (zh) | 2016-11-08 | 2017-11-08 | 高线性度相位内插器 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109964404A CN109964404A (zh) | 2019-07-02 |
| CN109964404B true CN109964404B (zh) | 2023-10-20 |
Family
ID=62064144
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780068625.3A Active CN109964404B (zh) | 2016-11-08 | 2017-11-08 | 高线性度相位内插器 |
| CN202311206443.1A Pending CN117240261A (zh) | 2016-11-08 | 2017-11-08 | 高线性度相位内插器 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311206443.1A Pending CN117240261A (zh) | 2016-11-08 | 2017-11-08 | 高线性度相位内插器 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US10855294B2 (enExample) |
| EP (1) | EP3539212A4 (enExample) |
| JP (2) | JP7132554B2 (enExample) |
| KR (2) | KR102471135B1 (enExample) |
| CN (2) | CN109964404B (enExample) |
| WO (1) | WO2018089509A1 (enExample) |
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| US11323123B2 (en) | 2019-12-20 | 2022-05-03 | Microchip Technology Inc. | Circuit to correct phase interpolator rollover integral non-linearity errors |
| US10917097B1 (en) | 2019-12-24 | 2021-02-09 | Microsemi Semiconductor Ulc | Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits |
| US11239933B2 (en) | 2020-01-28 | 2022-02-01 | Microsemi Semiconductor Ulc | Systems and methods for transporting constant bit rate client signals over a packet transport network |
| US11463005B2 (en) * | 2020-04-27 | 2022-10-04 | Texas Instruments Incorporated | Ramp generator for buck/boost converters |
| CN111697950B (zh) * | 2020-06-23 | 2021-07-09 | 上海安路信息科技股份有限公司 | 本征线性相位插值器 |
| US11424902B2 (en) | 2020-07-22 | 2022-08-23 | Microchip Technology Inc. | System and method for synchronizing nodes in a network device |
| US11165431B1 (en) * | 2020-12-09 | 2021-11-02 | Analog Devices, Inc. | Techniques for measuring slew rate in current integrating phase interpolator |
| US11500336B1 (en) | 2021-05-11 | 2022-11-15 | Texas Instruments Incorporated | Methods and apparatus for low jitter fractional output dividers |
| US12323334B2 (en) | 2021-06-30 | 2025-06-03 | Microchip Technology Inc. | System and method for performing rate adaptation and multiplexing of constant bit rate (CBR) client data for transmission over a metro transport network (MTN) |
| US11916662B2 (en) | 2021-06-30 | 2024-02-27 | Microchip Technology Inc. | System and method for performing rate adaptation of constant bit rate (CBR) client data with a fixed number of idle blocks for transmission over a metro transport network (MTN) |
| US11838111B2 (en) | 2021-06-30 | 2023-12-05 | Microchip Technology Inc. | System and method for performing rate adaptation of constant bit rate (CBR) client data with a variable number of idle blocks for transmission over a metro transport network (MTN) |
| US11581897B1 (en) | 2021-07-16 | 2023-02-14 | Texas Instruments Incorporated | Dual slope digital-to-time converters and methods for calibrating the same |
| US11736065B2 (en) | 2021-10-07 | 2023-08-22 | Microchip Technology Inc. | Method and apparatus for conveying clock-related information from a timing device |
| US11799626B2 (en) | 2021-11-23 | 2023-10-24 | Microchip Technology Inc. | Method and apparatus for carrying constant bit rate (CBR) client signals |
| US12192079B2 (en) | 2021-11-23 | 2025-01-07 | Microchip Technology Inc. | Method and apparatus for carrying constant bit rate (CBR) client signals using CBR carrier streams comprising frames |
| CN114070271B (zh) * | 2022-01-14 | 2022-05-03 | 南京沁恒微电子股份有限公司 | 基于相位插值的时钟抖动产生装置及其方法 |
| JP2023174194A (ja) * | 2022-05-27 | 2023-12-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US11799460B1 (en) | 2022-06-29 | 2023-10-24 | Texas Instruments Incorporated | Dynamic phase adjustment for high speed clock signals |
| US12425041B2 (en) * | 2022-07-06 | 2025-09-23 | Skyworks Solutions, Inc. | Interpolative divider |
| US12143114B2 (en) * | 2022-10-24 | 2024-11-12 | Texas Instruments Incorporated | Digital-to-time converter (DTC) having a pre-charge circuit for reducing jitter |
| CN115833798B (zh) * | 2023-02-15 | 2023-05-02 | 南京沁恒微电子股份有限公司 | 一种高线性度多比特相位插值器 |
| CN116599523B (zh) * | 2023-07-19 | 2024-02-23 | 牛芯半导体(深圳)有限公司 | 相位插值电路、锁相环电路 |
| US12445137B2 (en) * | 2023-08-20 | 2025-10-14 | Apple Inc. | Low noise, supply rejecting linear phase interpolator |
| CN118367900B (zh) * | 2024-06-20 | 2024-09-03 | 格创通信(浙江)有限公司 | 一种相位插值电路及封装电路 |
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| CN1507717A (zh) * | 2001-03-20 | 2004-06-23 | Gct�뵼������˾ | 使用分数补偿方法的分数-n频率合成器 |
| US7417510B2 (en) * | 2006-09-28 | 2008-08-26 | Silicon Laboratories Inc. | Direct digital interpolative synthesis |
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-
2016
- 2016-11-08 US US15/346,524 patent/US10855294B2/en active Active
-
2017
- 2017-11-08 EP EP17870432.6A patent/EP3539212A4/en not_active Withdrawn
- 2017-11-08 JP JP2019545898A patent/JP7132554B2/ja active Active
- 2017-11-08 KR KR1020197012773A patent/KR102471135B1/ko active Active
- 2017-11-08 WO PCT/US2017/060658 patent/WO2018089509A1/en not_active Ceased
- 2017-11-08 CN CN201780068625.3A patent/CN109964404B/zh active Active
- 2017-11-08 KR KR1020227040926A patent/KR102656504B1/ko active Active
- 2017-11-08 CN CN202311206443.1A patent/CN117240261A/zh active Pending
-
2020
- 2020-10-27 US US17/080,879 patent/US20210044300A1/en active Pending
-
2022
- 2022-08-12 JP JP2022128801A patent/JP7655612B2/ja active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1507717A (zh) * | 2001-03-20 | 2004-06-23 | Gct�뵼������˾ | 使用分数补偿方法的分数-n频率合成器 |
| US7417510B2 (en) * | 2006-09-28 | 2008-08-26 | Silicon Laboratories Inc. | Direct digital interpolative synthesis |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2020501467A (ja) | 2020-01-16 |
| WO2018089509A1 (en) | 2018-05-17 |
| US20180131378A1 (en) | 2018-05-10 |
| CN109964404A (zh) | 2019-07-02 |
| KR20190090787A (ko) | 2019-08-02 |
| JP2022163176A (ja) | 2022-10-25 |
| KR102471135B1 (ko) | 2022-11-28 |
| JP7132554B2 (ja) | 2022-09-07 |
| CN117240261A (zh) | 2023-12-15 |
| EP3539212A1 (en) | 2019-09-18 |
| KR102656504B1 (ko) | 2024-04-12 |
| US10855294B2 (en) | 2020-12-01 |
| JP7655612B2 (ja) | 2025-04-02 |
| KR20240051295A (ko) | 2024-04-19 |
| KR20220162855A (ko) | 2022-12-08 |
| US20210044300A1 (en) | 2021-02-11 |
| EP3539212A4 (en) | 2019-12-18 |
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