CN109755207B - 集成扇出型封装及其形成方法 - Google Patents
集成扇出型封装及其形成方法 Download PDFInfo
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- CN109755207B CN109755207B CN201810730520.6A CN201810730520A CN109755207B CN 109755207 B CN109755207 B CN 109755207B CN 201810730520 A CN201810730520 A CN 201810730520A CN 109755207 B CN109755207 B CN 109755207B
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- layer
- metal
- integrated fan
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- intermetallic
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Abstract
本发明实施例公开多种集成扇出型封装及其形成方法。一种集成扇出型封装包括凸块结构、聚合物层以及金属层。凸块结构包括金属垫以及与金属垫电连接的凸块。聚合物层从凸块的侧壁侧向延伸。金属层覆盖凸块结构并与金属垫的侧表面实体接触。
Description
技术领域
本发明实施例是涉及集成扇出型封装及其形成方法。
背景技术
近年来,由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度持续提高,半导体产业已经历了快速成长。在很大程度上,集成密度的这种提高来自于最小特征尺寸(minimum feature size)的连续减小,这使得在给定区域中能够整合有更多组件。
与先前的封装相比,这些较小的电子组件也需要占据较小面积的较小的封装。半导体封装类型的实例包括方形扁平封装(quad flat packages,QFP)、针格阵列(pin gridarray,PGA)封装、球格阵列(ball grid array,BGA)封装、倒装芯片(flip chip,FC)、三维集成电路(three-dimensional integrated circuit,3DIC)、晶片级封装(wafer levelpackage,WLP)及叠层封装(package on package,PoP)装置等。目前,集成扇出型封装因其紧凑性(compactness)而变得越来越流行。然而,然而,存在与集成扇出型封装相关的许多挑战。
发明内容
根据本发明的一些实施例,一种集成扇出型封装包括凸块结构、聚合物层以及金属层。凸块结构包括金属垫以及与金属垫电连接的凸块。聚合物层从凸块的侧壁侧向延伸。金属层覆盖凸块结构并与金属垫的侧表面实体接触(physical contact)。
根据本发明的另一些实施例,集成扇出型封装包括半导体芯片、凸块结构以及第一重分布层。凸块结构电连接到半导体芯片并包括焊料凸块、镍接垫以及金属间化合物层。镍接垫电连接到焊料凸块。金属间化合物层在焊料凸块与镍接垫之间,其中金属间化合物层包括金。第一重分布层在凸块结构与半导体芯片之间。
根据本发明的替代实施例,形成集成扇出型封装的方法包括以下操作。提供载板,所述载板上形成有聚合物层和胶层。使用所述胶层作为晶种层在载板上镀覆多个金属垫。使用所述胶层作为晶种层在金属垫上镀覆第一重分布层。移除载板。形成多个凸块,所述凸块穿过聚合物层并与金属垫电连接。
附图说明
图1A至图1J是根据一些实施例的形成集成扇出型封装的方法的剖视图。
图2至图5是根据一些实施例的集成扇出型封装的剖视图。
图6A至图6H是根据替代实施例的形成集成扇出型封装的方法的剖视图。
图7至图10是根据替代实施例的集成扇出型封装的剖视图。
图11A至图11F是根据另一些实施例的形成集成扇出型封装的方法的剖视图。
图12是根据另一些实施例的集成扇出型封装的剖视图。
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同实施例或实例。以下出于以简化方式传达本公开内容的目的来阐述组件及排列形式的具体实例。当然,这些仅为实例而并非旨在进行限制。举例来说,以下说明中将第二特征形成在第一特征“之上”或第一特征“上”可包括其中第二特征与第一特征形成为直接接触的实施例,且也可包括其中第二特征与第一特征之间可形成附加特征、从而使得所述第二特征与所述第一特征可能不直接接触的实施例。另外,可使用相同的参考编号及/或字母来指代本公开的各种实例中的相同或相似的部分。重复使用参考编号是出于简明及清晰的目的,而其自身并不表示所论述的各种实施例及/或配置之间的关系。
此外,本文中可能使用例如“在…之下(beneath)”、“在…下方(below)”、“下部的(lower)”、“位于…上(on)”、“位于…之上(over)”、“在…上方(above)”、“上部的(upper)”等空间相对性用语以便于阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有另外取向(旋转90度或处于其他取向),且本文中所使用的空间相对性描述语可同样相应地进行解释。
图1A至图1J是根据一些实施例的形成集成扇出型封装的方法的剖视图。
参照图1A,在载板C上形成聚合物层101。在一些实施例中,载板C具有剥离层DB,聚合层101形成在剥离层DB上。在一些实施例中,载板C为玻璃衬底,剥离层DB为在玻璃衬底上形成的光热转换(Light-to-Heat Conversion,LTHC)离型层。聚合物层101包括聚苯并恶唑(polybenzoxazole,PBO)、聚酰亚胺(polyimide,PI)、苯并环丁烯(benzocyclobutene,BCB)、其组合或其类似物。
之后,在聚合物层101上依次形成可选阻障层(阻障层)102和胶层(glue layer)104。在一些实施例中,阻障层102包括金属,例如Ti、W、Cr、TiW或其组合,并且可以通过溅射或合适的方法形成。在一些实施例中,胶层104包括金属,如金或其合金,可以通过溅射或合适的方法形成。
之后,在胶层104上形成光刻胶层PR1。在一些实施例中,光刻胶层PR1是干式膜抗蚀剂(dry film resist,DFR)并具有开口,所述开口裸露出随后形成的金属垫109的预期位置。
参照图1B,在光刻胶层PR1的开口中形成金属垫109。在一些实施例中,形成金属垫109的方法包括执行电化学镀覆(electrochemical plating,ECP)工艺。在一些实施例中,金属垫109通过使用胶层104作为晶种层而镀覆在开口中。具体来说,在没有溅射或镀覆晶种层的情况下,将金属垫109直接镀覆在胶层104上。在一些实施例中,胶层104在整个说明书中被称为晶种层。
在一些实施例中,在金属垫109被镀覆之前,可以在每个开口中镀覆可选胶层106,以改善随后形成的金属垫109的镀覆性能。在一些实施例中,胶层106和胶层104由相同的材料制成。在替代实施例中,胶层106和胶层104包括不同的材料。
在一些实施例中,金属垫109包括镍、铜或其组合。在一些实施例中,每个金属垫109具有多层结构,其包括金属层108以及在金属层108上的可选顶盖层110。在一些实施例中,金属层108包括镍,顶盖层110包括铜。然而,本发明实施例不限于此。在替代实施例中,金属垫109由单一种材料制成,例如镍或铜。
在一些实施例中,对于多层金属垫109,金属层108的厚度约为顶盖层110的厚度的3至10倍(例如6倍)。在一些实施例中,金属层108的厚度约为胶层104或胶层106的厚度的5至40倍(例如30倍)。在一些实施例中,金属层108的厚度约为下方阻障层102的厚度的5至20倍(例如10倍)。
参考图1C,移除光刻胶层PR1及其下方的胶层104以及阻障层102,因此剩余胶层104a和阻障层102a被设置在相应的金属垫109的下方。
参照图1D,在聚合物层101上形成聚合物层112。在一些实施例中,聚合物层112具有分别裸露出金属垫109的部分顶面的开口。在一些实施例中,聚合物层112包括聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合或其类似物。
参照图1E,晶种层114形成在聚合物层122的整个表面上并且与金属垫109的裸露出的顶面实体接触。在一些实施例中,晶种层114为钛/铜复合层,通过溅射或合适的方法形成。
之后,在晶种层114上形成光刻胶层PR2。在一些实施例中,光刻胶层PR2是干式膜抗蚀剂(DFR)并具有开口,所述开口裸露出随后形成的重分布层的预期位置。之后,执行镀覆工艺以在由光刻胶层PR2的开口裸露出的晶种层114上形成金属层116(例如,铜层)。
参考图1F,移除光刻胶层PR2及其下方的晶种层114,因此,第一重分布层115形成在金属垫109上并通过其通孔(vias)113电连接到金属垫109。在一些实施例中,第一重分布层115包括晶种层114a和在晶种层114a上的金属层116。在一些实施例中,第一重分布层115的金属层116的厚度约为其下方的每个金属垫109的金属层108的厚度的0.5至5倍(例如1.5至2.0倍)。
之后,在聚合物层112上形成聚合物层118。在一些实施例中,聚合物层112具有开口,所述开口部分裸露出第一重分布层115的顶面。在一些实施例中,聚合物层118包括聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合或其类似物。
在一些实施例中,第一重分布层115和聚合物层118构成第一重分布层结构RDL1。在一些实施例中,第一重分布层结构RDL1在整个说明书中被称为背侧重分布层结构。
参照图1G,在第一重分布层115上形成集成扇出型穿孔TIV,且集成扇出型穿孔TIV电连接到第一重分布层115。在一些实施例中,集成扇出型穿孔TIV穿过聚合物层118并电连接至第一重分布层115,从而电连接至金属垫109。在一些实施例中,集成扇出型穿孔TIV包括铜,并由光刻、镀覆和光刻胶剥除所形成。
参照图1H,拾取半导体芯片100并放置在载板C上,使得集成扇出型穿孔TIV位于半导体芯片100的侧边或周围。在一些实施例中,半导体芯片100具有衬底100a、在衬底100a上方的接垫100b、在衬底100a上方且裸露出部分接垫100b的钝化层100c、在钝化层100c上方并电连接到接垫100b连接件100d以及在钝化层100c上方和连接件100d侧边的保护层100e。在一些实施例中,半导体芯片100的具有连接件100d的一侧在整个说明书中被称为前侧。在一些实施例中,在半导体芯片100的背侧与聚合物层118之间形成晶粒贴合膜(die attachfilm,DAF)。
之后,在半导体芯片100和集成扇出型穿孔TIV侧边的载板C上形成包封体(encapsulant)E。在一些实施例中,包封体E围绕着半导体芯片100和集成扇出型穿孔TIV,并裸露出集成扇出型穿孔TIV和连接件100d的表面。包封体E包括模塑化合物,如环氧树脂;光敏材料,如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合或其类似物。形成包封体E的方法包括在载板C上形成覆盖半导体芯片100和集成扇出型穿孔TIV的包封体材料层,并进行研磨工艺以部分地移除包封体材料层。
参照图1I,在半导体芯片100和集成扇出型穿孔TIV上形成第二重分布层结构RDL2,且第二重分布层结构RDL2与半导体芯片100和集成扇出型穿孔TIV电连接。在一些实施例中,第二重分布层结构RDL2在整个说明书中被称为前侧重分布层结构。
在一些实施例中,第二重分布层结构RDL2包括交替堆叠的多个聚合物层120和多个第二重分布层122。在一些实施例中,每个聚合物层120包括聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合或其类似物。每个第二重分布层12包括铜,并且由光刻、镀覆和光刻胶剥除所形成。
继续参照图1I,在第二重分布层结构RDL2上形成凸块下金属化(under-凸块metallurgy,UBM)接垫123,且UBM接垫123电连接到第二重分布层结构RDL2。之后,在UBM接垫123上分别形成凸块124。在一些实施例中,凸块124为焊料凸块(solder凸块s),可以通过蒸镀、镀覆、球滴或丝网印刷等适当的工艺形成。在一些实施例中,凸块124可从下至上包括铜层、镍层、另一铜层和焊料凸块。根据工艺要求,可以使用其他类型的凸块结构。
参考图1J,移除载板C。在一些实施例中,剥离层DB在光热下分解,然后载板C从半导体芯片100的背侧剥离。
之后,将介电层101图案化,使得开口OP形成为穿过介电层101。在一些实施例中,介电层101的开口OP由激光钻孔工艺然后接着电浆清洁工艺所形成。在一些实施例中,在图案化操作过程中,会同时移除部分阻障层102a,以裸露出胶层104a的底面。在一些实施例中,开口OP的数目对应于集成扇出型穿孔TIV的数目。之后,在介电层101的开口中放置凸块126。在一些实施例中,凸块126为焊料凸块,可以通过蒸镀、镀覆、球滴或丝网印刷等适当的工艺形成。于凸块形成操作的热回流工艺期间,在胶层104a与凸块126之间分别形成金属间化合物层(金属间化合物层)IMC1。在一些实施例中,金属间化合物层IMC1包括金(Au)。举例来说,金属间化合物层IMC1包括金-锡金属间化合物层。由此完成具有双侧端子(例如,凸块124和凸块126)的集成扇出型封装10。
之后,提供另一封装200。在一些实施例中,封装200包括存储器或其他适当的半导体组件。封装200通过接垫202和凸块126电连接到集成扇出型封装10,从而制造了叠层封装(POP)结构。
尽管以上描述了集成扇出型封装10,但应理解,本发明实施例不限于上述结构,因为可以在组件的材料和排列方面做出许多修改。下面描述了结构的一些可能的修改。
在一些实施例中,如图1J以及图2至图5所示,集成扇出型封装10/11/12/13/14包括半导体芯片100、凸块结构BS以及第一重分布层115。凸块结构BS电连接到半导体芯片100并且包括焊料凸块126、金属垫109以及金属间化合物层IMC1/IMC2。金属垫109(例如镍接垫)电连接到焊料凸块126。金属间化合物层IMC1/IMC2位于焊料凸块126与金属垫109之间。第一重分布层115位于凸块结构BS与半导体芯片100之间,并且包括晶种层114a和连接到晶种层114a的金属层116。
在一些实施例中,集成扇出型封装10/11/12/13/14还包括集成扇出型穿孔TIV,且集成扇出型穿孔TIV电连接到第一重分布层115,且因此电连接到金属垫109。在一些实施例中,集成扇出型穿孔TIV的晶种层与第一重分布层115的金属层116实体接触。
在一些实施例中,凸块结构BS的金属垫109与第一重分布层115的晶种层114a实体接触。在一些实施例中,第一重分布层115通过通孔113与金属垫109的顶盖层110(例如铜层)的部分顶面实体接触,如图1J的集成扇出型封装10所示。在替代实施例中,当从上述方法中省略形成可选顶盖层110时,第一重分布层115形成为通过通孔113与金属垫109的金属层108(例如,镍层)的部分顶面接触,如图2的集成扇出封装11所示。
在一些实施例中,每个凸块结构BS还包括胶层106和胶层104a,胶层106和胶层104a位于金属垫109与金属间化合物层IMC1之间,如图1J和图2的集成扇出型封装10/11所示。在一些实施例中,金属间化合物层IMC1是金-锡金属间化合物层。
在一些实施例中,集成扇出型封装还包括阻障层102a,且阻障层102a配置为与金属间化合物层IMC1实体接触且位于焊料凸块126周围。胶层106和胶层104a包括与阻障层102a不同的材料。举例来说,胶层106和胶层104a包括金或其合金,阻障层102a包括Ti、W、Cr、TiW或其组合。在一些实施例中,金属垫109的边缘实质上与胶层104a和阻障层102a的边缘对齐。
在一些实施例中,如图3所示,焊料凸块126可以完全消耗(consume)胶层104a和胶层106(例如金层),并且可以与金和镍反应以在焊料凸块126与金属垫109之间形成金属间化合物层IMC2。在一些实施例中,金属间化合物层IMC2是镍-金-锡金属间化合物层。
在一些实施例中,当从上述方法中省略形成可选胶层106,金属层108直接溅射在胶层104a上,如图4的集成扇出封装13所示。在一些实施例中,如图5所示,焊料凸块126可以完全消耗胶层104a(例如金层),并且可以与金和镍反应以在焊料凸块126与金属垫109之间形成金属间化合物层IMC2。
在本发明实施例中,在焊料凸块和背侧重分布层之间引入金属垫(例如Cu/Ni/Au或Ni/Au堆叠),所以焊料凸块不会消耗背侧重分布层而生成金属间化合物(IMC)等等,因此可提高封装的可靠度。
以上实施是关于最终封装质量。以下实施例旨在提高封装质量和节约成本。
图6A至图6H是根据替代实施例的形成集成扇出型封装的方法的剖视图。图6A-6H的方法与图1A-1J的方法相似,不同之处在于背侧重分布层的形成和配置。相似参考编号将被用来表示相似组件。它们之间的区别将在下面详细描述,并且这里不重复相似性。
参照图6A,提供载板C,且载板C上形成有聚合物层101和胶层104。在一些实施例中,载板C具有剥离层DB,聚合层101形成在剥离层DB上。在一些实施例中,在聚合物层101上形成可选阻障层102和胶层104。在一些实施例中,阻障层102包括金属,例如Ti、W、Cr、TiW或其组合,并且可以通过溅射或合适的方法形成。在一些实施例中,胶层104包括金属,如金或其合金,可以通过溅射或合适的方法形成。
之后,在胶层104上形成光刻胶层PR1。在一些实施例中,光刻胶层PR1是干式膜抗蚀剂(DFR)并具有开口,所述开口裸露出随后形成的金属垫109的预期位置。
参照图6B,通过使用胶层104作为晶种层,将多个金属垫109镀覆在载板C上。在一些实施例中,通过使用溅射胶层104作为晶种层,将金属垫109镀覆在光刻胶层PR1的开口中。具体来说,在没有溅射或镀覆晶种层的情况下,将金属垫109直接镀覆在胶层104上。
在一些实施例中,金属垫109包括镍、铜或其组合。在一些实施例中,每个金属垫109具有多层结构,其包括金属层108以及在金属层108上的可选顶盖层110。在一些实施例中,金属层108包括镍,顶盖层110包括铜。然而,本发明实施例不限于此。在替代实施例中,金属垫109由单一种材料制成,例如镍或铜。
在一些实施例中,每个金属垫109的镍层的厚度约为可选顶盖层110的厚度的3至10倍(例如6倍)。在一些实施例中,每个金属垫109的镍层的厚度约为下方金胶层104的厚度的5至40倍(例如30倍)。
参照图6C至图6E,通过使用相同的胶层104作为晶种层,将金属层116镀覆在金属垫109上。在一些实施例中,金属层116在整个说明书中被称为背侧重分布层。
在一些实施例中,如图6C所示,在不移除胶层104和阻障层102的情况下,移除(例如剥除)光刻胶层PR1。之后,如图6D所示,在移除光刻胶层PR1之后,在胶层104上形成另一光刻胶层PR2。在一些实施例中,光刻胶层PR2是干式膜抗蚀剂(DFR)并具有开口,所述开口裸露出随后形成的重分布层的预期位置。之后,执行镀覆工艺以在由光刻胶层PR2的开口裸露出的胶层104上形成金属层116(例如,铜层)。具体来说,在不溅射或镀覆晶种层的情况下,将金属层116直接镀覆在胶层104上。换句话说,在形成金属层116的操作期间不需要传统的Ti/Cu晶种层。
在一些实施例中,在胶层104上形成金属层116,且金属层116覆盖或包封金属垫109的侧表面和顶面。在一些实施例中,金属层116形成为与金属垫109接触。
之后,如图6E所示,移除光刻胶层PR2及其下方的胶层104以及阻障层102,因此剩余胶层104b和阻障层102b被设置在第一金属层116的下方。然后,在聚合物层112上形成聚合物层118。在一些实施例中,聚合物层112具有开口,所述开口部分裸露出金属层116的顶面。在一些实施例中,金属层116和聚合物层118构成第一重分布层结构RDL1。在一些实施例中,第一重分布层结构RDL1在整个说明书中被称为背侧重分布层结构。
继续参考图6E,在重分布层(例如,金属层116)上形成多个集成扇出型穿孔TIV,且集成扇出型穿孔TIV电连接到重分布层。在一些实施例中,集成扇出型穿孔TIV穿过聚合物层118并电连接到金属层116,且因此电连接到金属垫109。
参考图6F,拾取半导体芯片100并放置在载板C上,使得集成扇出型穿孔TIV位于半导体芯片100的侧边或周围。之后,在半导体芯片100和集成扇出型穿孔TIV侧边的载板C上形成包封体E。
参考图6G,在半导体芯片100上形成第二重分布层结构RDL2,且第二重分布层结构RDL2电连接到集成扇出型穿孔TIV。在一些实施例中,第二重分布层结构RDL2在整个说明书中被称为前侧重分布层结构。在一些实施例中,第二重分布层结构RDL2包括交替堆叠的多个聚合物层120和多个第二重分布层122。之后,在第二重分布层结构RDL2上形成UBM接垫123,且UBM接垫123电连接到第二重分布层结构RDL2。之后,在UBM接垫123上分别形成凸块124。
参照图6H,凸块126形成为穿过聚合物层101并电连接到金属垫109。在一些实施例中,移除载板C,然后将介电层101和阻障层102b图案化,使得开口OP形成为穿过介电层101和阻障层102b,并且将凸块126放置在开口OP中。于凸块形成操作的热回流工艺期间,在胶层104b与凸块126之间分别形成金属间化合物层IMC1。在一些实施例中,金属间化合物层IMC1包括金(Au)。举例来说,金属间化合物层IMC1包括金-锡金属间化合物层。由此完成具有双侧端子(例如,凸块124和凸块126)的集成扇出型封装20。
之后,提供另一封装200,封装200通过接垫202和凸块126电连接到集成扇出型封装20,从而制造了叠层封装(POP)结构。
尽管以上描述了集成扇出型封装20,但应理解的是,本发明实施例不限于结构,因为可以在组件的材料和布置两方面做出许多修改。下面描述了结构的一些可能的修改。
在一些实施例中,如图6H和图7-10所示,集成扇出型封装20/21/22/23/24包括凸块结构BS、聚合物层101以及金属层116。凸块结构BS包括金属垫109以及与金属垫109电连接的凸块126。聚合物层101从凸块126的侧壁侧向延伸。金属层116位于凸块结构BS之上并且与金属垫109的侧表面实体接触。在一些实施例中,金属层116包封金属垫109的侧表面和顶面。
在一些实施例中,集成扇出型封装20/21/22/23/24还包括集成扇出型穿孔TIV,集成扇出型穿孔TIV电连接到金属层116,且因此电连接到金属垫109。在一些实施例中,集成扇出型穿孔TIV的晶种层与金属层116实体接触。
在一些实施例中,金属垫109包括镍、铜或其组合。举例来说,金属垫109包括金属层108(例如镍层)以及在金属层108上的可选顶盖层110(例如铜层)。在一些实施例中,金属层116与金属层108和顶盖层110实体接触,如图6H的集成扇出型封装20所示。在替代实施例中,当从上述方法中省略形成可选顶盖层110时,金属层116形成为接触金属垫109的金属层108,如图7的集成扇出型封装21所示。
在一些实施例中,凸块结构BS还包括金属垫109与凸块126之间的金属间化合物层IMC1/IMC2,且金属间化合物层包括金(Au)。
在一些实施例中,每个凸块结构BS还包括胶层104b,胶层104b位于金属垫109与金属间化合物层IMC1之间以及聚合物层101与金属层116之间,如图6H和图7的集成扇出型封装20/21所示。在一些实施例中,金属间化合物层IMC1是金-锡金属间化合物层。
在一些实施例中,在胶层104b与聚合物层101之间和凸块126周围还包括阻障层102b。胶层104b和阻障层102b包括不同的材料。举例来说,胶层104b包括金或其合金,阻障层102b包括Ti、W、Cr、TiW或其组合。在一些实施例中,金属层116的边缘实质上与胶层104b和阻障层102b的边缘对齐。
在一些实施例中,如图8所示,焊料凸块126可以完全消耗胶层104b(例如金层),并且可以与金和镍(或铜)反应以形成在焊料凸块126与金属垫109之间的金属间化合物层IMC2。在一些实施例中,金属间化合物层IMC2更在金属层116与聚合物层101之间延伸。在一些实施例中,金属间化合物层IMC2包括镍-金-锡金属间化合物层、铜-金-锡金属间化合物层或两者。具体来说,金属垫109与焊料凸块126之间的金属间化合物层IMC2的部分为镍-金-锡金属间化合物层,而金属层116与聚合物层101之间的金属间化合物层IMC2的另一部分为铜-金-锡金属间化合物层。在一些实施例中,金属间化合物层IMC2与聚合物层101之间和焊料凸块126周围还包括阻障层102b。
在一些实施例中,上述方法还包括形成可选胶层106,并且通过使用胶层106作为晶种层,将金属层108镀覆在胶层106上,如图9的集成扇出型封装23所示。具体来说,在金属垫109与焊料凸块126之间的胶层较厚,而在聚合物层101与金属层116之间的胶层较薄。在一些实施例中,金属垫109的金属层108的厚度约为胶层106厚度的5至30倍(例如15倍),并且约为胶层104b的厚度的5倍至40倍(例如30倍)。
在一些实施例中,如图10所示,焊料凸块126可以完全消耗胶层104a和胶层106(例如金层),并且可以与金和镍(或铜)反应以形成在焊料凸块126与金属垫109之间的金属间化合物层IMC2。在一些实施例中,金属间化合物层IMC2更在金属层116与聚合物层101之间延伸。在一些实施例中,金属间化合物层IMC2包括镍-金-锡金属间化合物层、铜-金-锡金属间化合物层或两者。
在形成重分布层之前形成金属垫的上述实施例是为了说明目的而提供的,并不被解释为限制本发明实施例。在一些实施例中,可以根据工艺要求,在形成重分布层之后形成金属垫。
图11A至图11F是根据另一些实施例的形成集成扇出型封装的方法的剖视图。图11A-11F的方法与图1A-1J的方法相似,不同之处在于金属垫和重分布层的形成顺序。相似参考编号将被用来表示相似组件。它们之间的区别将在下面详细描述,并且这里不重复相似性。
参照图11A,提供载板C,且载板C上形成有聚合物层101。在一些实施例中,载板C具有剥离层DB,聚合层101形成在剥离层DB上。在一些实施例中,在聚合物层101上形成可选阻障层102。在一些实施例中,阻障层102包括金属,例如Ti、W、Cr、TiW或其组合,并且可以通过溅射或合适的方法形成。
之后,在阻障层102上形成第一重分布层115。在一些实施例中,第一重分布层115包括晶种层114a以及在晶种层114a上的金属层116。之后,在聚合物层112上形成聚合物层118。在一些实施例中,第一重分布层115和聚合物层118构成第一重分布层结构RDL1。在一些实施例中,第一重分布层结构RDL1在整个说明书中被称为背侧重分布层结构。
参照图11B,在第一重分布层115上形成集成扇出型穿孔TIV,且集成扇出型穿孔TIV电连接到第一重分布层115。之后,拾取半导体芯片100并放置在载板C上,使得集成扇出型穿孔TIV位于半导体芯片100的侧边或周围。之后,在半导体芯片100和集成扇出型穿孔TIV侧边的载板C上形成包封体E。
参考图11C,在半导体芯片100上形成第二重分布层结构RDL2,且第二重分布层结构RDL2电连接到集成扇出型穿孔TIV。在一些实施例中,第二重分布层结构RDL2在整个说明书中被称为前侧重分布层结构。在一些实施例中,第二重分布层结构RDL2包括交替堆叠的多个聚合物层120和多个第二重分布层122。之后,在第二重分布层结构RDL2上形成UBM接垫123,且UBM接垫123电连接到第二重分布层结构RDL2。之后,在UBM接垫123上分别形成凸块124。
参考图11D,剥离层DB在光热下分解,然后载板C从半导体芯片100的背侧剥离。之后,将介电层101图案化,使得开口OP形成为穿过介电层101。在一些实施例中,介电层101的开口OP由激光钻孔工艺然后接着电浆清洁工艺所形成。在一些实施例中,在图案化操作过程中,会同时移除部分阻障层102,以裸露出晶种层114a的底面。
参照图11E,在每个开口OP中形成金属垫125和胶层127,并且金属垫125位在晶种层114a与胶层127之间并与晶种层114a与胶层127实体接触。
在一些实施例中,每个金属垫125由单一种材料制成,例如镍、铜或其组合,且胶层127包括金或其合金。在一些实施例中,形成金属垫125和胶层127的方法包括进行化学镀(electroless plating),例如化学镀镍浸金(Electroless Nickel Immersion Gold,ENIG)工艺。在一些实施例中,每个金属垫125的镍层的厚度约为下方金胶层127的厚度的5至40倍(例如30倍)。
在替代实施例中,金属垫125是多层结构,其包括(举例来说)金属层(例如镍层)以及可选接口层(例如铂层),接口层位于镍层以及随后形成的焊料凸块之间并与镍层以及随后形成的焊料凸块实体接触。在这种实例中,形成金属垫125和胶层127的方法包括进行化学镀,例如化学镀镍化学镀钯浸金(Electroless Nickel Electroless PalladiumImmersion Gold,ENEPIG)工艺。在一些实施例中,每个金属垫125的镍层的厚度约为铂层厚度的5至40倍(例如30倍)。在一些实施例中,每个金属垫125的镍层的厚度约为下方金胶层127的厚度的5至40倍(例如30倍)。
之后,在介电层101的开口OP中放置凸块126。在一些实施例中,凸块126为焊料凸块,可以通过蒸镀、镀覆、球滴或丝网印刷等适当的工艺形成。于凸块形成操作的热回流工艺期间,在胶层127与凸块126之间分别形成金属间化合物层IMC1。在一些实施例中,金属间化合物层IMC1包括金(Au)。举例来说,金属间化合物层IMC1包括金-锡金属间化合物层。由此完成具有双侧端子(例如,凸块124和凸块126)的集成扇出型封装30。
之后,提供另一封装200,封装200通过接垫202和凸块126电连接到集成扇出型封装30,从而制造了叠层封装(POP)结构。
尽管以上描述了集成扇出型封装30,但应理解的是,本发明实施例不限于结构,因为可以在组件的材料和排列方面做出许多修改。下面描述了结构的一些可能的修改。
在一些实施例中,如图11E和图12所示,集成扇出型封装30/31包括半导体芯片100、凸块结构BS以及第一重分布层115。凸块结构BS电连接到半导体芯片100并且包括焊料凸块126、电连接到焊料凸块126的金属垫125(例如镍接垫)以及在焊料凸块126与金属垫125之间的金属间化合物层IMC1/IMC2。第一重分布层115位于凸块结构BS与半导体芯片100之间,并且包括晶种层114a和连接到晶种层114a的金属层116。
在一些实施例中,每个凸块结构BS还包括胶层127,胶层127位于金属垫125与金属间化合物层IMC1之间。在一些实施例中,胶层127的边缘实质上与金属垫125的边缘对齐。在一些实施例中,金属间化合物层IMC1是金-锡金属间化合物层。
在一些实施例中,集成扇出型封装30/31还包括阻障层102,且阻障层102配置成从焊料凸块126的侧壁延伸。在一些实施例中,阻障层102与第一重分布层115的晶种层114a实体接触,阻障层102延伸超过第一重分布层115的边缘。
在一些实施例中,凸块结构BS的金属垫125与第一重分布层115的晶种层114a实体接触。在一些实施例中,第一重分布层115与金属垫125的全部顶面实体接触,如图11F的集成扇出型封装30所示。
在一些实施例中,如图12所示,焊料凸块126可以完全消耗胶层127(例如金层),并且可以与金和镍反应以在焊料凸块126与金属垫125之间形成金属间化合物层IMC2。在一些实施例中,金属间化合物层IMC2是镍-金-锡金属间化合物层。
基于上述,在焊料凸块与背侧重分布层之间引入金属垫(例如Cu/Ni/Au或Ni/Au堆叠),所以焊料凸块不会消耗背侧重分布层而生成金属间化合物(IMC)等等,因此可提高封装的可靠度。利用本发明实施例的方法,形成凸块结构不需要传统的焊料膏(solderpaste)或助焊剂(flux),因此可以延长等待时间(Q-time)以在生产流程中提供更大的灵活性。
根据本发明的一些实施例,一种集成扇出型封装包括凸块结构、聚合物层以及金属层。凸块结构包括金属垫以及与金属垫电连接的凸块。聚合物层从凸块的侧壁侧向延伸。金属层覆盖凸块结构并与金属垫的侧表面实体接触。
在一些实施例中,所述金属层包封所述金属垫的所述侧表面和顶面。在一些实施例中,所述凸块结构还包括在所述金属垫与所述凸块之间的金属间化合物层,并且所述金属间化合物层包括金。在一些实施例中,所述金属间化合物层包括金-锡金属间化合物层或镍-金-锡金属间化合物层。在一些实施例中,所述金属间化合物层更延伸于所述金属层与所述聚合物层之间。在一些实施例中,还包括在所述金属间化合物层与所述聚合物层之间的阻障层。在一些实施例中,所述金属垫包括镍、铜或其组合。在一些实施例中,所述凸块结构还包括在所述金属垫与所述凸块之间以及在所述聚合物层与所述金属层之间的胶层。在一些实施例中,在所述金属垫与所述凸块之间的所述胶层较厚,而在所述聚合物层与所述金属层之间的所述胶层较薄。在一些实施例中,还包括与所述金属层电连接的集成扇出型穿孔。
根据本发明的另一些实施例,集成扇出型封装包括半导体芯片、凸块结构以及第一重分布层。凸块结构电连接到半导体芯片并包括焊料凸块、镍接垫以及金属间化合物层。镍接垫电连接到焊料凸块。金属间化合物层在焊料凸块与镍接垫之间,其中金属间化合物层包括金。第一重分布层在凸块结构与半导体芯片之间。
在一些实施例中,所述第一重分布层与所述镍接垫的部分顶面实体接触。在一些实施例中,所述第一重分布层与所述镍接垫的全部顶面实体接触。在一些实施例中,所述凸块结构还包括所述镍接垫与所述金属间化合物层之间的胶层。在一些实施例中,所述第一重分布层包括晶种层以及连接到所述晶种层的金属层,且所述凸块结构的所述金属垫与所述第一重分布层的所述晶种层实体接触。在一些实施例中,还包括阻障层,所述阻障层与所述金属间化合物层实体接触且围绕所述焊料凸块。在一些实施例中,所述金属间化合物层包括金-锡金属间化合物层或镍-金-锡金属间化合物层,并且所述阻障层包括Ti、W、Cr、TiW或其组合。
根据本发明的替代实施例,形成集成扇出型封装的方法包括以下操作。提供载板,所述载板上形成有聚合物层和胶层。使用所述胶层作为晶种层在载板上镀覆多个金属垫。使用所述胶层作为晶种层在金属垫上镀覆第一重分布层。移除载板。形成多个凸块,所述凸块穿过聚合物层并与金属垫电连接。
在一些实施例中,于镀覆所述第一重分布层之后以及移除所述载板之前,所述方法还包括:形成多个集成扇出穿孔,所述集成扇出穿孔与所述金属垫电连接;在所述载板上以及所述集成扇出穿孔侧边放置半导体芯片;以及在所述半导体芯片上形成第二重分布层结构。在一些实施例中,还包括在所述胶层与所述聚合物层之间形成阻障层。
也可包括其他特征及工艺。举例来说,可包括测试结构,以说明对三维封装或三维集成电路装置进行验证测试。所述测试结构可例如包括在重分布层中或在衬底上形成的测试接垫(testpad),以便能够对三维封装或三维集成电路进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外,可将本文中所公开的结构及方法与包括对已知良好晶粒(known good die)进行中间验证的测试方法结合使用,以提高良率并降低成本。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解,其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本公开的精神及范围,而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。
Claims (25)
1.一种集成扇出型封装,其特征在于,包括:
凸块结构包括:
金属垫;以及
凸块,电连接到所述金属垫;
介电层,从所述凸块的侧壁侧向延伸;以及
重分布层,包括金属层和聚合物层,所述聚合物层包覆所述金属层,其中所述金属垫位在所述金属层与所述凸块之间,且所述金属层与所述金属垫的侧表面实体接触,
其中所述凸块结构还包括在所述金属垫与所述凸块之间的金属间化合物层,并且所述金属间化合物层包括金,且
阻障层,在所述金属间化合物层与所述介电层之间。
2.根据权利要求1所述的集成扇出型封装,其特征在于,所述金属层包封所述金属垫的全部所述侧表面和顶面。
3.根据权利要求1所述的集成扇出型封装,其特征在于,所述金属间化合物层与所述金属层实体接触。
4.根据权利要求1所述的集成扇出型封装,其特征在于,所述金属间化合物层侧向延伸以远离所述凸块。
5.根据权利要求1所述的集成扇出型封装,其特征在于,所述金属垫包括镍、铜或其组合。
6.根据权利要求1所述的集成扇出型封装,其特征在于,所述金属间化合物层还延伸至所述介电层与所述金属层之间,在所述金属垫与所述凸块之间的所述金属间化合物层较厚,而在所述介电层与所述金属层之间的所述金属间化合物层较薄。
7.根据权利要求1所述的集成扇出型封装,其特征在于,还包括与所述金属层电连接的集成扇出型穿孔。
8.一种集成扇出型封装,其特征在于,包括:
半导体芯片;
凸块结构,电连接到所述半导体芯片并包括:
焊料凸块;
镍接垫,电连接到所述焊料凸块;以及
金属间化合物层,在所述焊料凸块与所述镍接垫之间,其中所述金属间化合物层包括金;以及
第一重分布层,在所述凸块结构与所述半导体芯片之间,
其中所述集成扇出型封装还包括从所述焊料凸块的侧壁侧向延伸的阻障层。
9.根据权利要求8所述的集成扇出型封装,其特征在于,所述第一重分布层与所述镍接垫的部分顶面实体接触。
10.根据权利要求8所述的集成扇出型封装,其特征在于,所述第一重分布层与所述镍接垫的全部顶面实体接触。
11.根据权利要求8所述的集成扇出型封装,其特征在于,所述凸块结构还包括在所述镍接垫与所述金属间化合物层之间的胶层。
12.根据权利要求8所述的集成扇出型封装,其特征在于,所述第一重分布层包括晶种层以及连接到所述晶种层的金属层,且所述凸块结构的金属垫与所述第一重分布层的所述晶种层实体接触。
13.根据权利要求8所述的集成扇出型封装,其特征在于,所述阻障层与所述金属间化合物层实体接触且围绕所述焊料凸块。
14.根据权利要求8所述的集成扇出型封装,其特征在于,所述金属间化合物层包括金-锡金属间化合物层或镍-金-锡金属间化合物层,并且所述阻障层包括Ti、W、Cr、TiW或其组合。
15.一种形成集成扇出型封装的方法,其特征在于,包括:
提供载板,所述载板上形成有介电层和胶层;
使用所述胶层作为晶种层,以在所述载板上镀覆多个金属垫;
使用所述胶层作为晶种层,以在所述金属垫上镀覆第一重分布层,
其中所述第一重分布层中的每一个金属层与每个所述金属垫的全部侧表面实体接触;
形成包覆所述金属层的聚合物层;
移除所述载板;以及
形成多个凸块,所述凸块穿过所述介电层并与所述金属垫电连接。
16.根据权利要求15所述的形成集成扇出型封装的方法,其特征在于,在镀覆所述第一重分布层之后以及移除所述载板之前,所述方法还包括:
形成多个集成扇出穿孔,所述集成扇出穿孔与所述金属垫电连接;
在所述载板上以及所述集成扇出穿孔侧边放置半导体芯片;以及
在所述半导体芯片上形成第二重分布层结构。
17.根据权利要求15所述的形成集成扇出型封装的方法,其特征在于,还包括在所述胶层与所述介电层之间形成阻障层。
18.一种集成扇出型封装,其特征在于,包括:
半导体芯片;
第一重分布层结构,位在所述半导体芯片的背侧;以及
第二重分布层结构,位在所述半导体芯片的前侧,
其中所述第一重分布层结构包括聚合物层、金属垫以及金属层,所述金属层与所述金属垫的全部侧表面实体接触,所述聚合物层包覆所述金属层,
其中所述集成扇出型封装还包括凸块,位在半导体芯片的所述背侧且电连接到所述第一重分布层结构,且
其中所述集成扇出型封装还包括阻障层,所述阻障层从所述凸块的侧向延伸。
19.根据权利要求18所述的集成扇出型封装,其特征在于,所述金属层包封所述金属垫的所述侧表面和顶面。
20.根据权利要求18所述的集成扇出型封装,其特征在于,还包括:
金属间化合物层,位在所述金属垫与所述凸块之间,其中所述金属间化合物层包括金。
21.根据权利要求20所述的集成扇出型封装,其特征在于,所述金属间化合物层包括金-锡金属间化合物层、镍-金-锡金属间化合物层、铜-金-锡金属间化合物层或其组合。
22.根据权利要求20所述的集成扇出型封装,其特征在于,所述金属间化合物层还侧向延伸以远离所述凸块。
23.根据权利要求20所述的集成扇出型封装,其特征在于,所述金属间化合物层的边缘实质上与所述金属层的边缘对齐。
24.根据权利要求20所述的集成扇出型封装,其特征在于,所述金属间化合物层具有非均匀厚度。
25.根据权利要求20所述的集成扇出型封装,其特征在于,所述阻障层与所述金属间化合物层实体接触。
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CN109755207A (zh) | 2019-05-14 |
TW201919180A (zh) | 2019-05-16 |
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