CN109727939A - 重布线路结构 - Google Patents

重布线路结构 Download PDF

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Publication number
CN109727939A
CN109727939A CN201810339642.2A CN201810339642A CN109727939A CN 109727939 A CN109727939 A CN 109727939A CN 201810339642 A CN201810339642 A CN 201810339642A CN 109727939 A CN109727939 A CN 109727939A
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China
Prior art keywords
conductive
layer
dielectric layer
conductive layer
mask
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CN201810339642.2A
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English (en)
Inventor
杜尚耘
萧景文
吴胜郁
陈清晖
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109727939A publication Critical patent/CN109727939A/zh
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract

本发明的实施例公开一种重布线路结构。重布线路结构包括第一导电结构、介电层及第二导电结构。介电层设置在所述第一导电结构之上且暴露出所述第一导电结构的一部分。第二导电结构设置在所述介电层中以电连接到所述第一导电结构，且包括第一导电层及第二导电层，所述第二导电层设置在所述第一导电层上且电连接到所述第一导电层，其中所述第一导电层包括上表面，所述上表面在整个边缘处具有突起部。

Description

重布线路结构
技术领域
本发明的实施例涉及一种重布线路结构。
背景技术
在集成电路(integrated circuit，IC)的制造期间，依序实行半导体制造工艺的多步骤以在半导体工件上逐渐地形成电子电路。光刻(lithography)是此种半导体制造工艺中的一个步骤。光刻是将几何图案转移到半导体工件的工艺。光刻可通过例如光刻法(photolithography)、带电粒子光刻(charged particle lithography)或纳米压印光刻(nanoimprint lithography)来实行。
发明内容
本发明实施例的一种重布线路结构包括第一导电结构、介电层及第二导电结构。介电层设置在所述第一导电结构之上且暴露出所述第一导电结构的一部分。第二导电结构设置在所述介电层中以电连接到所述第一导电结构，且包括第一导电层及第二导电层，所述第二导电层设置在所述第一导电层上且电连接到所述第一导电层，其中所述第一导电层包括上表面，所述上表面在整个边缘处具有突起部。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的临界尺寸(critical dimension)。
图1示出流程图，其示出根据本发明一些实施例的形成集成扇出(integratedfan-out，INFO)封装的方法。
图2A至图2G是示出根据本发明一些实施例的集成扇出(INFO)封装的制造工艺的示意性剖视图。
图2H是示出根据本发明一些实施例的叠层封装(package-on-package，PoP)结构的剖视图。
图3示出流程图，其示出根据本发明一些实施例的形成重布线路结构的方法。
图4A至图4H是示出根据本发明一些实施例的图2D中所绘示重布线路结构的制造工艺的剖视图。
图5是示出根据本发明一些实施例的图4H中所绘示重布线路结构的俯视图。
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本发明。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第二特征形成于第一特征“之上”或第一特征“上”可包括其中第二特征及第一特征被形成为直接接触的实施例，且也可包括其中第二特征与第一特征之间可形成有附加特征、进而使得所述第二特征与所述第一特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“位于…上(on)”、“位于…之上(over)”、“上覆的(overlying)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)且本文中所使用的空间相对性描述语可同样相应地进行解释。
另外，为易于说明，本文中可使用例如“第一”、“第二”、“第三”、“第四”等用语来阐述图中所示的相似或不同的元件或特征，且可依据存在的次序或说明的上下文而互换地使用。
也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(three-dimensional，3D)封装或三维集成电路(3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫，以容许对三维封装或三维集成电路进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯进行中间验证的测试方法而使用，以提高良率(yield)及降低成本。
图1示出流程图，其示出根据本发明一些实施例的形成INFO封装的方法。图2A至图2G是示出根据本发明一些实施例的集成扇出(INFO)封装的制造工艺的示意性剖视图。参照图1及图2A，在步骤S100处，提供载体C，且在载体C之上形成导电柱102及集成电路104。在载体C之上依序堆叠剥离层DB及介电层DI。在一些实施例中，剥离层DB形成在载体C的上表面上，且剥离层DB位于载体C与介电层DI之间。载体C为例如玻璃衬底。另一方面，在一些实施例中，剥离层DB为形成在玻璃衬底上的光热转换(light-to heat-conversion，LTHC)释放层。在一些实施例中，介电层DI例如为聚合物，例如聚酰亚胺(polyimide，PI)、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzoxazole，PBO)或类似物。在一些替代实施例中，介电层DI可包含无机介电材料，例如氧化硅、氮化硅、碳化硅、氮氧化硅或类似物。然而，剥离层DB、载体C及介电层DI的所述材料仅用于说明，且本发明并非仅限于此。
在介电层DI之上设置多个预先制作的导电柱102及多个预先制作的集成电路104。集成电路104被安装到上面形成有导电柱102的介电层DI上。集成电路104与介电层DI之间具有用于将集成电路104粘着到介电层DI上的管芯贴合膜(die attach film，DAF)(图中未示出)。集成电路104排列成阵列且被导电柱102环绕。集成电路104例如为半导体管芯。集成电路104中的每一者包括有源表面104a、分布在有源表面104a上的多个接垫104b、覆盖有源表面104a的钝化层104c、多个导电柱104d及保护层104e。接垫104b被钝化层104c局部地暴露出，导电柱104d设置在接垫104b上且电连接到接垫104b，且保护层104e覆盖导电柱104d及钝化层104c。导电柱104d例如为铜柱或其他适合的金属柱。在一些实施例中，保护层104e可为聚苯并恶唑(PBO)层、聚酰亚胺(PI)层或其他适合的聚合物。在一些替代实施例中，保护层104e可由无机材料制成。如图2A中所示，集成电路104的顶表面低于导电柱102的顶表面。然而，本发明并非仅限于此。在一些替代实施例中，集成电路104的顶表面可与导电柱102的顶表面实质上共面。
参照图1及图2B，在步骤S200处，形成绝缘材料106以包封导电柱102及集成电路104。在一些实施例中，绝缘材料106是通过模塑工艺(molding process)在介电层DI上形成的模塑化合物(molding compound)。集成电路104的导电柱102及保护层104e被绝缘材料106包封。换句话说，集成电路104的导电柱102及保护层104e未被显露出且被绝缘材料106完善地保护。在一些实施例中，绝缘材料106可包括环氧树脂(epoxy)或其他适合的材料。
参照图1及图2C，在步骤S300处，对绝缘材料106进行研磨直到暴露出集成电路104的顶表面，以形成绝缘包封体106’。在一些实施例中，对集成电路104的绝缘材料106及保护层104e进行研磨直到暴露出导电柱104d的顶表面。在绝缘材料106被研磨之后，在介电层DI之上形成绝缘包封体106’。在前述研磨工艺期间，还对保护层104e的一些部分进行研磨以形成保护层104e’。在一些实施例中，在绝缘材料106及保护层104e的前述研磨工艺期间，对导电柱104d的一些部分及导电柱102的一些部分进行研磨直到导电柱104d的顶表面及导电柱102的顶表面暴露出。换句话说，绝缘包封体106’暴露出集成电路104的至少一部分及导电柱102的至少一部分。在一些实施例中，可通过机械研磨(mechanical grinding)、化学机械抛光(chemical mechanical polishing，CMP)或另一种适合的机制来形成绝缘包封体106’。
绝缘包封体106’包封集成电路104的侧壁，且绝缘包封体106’被导电柱102穿透。换句话说，集成电路104及导电柱102嵌置在绝缘包封体106’中。应注意，尽管集成电路104及导电柱102嵌置在绝缘包封体106’中，然而绝缘包封体106’仍暴露出集成电路104的顶表面及导电柱102的顶表面。换句话说，导电柱102的顶表面、保护层104e’的顶表面及导电柱104d的顶表面与绝缘包封体106’的顶表面实质上共面。
参照图1及图2D，在步骤S400处，在导电柱102、绝缘包封体106’及集成电路104上形成重布线路结构108。在一些实施例中，在形成绝缘包封体106’及保护层104e’之后，在导电柱102的顶表面、绝缘包封体106’的顶表面、导电柱104d的顶表面及保护层104e’的顶表面上形成与集成电路104的导电柱104d以及导电柱102电连接的重布线路结构108。如图2D中所示，重布线路结构108包括交替堆叠的多个层间介电层108a及多个重布线导电图案108b。重布线导电图案108b电连接到集成电路104的导电柱104d及嵌置在绝缘包封体106’中的导电柱102。在一些实施例中，导电柱104d的顶表面及导电柱102的顶表面与重布线路结构108的最底重布线导电图案108b接触。导电柱104d的顶表面及导电柱102的顶表面被最底层间介电层108a局部地覆盖。此外，最顶重布线导电图案108b包括多个接垫。在一些实施例中，前述接垫包括用于球安装(ball mount)的多个球下金属(under-ball metallurgy，UBM)图案108b1及/或用于安装无源组件的至少一个连接接垫108b2。球下金属图案108b1及连接接垫108b2的数目在本发明中并无限制。
以下将呈现重布线路结构108的至少一部分的详细形成方法。图3示出流程图，其示出根据本发明一些实施例的形成重布线路结构的方法。图4A至图4H是示出根据本发明一些实施例的图2D中所绘示重布线路结构108的制造工艺的剖视图。应注意，图4A至图4H中所绘示示意图仅充当示范实例。如此一来，图4A至图4H中所示比例(scale)、尺寸及形状可能无法完整地反映图2D中所示重布线路结构108。然而，通过相同的参考编号表示相同的元件以在图4A至图4H与图2D之间建立相关性。
参照图3及图4A，在步骤S410处，在导电结构CS之上形成层间介电层108a，其中层间介电层108a包括接触开口108c以暴露出导电结构CS的一部分。在一些实施例中，导电结构CS可为重布线导电图案108b中的一者。然而，本发明并非仅限于此。在一些替代实施例中，层间介电层108a可为最底层间介电层108a，且导电结构CS可为导电柱102或导电柱104d。在一些实施例中，如图2D中所示，在层间介电层108a中形成多个接触开口108c以使导电结构CS与后续形成的导电材料之间进行电连接。在一些实施例中，层间介电层108a可为单层式结构或多层式结构。层间介电层108a可具有为近似10微米(μm)至近似30μm的厚度。
参照图4B，在层间介电层108a之上形成障壁层210。在一些实施例中，障壁层210共形地设置在层间介电层108a之上。即，障壁层210延伸到接触开口108c中以覆盖接触开口108c的底表面及侧壁。障壁层210可包含例如钛、氮化钛、钽、氮化钽、其他适合的材料或其组合。在一些实施例中，通过物理气相沉积(physical vapor deposition)或其他可适用方法形成障壁层210。障壁层210可具有为近似0.01μm至近似1μm的厚度。在一些替代实施例中，可省略障壁层210。
参照图3及图4C，在步骤420处，在层间介电层108a之上形成掩模M1以覆盖接触开口108c的上部部分109b。在一些实施例中，掩模M1形成在障壁层210上以覆盖接触开口108c的上部部分109b，且具有与接触开口108c的下部部分109a对应的开口OP1。如以上所提及，障壁层210共形地设置到接触开口108c中，且因此开口OP1暴露出障壁层210的位于接触开口108c的下部部分109a之上的至少一部分。在一些实施例中，掩模M1可由光刻胶或干膜(dry film)形成。
参照图3及图4D，在步骤S430处，通过使用掩模M1作为掩模，在接触开口108c的下部部分109a中形成导电层230。在一些实施例中，导电层230形成在与接触开口108c的下部部分109a对应的开口OP1中。在一些实施例中，可通过镀覆工艺(plating process)来形成导电层230。所述镀覆工艺例如为电镀(electro-plating)、无电镀覆(electroless-plating)、浸镀(immersion plating)或类似工艺。所述导电材料例如为铜、铜合金或类似物。在一些实施例中，下部部分109a的深度为接触开口108c的深度的约一半，且本发明并非仅限于此。在一些替代实施例中，可在障壁层210与导电层230之间形成晶种层。
参照图3及图4E，在步骤S440处，在形成导电层230之后，移除掩模M1。在一些实施例中，导电层230包括上表面，所述上表面在整个边缘处具有突起部232。举例来说，突起部232的外壁232a实质上垂直于导电结构CS的被暴露出的表面。在一些实施例中，举例来说，导电层230的上表面与突起部232的内壁232b之间的夹角θ为钝角。在一些实施例中，其剖视图为三角形。然而，本发明并非仅限于此。换句话说，导电层230可具有其他轮廓，所述其他轮廓实质上对应于掩模M1的开口OP1的轮廓。举例来说，在一些替代实施例中，突起部232可具有平的上表面，且其剖视图为梯形。在一些替代实施例中，突起部232可具有圆化的上表面。在一些实施例中，通过剥除方法(stripping method)移除掩模M1。
参照图3及图4F，在步骤S450处，在层间介电层108a之上形成掩模M2，掩模M2不覆盖接触开口108c。将掩模M2图案化以形成开口OP2，开口OP2对应于接触开口108c。在一些实施例中，开口OP2暴露出位于接触开口108c的下部部分109a中的导电层230及位于接触开口108c的上部部分109b中的障壁层210。在一些实施例中，掩模M2还可包括多个图案MP及位于层间介电层108a之上的相邻图案MP之间的至少一个开口OP3，且因此开口OP3还暴露出障壁层210的位于层间介电层108a之上的一部分。此外，举例来说，掩模M2的图案MP的宽度及位于层间介电层108a之上的掩模M2的开口OP3的宽度可分别不大于10μm。在一些实施例中，掩模M2可由光刻胶或干膜形成。在一些实施例中，上部部分109b的深度实质上等于下部部分109a的深度。在一些实施例中，上部部分109b的深度为接触开口108c的深度的约一半，且本发明并非仅限于此。
参照图3及图4G，在步骤S460处，通过使用掩模M2作为掩模，在导电层230上在接触开口108c的上部部分109b中形成导电层240，以形成包括导电层230、240在内的导电结构。在一些实施例中，形成导电材料以覆盖导电层230，以形成重布线导电图案108b。在一些实施例中，导电材料包括导电层240，且导电层240填充在接触开口108c的位于导电层230之上的上部部分109b中且在层间介电层108a的一部分之上延伸。在一些实施例中，导电层240与在边缘处具有突起部232的导电层230以及接触开口108c的上部部分109b共形地形成。另外，导电材料还可包括形成在开口OP3中的导电图案242。在一些实施例中，举例来说，导电图案242的宽度不大于10μm。在一些实施例中，可通过镀覆工艺来形成导电层240。所述镀覆工艺例如为电镀、无电镀覆、浸镀或类似工艺。所述导电材料例如为铜、铜合金或类似物。重布线导电图案108b包括导电层230及导电层240，且导电层230与导电层240之间形成有界面。
参照图3及图4H，在步骤S470处，在形成导电层240之后，随后移除掩模M2。在一些实施例中，通过剥除方法移除掩模M2。接着，使用导电层240及导电图案242作为掩模来移除障壁层210的一部分。在一些实施例中，通过干法刻蚀工艺(dry etching process)或湿法刻蚀工艺(wet etching process)移除障壁层210。
在一些实施例中，如图4H中所示，尽管层间介电层108a的侧壁不具有台阶结构(step structure)，然而重布线导电图案108b的上表面包括具有三个台阶ST1、ST2、ST3的台阶结构ST。另外，如图5中所示，由于台阶ST1、ST2、ST3的高度不同，因此在俯视图中，台阶结构ST包括分别由台阶ST1、ST2、ST3形成的三个圆，且本发明并非仅限于此。在一些替代实施例中，当导电层230还在上表面中包括至少一个凹陷部时(此意指在所述上表面中形成有多于两个不同的高度)，重布线导电图案108b的台阶结构ST可例如具有多于三个台阶。
在一些实施例中，从导电层230的最低部分到导电层230的最高部分的距离D1实质上等于从导电层240的最低部分到导电层240的最高部分的距离D2。在一些实施例中，举例来说，从导电层230的底部到导电层240的最低上表面的厚度T1对导电层240的在层间介电层108a之上延伸的一部分的厚度T2的比率大于1.5。在一些实施例中，导电层240的厚度T2大于5μm。另外，层间介电层108a及位于层间介电层108a上的导电层240的总厚度T3比导电结构CS的被层间介电层108a暴露出的一部分的宽度W1大两倍。在一些实施例中，导电图案242的宽度W2小于导电结构CS的一部分的宽度W1，且导电图案242的宽度W2实质上等于导电图案242与导电层240之间或相邻导电图案242之间的线间距S。一般来说，元件的前述厚度、宽度或高度可能增加在开口中落放(land)导电图案的难度，此意指显影不足(underdevelopment)的风险增大。然而，在一些实施例中，由于重布线导电图案是通过两种沉积工艺或镀覆工艺形成，因此将导电材料填充到深的开口中的难度降低，且分辨率提高。因此，焦深(depth of focus，DOF)的窗口被放大。另外，在一些实施例中，导电图案(例如导电图案242)的线宽及线间距减小，且因此用于设置所述导电图案的区域可减小。因此，重布线路结构的性能提高。
在一些实施例中，重布线路结构108为单层式结构。因此，在实行图4A至图4H中所示步骤之后，重布线路结构108实质上完成。然而，在一些替代实施例中，重布线路结构108为多层式结构(例如，图2D中所示重布线路结构108)。在此种条件下，可将图4A至图4H中所示步骤重复进行若干次，以形成重布线路结构108。
应注意，图4A至图4H中所绘示步骤并非仅限于制作图2D中所示重布线路结构108。可在位于封装中其他位置处的重布线路结构中使用前述步骤。举例来说，可在位于集成电路内的重布线路结构中采用前述步骤。在一些替代实施例中，可使用前述步骤来制造UBM。
重新参照图1及图2E，在步骤S500处，在重布线路结构108的第一侧之上形成导电端子110及无源组件112。在一些实施例中，在形成重布线路结构108之后，在球下金属图案108b1上放置多个导电端子110，且在连接接垫108b2上安装多个无源组件112。在一些实施例中，可通过植球工艺(ball placement process)或其他适合的工艺在球下金属图案108b1上放置导电端子110，且可通过焊接工艺(soldering process)、回流工艺(reflowingprocess)或其他适合的工艺在连接接垫108b2上安装无源组件112。
参照图1及图2F，在步骤S600处，移除载体C。在一些实施例中，在重布线路结构108上安装导电端子110及无源组件112之后，将形成在绝缘包封体106’的底表面上的介电层DI从剥离层DB剥离，使得介电层DI与载体C分离。即，载体C被移除。在一些实施例中，可通过紫外(ultra-violet，UV)激光照射剥离层DB(例如，LTHC释放层)，使得粘着在绝缘包封体106’的底表面上的介电层DI从载体C剥落。如图2F中所示，接着将介电层DI图案化，使得形成局部地暴露出导电柱102的多个接触开口O。接触开口O的数目对应于导电柱102的数目。在一些实施例中，通过激光钻孔工艺(laser drilling process)、机械钻孔工艺(mechanicaldrilling process)或其他适合的工艺形成介电层DI的接触开口O。
参照图1及图2G，在步骤S700处，在重布线路结构108的与第一侧相对的第二侧之上形成导电端子114，以形成INFO封装10。在一些实施例中，在介电层DI中形成接触开口O之后，在接触开口O中放置多个导电端子114，且将导电端子114电连接到导电柱102。此处，集成扇出(INFO)封装阵列的形成实质上完成。如图2G中所示，在形成导电端子110及导电端子114之后，对INFO封装阵列进行切割以形成具有双侧端子设计的多个INFO封装10。在一些实施例中，切割工艺(dicing process)或单体化工艺(singulation process)通常涉及以旋转刀片或激光束进行切割。换句话说，切割工艺或单体化工艺例如为激光切削工艺(lasercutting process)、机械切削工艺(mechanical cutting process)或其他适合的工艺。
图2H是示出根据本发明一些实施例的叠层封装(PoP)结构的剖视图。在一些实施例中，INFO封装10可与其他电子装置进行堆叠。举例来说，参照图1及图2H，在步骤S800处，在INFO封装10上堆叠另一封装20且通过导电端子114将所述另一封装20电连接到INFO封装10，以形成叠层封装(PoP)结构。在一些实施例中，封装20例如为IC封装。应注意，图2H仅充当示例性说明，且本发明并非仅限于此。在一些替代实施例中，INFO封装10可与其他电子装置(例如另一INFO封装、存储装置、球栅阵列封装(ball grid array，BGA)或晶片)进行堆叠。此外，可在切割工艺之前实行堆叠。举例来说，可将图2G中所示INFO封装阵列与晶片堆叠，且可同时对经堆叠的所述INFO封装阵列与所述晶片实行单体化工艺。
根据本发明的一些实施例，一种重布线路结构包括第一导电结构、介电层及第二导电结构。介电层设置在所述第一导电结构之上且暴露出所述第一导电结构的一部分。第二导电结构设置在所述介电层中以电连接到所述第一导电结构，且包括第一导电层及第二导电层，所述第二导电层设置在所述第一导电层上且电连接到所述第一导电层，其中所述第一导电层包括上表面，所述上表面在整个边缘处具有突起部。
根据本发明的一些实施例，所述突起部的外壁实质上垂直于所述第一导电结构的暴露表面。
根据本发明的一些实施例，所述第一导电层的上表面与所述突起部的内壁之间的夹角是钝角。
根据本发明的一些实施例，所述第二导电层的一部分还在所述介电层之上延伸。
根据本发明的一些实施例，从所述第一导电层的底部到所述第二导电层的最低上表面的厚度对所述第二导电层的在所述介电层之上延伸的所述一部分的厚度的比率大于1.5。
根据本发明的一些实施例，所述介电层及所述第二导电层的在所述介电层之上延伸的所述一部分的总厚度比所述第一导电结构的被所述介电层暴露出的所述一部分的宽度大两倍。
根据本发明的一些实施例，从所述第一导电层的最低部分到所述第一导电层的最高部分的距离实质上等于从所述第二导电层的最低部分到所述第二导电层的最高部分的距离。
根据本发明的一些实施例，在所述第一导电层与所述第二导电层之间形成有界面。
根据本发明的一些实施例，还包括位于所述第二导电结构与所述介电层之间以及位于所述第二导电结构与所述第一导电结构之间的障壁层。
根据本发明的替代实施例，一种重布线路结构包括第一导电结构、介电层及第二导电结构。介电层设置在所述第一导电结构之上且暴露出所述第一导电结构的一部分。第二导电结构设置在所述介电层中以电连接到所述第一导电结构，其中所述第二导电结构的上表面包括具有至少三个台阶的台阶结构。
根据本发明的一些实施例，所述台阶结构包括三个台阶。
根据本发明的一些实施例，从所述第一导电结构的上表面到所述第二导电结构的最低上表面的厚度对位于所述介电层之上的所述第二导电结构的一部分的厚度的比率大于1.5。
根据本发明的一些实施例，所述介电层不具有台阶结构。
根据本发明的一些实施例，还包括位于所述第二导电结构与所述介电层之间以及位于所述第二导电结构与所述第一导电结构之间的障壁层。
根据本发明的又一些替代实施例，一种形成重布线路结构的方法包括以下步骤。在第一导电结构之上形成介电层，其中所述介电层包括第一开口，所述第一开口暴露出所述第一导电结构的一部分。在所述介电层之上形成第一掩模，以覆盖所述第一开口的上部部分。通过使用所述第一掩模作为掩模，在所述第一开口的下部部分中形成第一导电层。移除所述第一掩模。在所述介电层之上形成第二掩模，所述第二掩模不覆盖所述第一开口。通过使用所述第二掩模作为掩模，在所述第一导电层上在所述第一开口的所述上部部分中形成第二导电层，以形成包括所述第一导电层及所述第二导电层的第二导电结构。移除所述第二掩模。
根据本发明的一些实施例，所述方法还包括：在所述第二导电结构与所述介电层之间以及在所述第二导电结构与所述第一导电结构之间形成障壁层。
根据本发明的一些实施例，所述第二掩模的至少一个第三开口形成在所述介电层之上。
根据本发明的一些实施例，所述第二导电层还形成在所述至少一个第三开口中。
根据本发明的一些实施例，所述第一开口的所述下部部分的深度实质上等于所述第一开口的所述上部部分的深度。
根据本发明的一些实施例，所述第一导电层包括上表面，所述上表面在整个边缘处具有突起部。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种重布线路结构，其特征在于，包括：
第一导电结构；
介电层，设置在所述第一导电结构之上且暴露出所述第一导电结构的一部分；以及
第二导电结构，设置在所述介电层中以电连接到所述第一导电结构，且包括第一导电层及第二导电层，所述第二导电层设置在所述第一导电层上且电连接到所述第一导电层，其中所述第一导电层包括上表面，所述上表面在整个边缘处具有突起部。
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