CN109688724A - 半导体装置组合件及形成所述半导体装置组合件的方法 - Google Patents
半导体装置组合件及形成所述半导体装置组合件的方法 Download PDFInfo
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- CN109688724A CN109688724A CN201811134097.XA CN201811134097A CN109688724A CN 109688724 A CN109688724 A CN 109688724A CN 201811134097 A CN201811134097 A CN 201811134097A CN 109688724 A CN109688724 A CN 109688724A
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01R12/778—Coupling parts carrying sockets, clips or analogous counter-contacts
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/87—Electrodes or interconnections, e.g. leads or terminals
- H10N30/875—Further connection or lead arrangements, e.g. flexible wiring boards, terminal pins
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
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- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
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- H01R12/716—Coupling device provided on the PCB
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
Abstract
本申请案涉及半导体装置组合件及形成所述半导体装置组合件的方法。一种半导体装置组合件,其包含柔性构件,所述柔性构件具有连接到衬底的第一部分及附接到所述柔性构件的第二部分的连接器。所述连接器经由所述柔性构件内的导电层电连接到所述衬底。所述衬底可为半导体装置,例如芯片。所述连接器可经配置以将所述半导体装置连接到另一半导体装置组合件或系统板,例如印刷电路板。材料可囊封所述半导体组合件的所述衬底的至少一部分。可通过选择性地将所述柔性构件连接到第一衬底来形成所述半导体装置组合件。然后可将第二衬底及连接器连接到所述柔性构件。释放层可用于从所述第一衬底释放所述第二衬底、柔性构件及连接器的所述组合件。
Description
技术领域
本文描述的实施例涉及一种柔性构件,其具有连接到衬底的连接器,所述衬底可为半导体装置,例如(但不限于)硅晶片的单个裸片、集成电路、单片集成电路、半导体芯片或微芯片。连接器远离衬底定位,但经由柔性构件电连接到衬底。
背景技术
半导体处理及封装技术持续演进以满足对提高性能及减小大小的工业需求。例如蜂窝电话、智能电话、平板计算机、个人数字助理、膝上型计算机以及其它电子装置的电子产品需要具有高装置密度同时具有相对小的占据面积的封装半导体组合件。小型化的半导体装置组合件通常焊接安装到装置内的系统板上,例如印刷电路板。将半导体装置组合件焊接安装到板上使几乎不可能在不实际损坏半导体装置组合件的情况下拆卸半导体装置组合件。因此,如果半导体装置组合件停止工作,那么整个板也停止工作。在仅半导体装置组合件不能正常工作的情况下,可能需要更换整个板或甚至更换整个装置。可能存在额外缺陷及缺点。
发明内容
在一个方面中,本发明提供一种半导体装置组合件,其包括:衬底,其具有第一表面及第二表面;柔性构件,其具有导电层,所述柔性构件连接到所述衬底的所述第二表面,所述柔性构件具有邻近所述衬底的第一部分及远离所述衬底定位的第二部分;及连接器,其位于所述柔性构件的所述第二部分上,其中所述连接器经由所述柔性构件的所述导电层电连接到所述衬底的电连接件。
在另一方面中,本发明提供一种半导体装置组合件,其包括:第一衬底;所述第一衬底的表面上的释放层;柔性构件,其具有导电层,其中所述释放层选择性地将所述柔性构件结合到所述第一衬底的所述表面;连接器,其连接到所述柔性构件的一部分,所述连接器电连接到所述柔性构件的所述导电层;及第二衬底,其电连接到所述柔性构件,所述连接器经由所述柔性构件的所述导电层电连接到所述第二衬底,其中所述释放层经配置以选择性地从所述第一衬底的所述第一表面释放所述柔性构件、连接器及第二衬底。
在进一步方面中,本发明提供一种形成半导体装置组合件的方法,所述方法包括:提供第一衬底;将柔性构件连接到所述第一衬底的表面,所述柔性构件包含导电层;将第二衬底连接到所述柔性构件,所述柔性构件的所述导电层电连接到所述第二衬底的电连接件,其中所述柔性构件定位在所述第一衬底的至少一部分与所述第二衬底的一部分之间;以及在所述柔性构件的一部分上提供连接器,所述连接器经由所述柔性构件的所述导电层电连接到所述第二衬底的所述电连接件。
附图说明
图1是半导体装置组合件的实施例的示意性横截面图。
图2是连接到印刷电路板的半导体装置组合件的实施例的示意性顶视图。
图3是半导体装置组合件的实施例的示意性横截面图,所述半导体装置组合件包含连接到第一衬底的柔性构件。
图4是半导体装置组合件的实施例的示意性横截面图,所述半导体装置组合件包含连接到柔性构件的第二衬底,所述柔性构件连接到第一衬底。
图5是半导体装置组合件的实施例的示意性横截面图,所述半导体装置组合件包含囊封连接到柔性构件的第二衬底的至少一部分的材料,所述柔性构件连接到第一衬底。
图6是半导体装置组合件的实施例的示意性横截面图,所述半导体装置组合件包含柔性构件,所述柔性构件具有定位在第一衬底与第二衬底之间的连接器。
图7是连接到从第一衬底移除的柔性构件的第二衬底的半导体装置组合件的实施例的示意性横截面图。
图8是载体衬底上的多个半导体装置组合件的实施例的示意图。
图9是形成半导体装置组合件的方法的一个实施例的流程图。
虽然本发明易于进行各种修改及替代形式,但在图式中通过实例的方式展示特定实施例,并且将在本文中对其进行详细描述。然而,应理解,本发明不希望限于所揭示的特定形式。而是,希望覆盖落入由所附权利要求书界定的本发明范围内的所有修改、等效物及替代物。
具体实施方式
在本发明中,论述众多特定细节以提供对本发明的实施例的全面及有利的描述。所属领域的一般技术人员将认识到,可在没有特定细节中的一或多者的情况下实践本发明。通常与半导体装置相关联的众所周知的结构及/或操作可能未展示及/或可能未详细描述以避免模糊本发明的其它方面。一般来说,应理解,除本文揭示的那些特定实施例之外的各种其它装置、系统及/或方法可在本发明的范围内。
术语“半导体装置组合件”可指代一或多个半导体装置、半导体装置封装及/或衬底的组合件,其可包含插入物、支撑物及/或其它合适衬底。半导体装置组合件可制造为(但不限于)离散封装形式、条带或矩阵形式及/或晶片面板形式。术语“半导体装置”通常指代包含半导体材料的固态装置。半导体装置可包含(例如)半导体衬底、晶片、面板或来自晶片或衬底的单个裸片。半导体装置在本文可指代半导体晶片,但半导体装置不限于半导体晶片。
如本文所使用,术语“垂直”、“横向”、“上”及“下”可指代图中所展示的半导体装置中的特征的相对方向或位置。举例来说,“上”或“最上”可指代比另一特征更靠近页面顶部定位的特征。然而,这些术语应被广义地解释为包含具有其它定向的半导体装置及/或半导体装置组合件,例如倒置或倾斜定向,其中顶部/底部、上方/下方、上面/下面、上/下及左/右可根据定向互换。
本发明的各种实施例涉及半导体装置组合件,以及制造及/或操作半导体装置组合件的方法。在本发明的一个实施例中,半导体装置组合件包括衬底及具有连接层的柔性构件,柔性构件的第一部分连接到衬底的底表面。连接器附接到柔性构件的第二部分,其中连接器经由柔性构件内的导电层或迹线电连接到衬底。衬底可为半导体装置,例如硅晶片的单个裸片、集成电路、单片集成电路、半导体芯片或微芯片。
在本发明的一个实施例中,半导体装置组合件包括第一衬底、在第一衬底的表面上的释放层以及具有导电层的柔性层,其中释放层选择性地将柔性层结合到第一衬底。半导体装置组合件包含连接到柔性层的连接器及电连接到柔性构件的第二衬底,连接器经由导电层电连接到第二衬底,其中释放层经配置以从第一衬底选择性地释放柔性构件、连接器及第二衬底的组合件。
在本发明的一个实施例中,一种形成半导体装置组合件的方法包括提供第一衬底并将柔性构件连接到第一衬底的表面。所述方法包括将第二衬底连接到柔性构件,其中柔性构件的导电层电连接到第二衬底的电连接件。所述方法包含在柔性构件的一部分上提供连接器,所述连接器经由柔性构件的导电层电连接到第二衬底的电连接件。
图1是半导体装置组合件100的实施例的示意性横截面视图。半导体装置组合件100包含衬底110,其具有第一或顶表面111及邻近柔性构件120定位的第二或底表面112。柔性构件120包含第一或顶表面121及第二或底表面122。柔性构件120的顶表面121包含多个垫123,并且衬底110的第二表面包含多个柱113,其允许衬底110及柔性构件120通过将每一柱113连接到每一垫123而连接在一起,以在衬底110与柔性构件120之间形成互连件130,如受益于本发明的所属领域的一般技术人员将了解。
柔性构件120的第一部分120A邻近衬底110定位,并且柔性构件120的第二部分120B远离衬底120B定位,如图1中所展示。换句话说,柔性构件120的部分120B可远离衬底110延伸。连接器140连接到远离衬底110定位的柔性构件120的部分120B。连接器140可定位在柔性构件120的端部处,如图1中所展示。然而,取决于应用,连接器140可能潜在地沿着柔性构件120的第二部分120B定位在各种位置,如受益于本发明的所属领域的一般技术人员所了解。衬底110、柔性构件120及/或连接器140的大小、配置及/或形状仅出于说明性目的而展示,并且可根据应用而变化,如受益于本发明的所属领域的一般技术人员所了解。举例来说,柔性构件120的第二部分120B可比柔性构件120的第一部分120A长得多。
连接器140包含顶端141、底端142及连接器140内的电连接件144。电连接件144电连接到电连接件,其也可被称为位于柔性构件120内的迹线124。连接器140可经配置以选择性地连接到印刷电路板300上的连接器(如图2中所展示)。连接器140的电连接件144经由柔性构件120内的电连接件124及衬底110与柔性构件120之间的互连件130电连接到衬底110。材料150可用于囊封衬底110的至少一部分。同样地,材料150可囊封连接到衬底110的柔性构件120的部分以及衬底110,这取决于应用,如受益于本发明的所属领域的一般技术人员所了解。衬底110及/或柔性构件120的一部分的囊封可使得例如散热器的额外结构能够连接到半导体装置组合件100,如受益于本发明的所属领域的一般技术人员所了解。可使用各种材料来囊封衬底110及/或柔性构件120。举例来说,材料150可为(但不限于)各种非导电膜及/或模制化合物。
衬底110可包括半导体装置。举例来说,衬底可为(但不限于)硅晶片的单个裸片、集成电路、单片集成电路、半导体芯片或微芯片。另外,衬底110可包括连接在一起的多个半导体装置,如受益于本发明的所属领域的一般技术人员所了解。
柔性构件120经配置以比典型的半导体装置更柔韧。在典型的室温(例如,华氏50度到华氏90度)下,柔性构件120可弯曲、折曲、扭曲或类似者,而不会破裂或断裂。具体来说,柔性构件120的部分120B经配置以使得其可弯曲或折曲,以使得连接器140能够插入到另一半导体装置组合件或系统板(例如,印刷电路板(PCB))的连接器中或从其移除。柔性构件120的部分120B可使连接器140能够插入对应连接件或从对应件连接移除,而不需要移动连接到衬底110的柔性构件120的部分120A,衬底110可为半导体装置。柔性构件120可由各种材料构成,所述材料使得柔性构件120的部分120B能够是柔性的。举例来说,柔性构件可由(但不限于)聚酰亚胺膜、聚醚醚酮膜、电介质材料、有机电介质材料、其组合或类似者构成。在实施例中,柔性构件120可在整个三百六十度内自由弯曲。换句话说,在实施例中,柔性构件120可卷成卷。
如受益于本发明的所属领域的一般技术人员所了解,取决于应用,柔性构件120可由各种其它材料构成。柔性构件120包含导电层或多个导电层,也称为迹线,其也是柔性的并且实现连接到柔性构件120的第一部分120A的衬底110与连接器140之间的电连接,连接器140连接到柔性构件120的第二部分120B。
连接器140可为可用于选择性地将半导体装置组合件100连接到PCB或类似物的各种类型的连接器中的一者,如受益于本发明的所属领域的一般技术人员所了解。柔性构件120及连接器140可使半导体装置组合件100能够选择性地安装及从PCB或类似物移除,而不会损坏半导体装置组合件,如受益于本发明的所属领域的一般技术人员所了解。
图2是PCB 300的示意性顶视图,其中半导体装置组合件100定位在PCB 300的表面301上。PCB 300的表面301可包含多个连接器容座310,如图2中所示。包括衬底(可为半导体装置110)的半导体装置组合件100经由连接到连接器容座310的连接器140连接到PCB 300。半导体装置组合件100的衬底或半导体装置110如本文所论述那样经由柔性构件120内的连接层或迹线连接到PCB 300。连接器140附接到柔性构件120并且将半导体装置110与PCB300电连接。如本文所论述,柔性构件120连接到半导体装置110的衬底(如图1中所展示),其可为经由环氧树脂或类似物选择性地附接到PCB 300,以将半导体装置110保持在适当位置。用于选择性地附接半导体装置110的环氧树脂可经配置以允许半导体装置110随后通过各种机制从PCB 300移除而不损坏半导体装置110,如受益于本发明的所属领域的一般技术人员所了解。
图3到7是展示形成半导体装置组合件200的实施例的各种步骤的示意性横截面图。图3展示半导体组合件200,其包含具有顶部或第一表面202及底部或第二表面203的第一衬底201。第一衬底201可由各种材料构成。举例来说,第一衬底201可为玻璃、硅或各种其它材料,如受益于本发明的所属领域的一般技术人员所了解。在一些实施例中,第一衬底201可为载体晶片。
释放层205位于第一衬底201的顶表面202上。释放层205可为临时结合材料,其选择性地将柔性构件220结合到第一衬底201,如本文所论述。释放层205可为粘合剂或类似物,其可用于选择性地将柔性构件220附接到第一衬底201,并且随后从第一衬底201选择性地释放柔性构件220,如本文所论述。释放层205可为光学释放层。可使用各种机制来选择性地从释放层205及第一衬底201释放柔性构件220,如本文所论述。
具有第一或顶表面221及第二或底表面222的柔性构件220定位在第一衬底201的顶表面202上的释放层205上。柔性构件220的顶表面221包含多个垫223或类似物,其可用于与第二衬底210(图4中展示)创建电互连件,如本文所论述。在一些实施例中,第二衬底210可由电连接在一起的多个半导体装置构成,如由受益于本发明的所属领域的一般技术人员将了解。柔性构件220包含在柔性构件220内的导电层224,也称为迹线。导电层224电连接到柔性构件200的顶表面221上的多个垫223。柔性层220可定位到释放层224上,并因此选择性地连接到第一衬底201。在另一实施例中,柔性构件220可通过将多个层沉积到释放层205上而形成,如由受益于本发明的所属领域的一般技术人员将了解。柔性构件220的导电层或迹线224可在将各种层沉积到释放层205上以形成柔性构件220的过程中形成。
图4展示衬底210,其可由各种半导体装置构成,例如芯片或裸片,衬底210具有顶部或第一表面211及多个柱213或类似物,从连接到柔性构件220的顶表面221的底部或第二表面212延伸。衬底210的柱213连接到垫223,以在衬底210与柔性构件220之间形成电互连件230。可使用各种结构及/或方法来形成衬底210与柔性构件220之间互连件230,如由受益于本发明的所属领域的一般技术人员将了解。
图5展示囊封衬底210及互连件230的至少一部分的材料250。材料250可由各种材料构成,所述材料可用于囊封半导体装置组合件200的一部分,如由受益于本发明的所属领域的一般技术人员将了解。举例来说,材料250可为(但不限于)模制化合物及/或非导电膜。囊封材料250邻近柔性构件220的第一部分220A定位,而柔性构件220的第二部分220B延伸超过囊封材料250。
图6展示连接器240,其具有连接到柔性构件220的第二部分220B的顶端241及底端242。连接器240包含连接到柔性构件220的导电层或迹线224的内部电连接件244。连接器240经由柔性构件220的导电层224及衬底210与柔性构件220之间的互连件230电连接到衬底210。连接器240使得衬底210能够选择性地连接到外部组合件或从外部组合件断开连接,所述外部组合件可为PCB或类似物,或另一半导体装置组合件,如由受益于本发明的所属领域的一般技术人员将了解。取决于应用,连接器240可通过各种机制附接到柔性构件220,如由受益于本发明的所属领域的一般技术人员将了解。举例来说,连接器240可通过(但不限于)焊接及/或施加环氧树脂来附接。连接器240可经配置以插入对应容座中。同样地,连接器240可为经配置以接纳对应插头或连接器的容座,如所属领域的一般技术人员将了解。
图7展示由第二衬底210、囊封材料250、柔性构件220及连接器240构成的从第一衬底201移除的半导体装置组合件200’。可使用各种机制及/或方法来选择性地将半导体装置组合件200’从第一衬底201释放,如由受益于本发明的所属领域的一般技术人员将了解。举例来说,可使用溶剂、激光及/或热量来使释放层205从第一衬底201释放半导体装置组合件200’。机械剥离可为用于将半导体装置组合件200’从第一衬底201释放的机制的另一实例。
在从第一衬底201移除半导体装置组合件200’之后,柔性构件220的第二部分220B可用于选择性地经由连接器240将半导体装置组合件200’(且更具体来说半导体装置210)连接外部装置或组合件。柔性构件220可使半导体装置组合件200’能够从PCB或类似物移除,而不会损坏半导体装置组合件200’。另外,半导体装置组合件200’的柔性构件220可允许在各种应用中使用半导体装置组合件200’,所述应用可包含柔性衬底及/或弯曲衬底。举例来说,半导体装置组合件200’可潜在地施加于(但不限于)织物,例如施加在衣服上,在腕带上,及/或在玻璃器皿的弯曲表面上。
图8展示包含第一衬底201的半导体装置组合件200A的示意图,第一衬底201是载体晶片。第一衬底201包含经由柔性构件220连接到连接器240的多个半导体装置210。由半导体装置210构成的经由柔性构件220连接到连接器240的多个半导体装置组合件200’可形成在单个衬底201上。然后,可从晶片201释放个别半导体装置组合件200’,如本文所论述。如所属领域的一般技术人员所理解的,可使用可用于保护半导体装置210的囊封材料250(图7中展示)来囊封半导体装置210,如由所属领域的一般技术人员将了解。衬底201、半导体装置210、柔性构件220及连接器240的大小、形状、数目、位置及/或配置仅出于说明的目的而展示并且可变化,如由受益于本发明的所属领域的一般技术人员将了解。
图9展示形成半导体装置组合件的方法400的实施例。方法400包含在步骤410提供第一衬底。第一衬底可为各种衬底。举例来说,第一衬底可为(但不限于)硅晶片或玻璃衬底。方法400包括在步骤420将柔性构件连接到第一衬底的表面。柔性构件包含柔性构件内的导电层或迹线。方法400可包含将柔性构件以多个层沉积到第一衬底的表面上的释放层上的任选步骤425。
在步骤430,方法400包含将第二衬底连接到柔性构件。柔性构件内的导电层电连接到第二衬底的电连接件。第二衬底可为(但不限于)半导体装置,例如芯片或微芯片。第二衬底可包括连接在一起的多个半导体装置。方法400可包括用材料囊封第二衬底的至少一部分的任选步骤435。可使用各种材料来囊封第二衬底并且可保护第二衬底。囊封材料还可囊封连接到第二衬底的柔性构件的一部分。
方法400包含在步骤440在柔性构件的一部分上提供连接器。连接器经由柔性构件内的导电层电连接到第二衬底。连接器连接到远离第二衬底延伸的柔性构件的一部分。连接器可为经配置以插入对应容座中的连接器,或者连接器可为经配置以接纳对应连接器的容座,如受益于本发明的所属领域的一般技术人员所了解。方法400可包含任选步骤450,其从第一衬底释放柔性构件以形成由第二衬底构成的组合件,所述第二衬底通过连接器连接到柔性构件。柔性构件可经由释放层从第一衬底释放,所述释放层可经配置以按各种方式选择性地释放柔性构件。举例来说,半导体装置组合件的加热可使释放层释放柔性构件。替代地,可施加机械力以释放柔性构件,或者可将溶剂施加到释放层。可使用各种其它方法来选择性地释放柔性构件,如受益于本发明的所属领域的一般技术人员将了解。
尽管已经根据某些实施例描述本发明,但对于所属领域的一般技术人员显而易见的其它实施例(包含不提供本文所阐述的所有特征及优点的实施例)也在本发明的范围内。本发明可涵盖未在本文明确展示或描述的其它实施例。因此,仅通过参考所附权利要求书及其等效物来界定本发明的范围。
Claims (22)
1.一种半导体装置组合件,其包括:
衬底,其具有第一表面及第二表面;
柔性构件,其具有导电层,所述柔性构件连接到所述衬底的所述第二表面,所述柔性构件具有邻近所述衬底的第一部分及远离所述衬底定位的第二部分;及
连接器,其位于所述柔性构件的所述第二部分上,其中所述连接器经由所述柔性构件的所述导电层电连接到所述衬底的电连接件。
2.根据权利要求1所述的半导体装置组合件,其中所述衬底进一步包括半导体装置。
3.根据权利要求2所述的半导体装置组合件,其进一步包括囊封所述半导体装置的至少一部分的模制化合物。
4.根据权利要求1所述的半导体装置组合件,其中所述柔性构件进一步包括聚酰亚胺膜、聚醚醚酮膜、电介质材料、有机电介质材料或其组合。
5.根据权利要求1所述的半导体装置组合件,其中所述柔性构件及所述衬底经由多个垫与多个柱之间的多个个别焊料连接件而连接在一起。
6.根据权利要求1所述的半导体装置组合件,其中所述连接器经配置以将所述衬底电连接到印刷电路板。
7.一种半导体装置组合件,其包括:
第一衬底;
所述第一衬底的表面上的释放层;
柔性构件,其具有导电层,其中所述释放层选择性地将所述柔性构件结合到所述第一衬底的所述表面;
连接器,其连接到所述柔性构件的一部分,所述连接器电连接到所述柔性构件的所述导电层;及
第二衬底,其电连接到所述柔性构件,所述连接器经由所述柔性构件的所述导电层电连接到所述第二衬底,其中所述释放层经配置以选择性地从所述第一衬底的所述第一表面释放所述柔性构件、连接器及第二衬底。
8.根据权利要求7所述的半导体装置组合件,其中所述连接器经配置以将所述第二衬底电连接到印刷电路板。
9.根据权利要求7所述的半导体装置组合件,其中所述第一衬底包括载体晶片。
10.根据权利要求7所述的半导体装置组合件,其中所述第一衬底包括玻璃、硅或其组合。
11.根据权利要求7所述的半导体装置组合件,其进一步包括囊封所述第二衬底的至少一部分的材料。
12.根据权利要求7所述的半导体装置组合件,其中所述第二衬底进一步包括半导体装置。
13.根据权利要求7所述的半导体装置组合件,其中所述第二衬底进一步包括多个第二衬底,并且所述柔性构件进一步包括各自具有导电层的多个柔性构件,所述释放层选择性地将每一个别柔性构件结合到所述第一衬底,其中每一第二衬底连接到个别柔性构件。
14.根据权利要求13所述的半导体装置组合件,其中所述连接器进一步包括多个连接器,其中每一连接器连接到个别柔性构件并且经由所述柔性构件的所述导电层电连接到个别第二衬底。
15.一种形成半导体装置组合件的方法,所述方法包括:
提供第一衬底;
将柔性构件连接到所述第一衬底的表面,所述柔性构件包含导电层;
将第二衬底连接到所述柔性构件,所述柔性构件的所述导电层电连接到所述第二衬底的电连接件,其中所述柔性构件定位在所述第一衬底的至少一部分与所述第二衬底的一部分之间;以及
在所述柔性构件的一部分上提供连接器,所述连接器经由所述柔性构件的所述导电层电连接到所述第二衬底的所述电连接件。
16.根据权利要求15所述的方法,其进一步包括用材料囊封所述第二衬底的至少一部分。
17.根据权利要求15所述的方法,其中在所述第一衬底的所述表面上提供所述柔性构件进一步包括在所述第一衬底的所述表面上沉积多个层以形成包含所述导电层的所述柔性构件。
18.根据权利要求15所述的方法,其中提供所述连接器进一步包括将插口焊接或用环氧树脂胶合到所述柔性构件的一部分。
19.根据权利要求15所述的方法,其进一步包括从所述第一衬底的所述表面释放所述柔性构件以形成组合件,所述组合件包括用连接器连接到所述柔性构件的所述第二衬底。
20.根据权利要求15所述的方法,其中所述将所述柔性构件连接到所述衬底的所述表面进一步包括用释放层将所述柔性构件结合到所述第一衬底的所述表面。
21.根据权利要求20所述的方法,其进一步包括从所述释放层释放所述柔性构件。
22.根据权利要求21所述的方法,其中从所述释放层释放所述柔性构件进一步包括机械地释放所述柔性构件,使用溶剂来释放所述柔性构件,使用激光来释放所述柔性构件,使用热量来释放所述柔性构件。
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US10943860B2 (en) | 2021-03-09 |
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