CN109585382A - 具有可挠性基板的晶片封装构造 - Google Patents

具有可挠性基板的晶片封装构造 Download PDF

Info

Publication number
CN109585382A
CN109585382A CN201710964288.8A CN201710964288A CN109585382A CN 109585382 A CN109585382 A CN 109585382A CN 201710964288 A CN201710964288 A CN 201710964288A CN 109585382 A CN109585382 A CN 109585382A
Authority
CN
China
Prior art keywords
base plate
flexible base
chip
wafer packaging
packaging construction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710964288.8A
Other languages
English (en)
Inventor
苏俊扬
王昭昕
杨念慈
罗信伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipbond Technology Corp
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Publication of CN109585382A publication Critical patent/CN109585382A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种具有可挠性基板的晶片封装构造，其在一可挠性基板的第一表面设置有晶片及防压件，且在该可挠性基板的第二表面设置有补强片，该防压件至少具有一对防压凸肋，各该防压凸肋分别位于该晶片外的二相对应外侧，借由位于该晶片外侧的该防压件避免该封装构造以外的元件(如曲面面板)压迫该晶片，而造成该晶片损坏。

Description

具有可挠性基板的晶片封装构造
技术领域
本发明是关于一种具有可挠性基板的晶片封装构造，其用以防止设置于可挠性基板的晶片被该封装构造以外的元件(如曲面面板)压迫而造成损坏。
背景技术
现行电子产品驱向于轻、薄及可弯曲，如具有曲面荧幕的电视或手机等电子产品，然由于电子产品的荧幕为曲面面板，因此会造成曲面面板压迫电子元件，而造成电子元件损坏。
请参阅图5，一种电子产品的液晶显示荧幕10具有曲面面板11及设置于电路基板12上的晶片13，由于该曲面面板11弯曲而压迫该晶片13，使得该晶片损坏，无法与该电路基板12电性连接，相对地，也提高了该电子产品的不良率或损坏率。
发明内容
本发明具有可挠性基板的晶片封装构造的发明目的是在一可挠性基板的不同表面分别设有防压件及补强片，借由该防压件防止设置于该可挠性基板的晶片受压迫而损坏。
本发明的一种具有可挠性基板的晶片封装构造包含可挠性基板、晶片、补强片以及防压件，该可挠性基板具有第一表面及第二表面，该晶片设置于该可挠性基板的该第一表面，该晶片具有主动面及背面，该主动面朝向该第一表面并电性连接该可挠性基板，该晶片的该背面至该可挠性基板的该第一表面之间具有第一高度，该补强片结合于可挠性基板的该第二表面，该补强片在该可挠性基板的该第一表面形成有投影区，该晶片位于该投影区中，该防压件设置于该可挠性基板的该第一表面，且该防压件至少具有一对防压凸肋，各该防压凸肋分别位于该晶片外的二相对应外侧，各该防压凸肋具有显露面及相对于该显露面的接合面，该防压凸肋以该接合面朝向该可挠性基板的该第一表面，该显露面至该可挠性基板的该第一表面之间具有第二高度，该第二高度不小于该第一高度。
上述的具有可挠性基板的晶片封装构造，其中该防压件为环状，该防压件环绕该晶片。
上述的具有可挠性基板的晶片封装构造，其中该防压件位于该投影区。
上述的具有可挠性基板的晶片封装构造，其中各该防压凸肋对称地设置于该晶片外。
上述的具有可挠性基板的晶片封装构造，其中该补强片的刚性大于该可挠性基板。
上述的具有可挠性基板的晶片封装构造，其中该防压件的材质选自于聚酰亚胺薄膜(PI)、聚对苯二甲酸乙二酯(PET)、不锈钢(SUS)。
上述的具有可挠性基板的晶片封装构造，其中该补强片以黏胶结合于该可挠性基板的该第二表面。
上述的具有可挠性基板的晶片封装构造，该接合面以一黏胶结合于该可挠性基板的该第一表面。
当该具有可挠性基板的晶片封装构造被装设于具有曲面面板的电子产品(如液晶显示荧幕(Liquid Crystal Display,LCD)中时，由于设置于该第一表面的该防压件高于设置于该第一表面的该晶片，因此可借由该防压件接触该曲面面板，以避免该晶片被该曲面面板压迫而损坏。
此外，当该防压凸肋位于该投影区时，可增加该具有可挠性基板的晶片封装构造的抗压及抗弯曲强度，且可防止该防压件受该曲面面板压迫变形而弯曲，以避免该晶片被该曲面面板压迫而损坏。
附图说明
图1：本发明具有可挠性基板的晶片封装构造的立体图。
图2：本发明具有可挠性基板的晶片封装构造的立体分解图。
图3：本发明具有可挠性基板的晶片封装构造与曲面面板的剖视图。
图4：本发明具有可挠性基板的晶片封装构造与曲面面板的剖视图。
图5：习知技术的晶片封装构造与曲面面板的剖视图。
【主要元件符号说明】
10：液晶显示荧幕 11：曲面面板
12：电路基板 13：晶片
100：晶片封装构造 110：可挠性基板
110a：导接垫 111：第一表面
112：第二表面 120：晶片
120a：凸块 121：主动面
122：背面 130：补强片
130A：投影区 140：防压件
141：防压凸肋 141a：显露面
141b：接合面 150：黏胶
160：黏胶 170：填充胶
H1：第一高度 H2：第二高度
200：曲面面板
具体实施方式
请参阅图1及图2，本发明的一种具有可挠性基板的晶片封装构造100包含可挠性基板110(例如运用于卷带承载封装(Tape Carrier Package,TCP)的基板或运用于薄膜覆晶封装(Chip on Film,COF)用基板)、晶片120及分别设置于该可挠性基板110不同表面的补强片130及防压件140。
请参阅图1及图2，该可挠性基板110具有第一表面111及第二表面112，该晶片120设置于该可挠性基板110的该第一表面111，该晶片120具有主动面121及背面122，该主动面121朝向该第一表面111并电性连接该可挠性基板110，请参阅图3及图4，在本实施例中，该晶片120以多个凸块120a电性连接该可挠性基板110的多个导接垫110a，较佳地，在该晶片120与该可挠性基板110之间填充一填充胶170，以密封该些凸块120a及该些导接垫110a，请参阅图3及图4，该晶片120的该背面122至该可挠性基板110的该第一表面111之间具有第一高度H1。
请参阅图1及图2，该补强片130结合于可挠性基板110的该第二表面112，请参阅图3及图4，在本实施例中，该补强片130以黏胶150结合于可挠性基板110的该第二表面112，该补强片130在该可挠性基板110的该第一表面111形成有投影区130A，该晶片120位于该投影区130A中，较佳地，该补强片130的刚性大于该可挠性基板110，其可避免在该投影区130A内的该可挠性基板110弯曲变形，较佳地，该补强片130可选自金属板以对该晶片封装构造100进行散热。
请参阅图1及图2，该防压件140设置于该可挠性基板110的该第一表面111，且该防压件140至少具有一对防压凸肋141，各该防压凸肋141分别位于该晶片120外的二相对应外侧，请参阅图3及图4，在本实施例中，该防压件140以黏胶160结合于该可挠性基板110的该第一表面111，该防压件的材质选自于聚酰亚胺薄膜(PI)、聚对苯二甲酸乙二酯(PET)、不锈钢(SUS)。
请参阅图1及图2，在本实施例中，该些防压凸肋141相互连接，使该防压件140形成为环状，且该防压件140环绕该晶片120，较佳地，各该防压凸肋141对称地设置于该晶片120外。
请参阅图1、2、3及图4，各该防压凸肋141具有显露面141a及相对于该显露面141a的接合面141b，各该防压凸肋141以该接合面141b朝向该可挠性基板110的该第一表面111，在本实施例中，该接合面141b以该黏胶160结合于该可挠性基板110的该第一表面111，该显露面141a至该可挠性基板110的该第一表面111之间具有第二高度H2，该第二高度H2不小于该第一高度H1，较佳地，该第二高度H2高于该第一高度H1，且该防压件140位于该投影区130A。
请参阅图1、3及图4，当该晶片封装构造100被装设于一具有曲面面板200的电子产品(如液晶显示荧幕(Liquid Crystal Display,LCD)中，若发生该曲面面板200弯曲度过大而压迫该晶片封装构造100时，由于该防压凸肋141的该显露面141a至该可挠性基板110的该第一表面111的该第二高度H2不小于该晶片120的该背面122至该可挠性基板110的该第一表面111的该第一高度H1，因此该曲面面板200会先压迫该防压凸肋141，而不会压迫位于该对防压凸肋141之间的该晶片120，其可避免该晶片120受该曲面面板200压迫而损坏。
请参阅图1、3及图4，由于该防压件140位于该投影区130A，因此可增加该具有可挠性基板的晶片封装构造100的抗压及抗弯曲强度，且可防止该防压件140受该曲面面板200压迫变形而弯曲，进而压迫该晶片120。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明,任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (8)

1.一种具有可挠性基板的晶片封装构造，其特征在于，包含：
可挠性基板，具有第一表面及第二表面；
晶片，设置于该可挠性基板的该第一表面，该晶片具有主动面及背面，该主动面朝向该第一表面并电性连接该可挠性基板，该晶片的该背面至该可挠性基板的该第一表面之间具有第一高度；
补强片，结合于可挠性基板的该第二表面，该补强片在该可挠性基板的该第一表面形成有投影区，该晶片位于该投影区中；以及
防压件，设置于该可挠性基板的该第一表面，且该防压件至少具有一对防压凸肋，各该防压凸肋分别位于该晶片外的二相对应外侧，各该防压凸肋具有显露面及相对于该显露面的接合面，该防压凸肋以该接合面朝向该可挠性基板的该第一表面，该显露面至该可挠性基板的该第一表面之间具有第二高度，该第二高度不小于该第一高度。
2.如权利要求1所述的具有可挠性基板的晶片封装构造，其特征在于，其中该防压件为环状，该防压件环绕该晶片。
3.如权利要求1或2所述的具有可挠性基板的晶片封装构造，其特征在于，其中该防压件位于该投影区。
4.如权利要求1所述的具有可挠性基板的晶片封装构造，其特征在于，其中各该防压凸肋对称地设置于该晶片外。
5.如权利要求1所述的具有可挠性基板的晶片封装构造，其特征在于，其中该补强片的刚性大于该可挠性基板。
6.如权利要求1所述的具有可挠性基板的晶片封装构造，其特征在于，其中该防压件的材质选自于聚酰亚胺薄膜(P I)、聚对苯二甲酸乙二酯(PET)、不锈钢(SUS)。
7.如权利要求1所述的具有可挠性基板的晶片封装构造，其特征在于，其中该补强片以黏胶结合于该可挠性基板的该第二表面。
8.如权利要求1所述的具有可挠性基板的晶片封装构造，其特征在于，该接合面以一黏胶结合于该可挠性基板的该第一表面。
CN201710964288.8A 2017-09-28 2017-10-17 具有可挠性基板的晶片封装构造 Pending CN109585382A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW106133279A TWI681516B (zh) 2017-09-28 2017-09-28 具有可撓性基板的晶片封裝構造
TW106133279 2017-09-28

Publications (1)

Publication Number Publication Date
CN109585382A true CN109585382A (zh) 2019-04-05

Family

ID=64739675

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710964288.8A Pending CN109585382A (zh) 2017-09-28 2017-10-17 具有可挠性基板的晶片封装构造

Country Status (5)

Country Link
US (1) US10168582B1 (zh)
JP (1) JP2019068024A (zh)
KR (1) KR101992732B1 (zh)
CN (1) CN109585382A (zh)
TW (1) TWI681516B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1146134A (zh) * 1995-09-05 1997-03-26 国际商业机器公司 用于在挠性电缆上安装电气元件的装配件
CN1219095A (zh) * 1997-11-27 1999-06-09 日本电气株式会社 其上设置有电子部件的柔性印刷电路板单元
US6388888B1 (en) * 1999-08-06 2002-05-14 Sharp Kabushiki Kaisha Semiconductor device and process for manufacturing the same, liquid crystal module and process for mounting the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2628741B2 (ja) * 1989-02-17 1997-07-09 住友電気工業株式会社 フレキシブルプリント配線板
US6518089B2 (en) * 2001-02-02 2003-02-11 Texas Instruments Incorporated Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
US7368803B2 (en) * 2004-09-27 2008-05-06 Idc, Llc System and method for protecting microelectromechanical systems array using back-plate with non-flat portion
JP2011176112A (ja) * 2010-02-24 2011-09-08 Renesas Electronics Corp 半導体集積回路及びその製造方法
KR20120021672A (ko) * 2010-08-12 2012-03-09 엘지이노텍 주식회사 인쇄회로 기판
TWI455273B (zh) * 2011-08-04 2014-10-01 Chipmos Technologies Inc 晶片封裝結構
US9198282B2 (en) * 2012-06-25 2015-11-24 Honeywell International Inc. Printed circuit board
US9111912B2 (en) * 2013-05-30 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
CN206272939U (zh) * 2016-11-11 2017-06-20 昆山乐华电子有限公司 柔性电路板用钢片补强片

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1146134A (zh) * 1995-09-05 1997-03-26 国际商业机器公司 用于在挠性电缆上安装电气元件的装配件
CN1219095A (zh) * 1997-11-27 1999-06-09 日本电气株式会社 其上设置有电子部件的柔性印刷电路板单元
US6388888B1 (en) * 1999-08-06 2002-05-14 Sharp Kabushiki Kaisha Semiconductor device and process for manufacturing the same, liquid crystal module and process for mounting the same

Also Published As

Publication number Publication date
KR101992732B1 (ko) 2019-06-25
JP2019068024A (ja) 2019-04-25
TW201916274A (zh) 2019-04-16
US10168582B1 (en) 2019-01-01
TWI681516B (zh) 2020-01-01

Similar Documents

Publication Publication Date Title
CN214476074U (zh) 柔性显示模组
US20190081255A1 (en) Display device
CN111128020A (zh) 显示面板及其制造方法、显示装置
US7561225B2 (en) Liquid crystal display device
CN110164825A (zh) 薄膜覆晶封装结构及其可挠性基板
CN112634764A (zh) 显示装置
CN113363297B (zh) 显示面板及其组装方法以及拼接显示装置
CN113555412A (zh) 一种显示模组及显示装置
CN112053633B (zh) 显示装置
US20210407338A1 (en) Display device and manufacturing method thereof
CN111292614B (zh) 显示模组、显示装置
JP2010224102A (ja) 液晶表示装置及びその製造方法
CN112164309A (zh) 显示装置
CN113724603A (zh) 显示模组
US20230137505A1 (en) Protective bracket and using method thereof
JP2006190989A (ja) キャリアフィルム、これを有する表示装置、及びその製造方法
US11745486B2 (en) Buffer component and pressing device
CN216980028U (zh) 显示装置及显示面板
CN107464792B (zh) 薄膜覆晶封装结构
CN113257114B (zh) 显示装置及电子设备
CN109585382A (zh) 具有可挠性基板的晶片封装构造
CN110295016A (zh) 保护膜及面板组件
CN112270890B (zh) 一种柔性显示面板及柔性显示装置
JP2001305568A (ja) 液晶モジュール
CN109814313B (zh) 一种显示模组和移动终端

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20190405

WD01 Invention patent application deemed withdrawn after publication