CN109509742A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN109509742A
CN109509742A CN201810082594.3A CN201810082594A CN109509742A CN 109509742 A CN109509742 A CN 109509742A CN 201810082594 A CN201810082594 A CN 201810082594A CN 109509742 A CN109509742 A CN 109509742A
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China
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mentioned
region
metal layer
film thickness
semiconductor device
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CN201810082594.3A
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刀祢馆达郎
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Publication of CN109509742A publication Critical patent/CN109509742A/zh
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Abstract

实施方式提供一种能够实现散热性的提高的半导体装置。实施方式的半导体装置具备：半导体芯片；金属板；绝缘基板，设在半导体芯片与金属板之间，具有第1金属层、第2金属层、和第1金属层与第2金属层之间的绝缘层，第2金属层具备具有第1膜厚的第1区域、具有第2膜厚的第2区域、具有比第1膜厚及第2膜厚厚的第3膜厚的第3区域，第3区域位于第1区域与第2区域之间；以及焊料层，设在第2金属层与金属板之间。

Description

半导体装置
本申请基于日本专利申请第2017－176262号(申请日：2017年9月14日)主张优先权，本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置。
背景技术
在功率半导体模块中，例如在金属基底板之上以在中间夹着绝缘基板的方式安装有功率半导体芯片。功率半导体芯片例如是IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)、MOSFET(Metal Oxide Field Effect Transistor，金属氧化物场效应晶体管)或二极管。
功率半导体芯片由于在高电压下流过高电流，所以发热量较大。如果功率半导体模块的散热性较低，则起因于功率半导体芯片的发热，发生接合线的断路不良等的可靠性不良。因此，功率半导体模块要求使散热性提高。
发明内容
本发明提供一种能够实现散热性的提高的半导体装置。
本发明的一技术方案的半导体装置具备：半导体芯片；金属板；绝缘基板，设在上述半导体芯片与上述金属板之间，具有第1金属层、第2金属层、和上述第1金属层与上述第2金属层之间的绝缘层，上述第2金属层具备具有第1膜厚的第1区域、具有第2膜厚的第2区域、具有比上述第1膜厚及上述第2膜厚厚的第3膜厚的第3区域，上述第3区域位于上述第1区域与上述第2区域之间；以及焊料层，设在上述第2金属层与上述金属板之间。
附图说明
图1是实施方式的半导体装置的示意剖视图。
图2是实施方式的一部分的放大示意剖视图。
图3是比较方式的半导体装置的示意剖视图。
图4是比较方式的半导体装置的问题点的说明图。
图5是实施方式的半导体装置的作用及效果的说明图。
具体实施方式
本说明书中，对于相同或类似的部件，有赋予相同的标号而省略重复的说明的情况。
本说明书中，为了表示零件等的位置关系，有将附图的上方向记述为“上”、将附图的下方向记述为“下”的情况。在本说明书中，“上”、“下”的概念并不一定是表示与重力的朝向的关系的用语。
实施方式的半导体装置具备：半导体芯片；金属板；绝缘基板，设在半导体芯片与金属板之间，具有第1金属层、第2金属层、和第1金属层与第2金属层之间的绝缘层，第2金属层具备具有第1膜厚的第1区域、具有第2膜厚的第2区域、具有比第1膜厚及第2膜厚厚的第3膜厚的第3区域，第3区域位于第1区域与第2区域之间；以及焊料层，设在第2金属层与金属板之间。
图1是实施方式的半导体装置的示意剖视图。图2是实施方式的一部分的放大示意剖视图。实施方式的半导体装置是功率半导体模块100。
实施方式的功率半导体模块100具备MOSFET10(半导体芯片)、MOSFET12、金属基底板14(金属板)、绝缘电路基板16(绝缘基板)、第1焊料层20(焊料层)、第2焊料层22(粘接层)、接合线24、树脂壳体26(框体)、盖28、第1电力端子30、第2电力端子32、硅胶34(密封剂)。绝缘电路基板16具有第1金属层17、第2金属层18、陶瓷层19(绝缘层)。第2金属层18具有第1凹区域18a(第1区域)、第2凹区域18b(第2区域)、凸区域18c(第3区域)。
MOSFET10及MOSFET12被设置在绝缘电路基板16之上。MOSFET10及MOSFET12是高耐压的功率MOSFET。MOSFET10及MOSFET12被用第2焊料层22固定在第1金属层17上。MOSFET10及MOSFET12例如是使用硅或碳化硅的纵型MOSFET。
MOSFET10及MOSFET12也可以代替焊料而通过例如使用了银膏的烧结接合来固定在第1金属层17上。
金属基底板14例如含有铜。金属基底板14例如是纯铜或铜合金。金属基底板14也可以是铝。
例如，在将功率半导体模块100向制品安装时，在金属基底板14的背面上连接着未图示的散热板。例如，通过将功率半导体模块100的四方和散热板进行螺钉固定，将金属基底板14与散热板固定。在金属基底板14与散热板之间例如夹着散热膏。
金属基底板14例如以对置于绝缘电路基板16的面的相反面为凸形状的方式弯曲。换言之，金属基底板14的背面具有中央部相对于端部突出那样的翘曲形状。
绝缘电路基板16被设置在MOSFET10与金属基底板14之间以及MOSFET12与金属基底板14之间。绝缘电路基板16具有确保MOSFET10与金属基底板14之间以及MOSFET12与金属基底板14之间的电绝缘的功能。在金属基底板14与绝缘电路基板16之间设置有第1焊料层20。
绝缘电路基板16具有第1金属层17、第2金属层18、陶瓷层19(绝缘层)。第1金属层17及第2金属层18例如含有铜。第1金属层17及第2金属层18例如是纯铜。陶瓷层19例如是氧化铝、氮化硅或氮化铝。
第2金属层18具有第1凹区域18a、第2凹区域18b、凸区域18c(第3区域)。凸区域18c位于第1凹区域18a与第2凹区域18b之间。
第1凹区域18a具有第1膜厚(图2中的t1)。第2凹区域18b具有第2膜厚(图2中的t2)。凸区域18c具有第3膜厚(图2中的t3)。第3膜厚t3比第1膜厚t1及第2膜厚t2厚。第1膜厚t1及第2膜厚t2是第3膜厚t3的0.4倍以上0.9倍以下。
第1膜厚t1、第2膜厚t2及第3膜厚t3的膜厚的关系例如可以通过在显微镜照片的图像上比较各自的膜厚来判定。
第1膜厚t1及第2膜厚t2例如是0.16mm以上且0.76mm以下。此外，第3膜厚t3例如是0.4mm以上且0.8mm以下。
凸区域18c位于MOSFET10与金属基底板14之间以及MOSFET12与金属基底板14之间。凸区域18c位于MOSFET10的正下方。此外，凸区域18c位于MOSFET12的正下方。
将MOSFET10的第1端部(图2中的E1)与第1凹区域18a和凸区域18c的边界部虚拟地连结的第1线段(图2中的L1)、与第2金属层18和陶瓷层19的界面(图2中的I)之间所成的角度(图2中的θ1)例如是45度以下。此外，将MOSFET10的第2端部(图2中的E2)与第2凹区域18b和凸区域18c的边界部虚拟地连结的第2线段(图2中的L2)、与第2金属层18和陶瓷层19的界面(图2中的I)之间所成的角度(图2中的θ2)例如是45度以下。
第1凹区域18a、第2凹区域18b、凸区域18c例如可以通过对平板形状的金属层进行蚀刻加工而形成。
第1焊料层20被设置在第2金属层18与金属基底板14之间。第1焊料层20将绝缘电路基板16固定到金属基底板14上。第1焊料层20的主成分例如是锡(Sn)－铅(Pb)合金、锡(Sn)－银(Ag)合金、锡(Sn)－铋(Bi)合金、锡(Sn)－铜(Cu)合金或锡(Sn)－铟(In)合金。此外，例如是包含锑(Sb)的锡(Sn)－锑(Sb)合金。
树脂壳体26将绝缘电路基板16的周围包围而设置。在树脂壳体26之上设有树脂的盖28。盖28将绝缘电路基板16夹在其与金属基底板14之间。
此外，在功率半导体模块100的内部中，作为密封材料而填充有硅胶34。树脂壳体26、金属基底板14、盖28及硅胶34具有对半导体模块100内的部件进行保护或绝缘的功能。
在树脂壳体26的上部，设有第1电力端子30及第2电力端子32。在树脂壳体26的上部，例如设有未图示的AC输出端子及栅极端子。通过第1电力端子30及第2电力端子32，进行功率半导体模块100与外部的电连接。
第1电力端子30使用接合线24电连接在第1金属层17上。MOSFET10使用接合线24电连接在第1金属层17上。MOSFET12使用接合线24电连接在第1金属层17上。第1金属层17使用接合线24电连接在第2电力端子32上。接合线24例如是铝线。
接着，对实施方式的半导体装置的作用及效果进行说明。
图3是比较方式的半导体装置的示意剖视图。比较方式的半导体装置是功率半导体模块900。
比较方式的功率半导体模块900在绝缘电路基板16的第2金属层18上没有设置凸区域18c这一点上与实施方式的功率半导体模块100不同。即，功率半导体模块900的第2金属层18是平板形状。
图4是比较方式的半导体装置的问题点的说明图。图4图示了功率半导体模块900的一部分及散热板。
在将功率半导体模块900向制品安装时，在金属基底板14的背面上连接散热板40。例如，通过将功率半导体模块900的四方与散热板40螺钉固定，推压金属基底板14，从而将金属基底板14与散热板40密接而固定。在金属基底板14与散热板40之间，例如夹着未图示的散热膏。
金属基底板14的背面具有中央部相对于端部突出那样的翘曲形状。金属基底板14的表面具有中央部相对于端部凹陷那样的翘曲形状。金属基底板14的翘曲量(图4中的Δ)例如是0mm以上且1mm以下。此外，例如是比0mm大且1mm以下。此外，例如是比0.1mm大且1mm以下。另外，在图4中，为了说明，将翘曲量强调地进行了图示。
假如在金属基底板14的背面不具有翘曲形状的情况下，在螺钉固定时，有可能在金属基底板14的背面的中央部与散热板40的表面之间出现间隙。并且，有可能热传导率较低的散热膏积存在该间隙中、或出现热传导率较低的空隙，热阻上升而散热性下降。
在金属基底板14具有翘曲形状的情况下，绝缘电路基板16的中央部与金属基底板14之间的第1焊料层20的厚度相比绝缘电路基板16的端部与金属基底板14之间的厚度变厚。焊料的热传导率例如与第2金属层18或金属基底板14的热传导率相比，显著较低。此外，如果焊料变厚，则热传导率比焊料更低的孔隙的发生概率变高。
因而，如果第1焊料层20的厚度变厚则热阻上升、散热性下降，所以不优选。特别是，发热量较大的MOSFET10的正下方及MOSFET12的正下方的第1焊料层20的厚度变厚，是不优选的。
图5是实施方式的半导体装置的作用及效果的说明图。图5图示了功率半导体模块100的一部分及散热板。
在实施方式中，在功率半导体模块100的第2金属层18上设有凸区域18c。凸区域18c被设置在发热量较大的MOSFET10的正下方及MOSFET12的正下方。通过设置凸区域18c，与比较方式相比，MOSFET10的下方的第1焊料层20的厚度及MOSFET12的下方的第1焊料层20的厚度变薄。因而，与比较方式相比，热阻下降，散热性提高。
第1凹区域18a的第1膜厚t1及第2凹区域18b的第2膜厚t2优选的是凸区域18c的第3膜厚t3的0.4倍以上且0.9倍以下。如果低于上述范围，则加工有可能变得困难。此外，如果低于上述范围，则在第1凹区域18a与凸区域18c的边界部、第2凹区域18b与凸区域18c的边界部，第1焊料层20的焊料量的变化变大，有可能成为裂纹发生的主要原因。此外，如果低于上述范围，则与第1焊料层20之间的合金形成变得不充分，绝缘电路基板16与金属基底板14的粘接性有可能下降。此外，如果高于上述范围，则第1焊料层20的厚度变得过厚，散热性的提高有可能变得不充分。
将MOSFET10的第1端部(图2中的E1)与第1凹区域18a和凸区域18c的边界部虚拟地连结的第1线段(图2中的L1)、与第2金属层18和陶瓷层19的界面(图2中的I)之间的角度(图2中的θ1)优选的是例如45度以下。此外，将MOSFET10的第2端部(图2中的E2)与第2凹区域18b和凸区域18c的边界部虚拟地连结的第2线段(图2中的L2)、与第2金属层18和陶瓷层19的界面(图2中的I)之间的角度(图2中的θ2)优选的是例如45度以下。
通过上述结构，在MOSFET10的下方，第1焊料层20的厚度较薄的区域扩展，能够使散热性提高。
在第1焊料层20的主成分是含有锑(Sb)的锡(Sn)－锑(Sb)合金的情况下，实施方式特别有效地发挥作用。锡(Sn)－锑(Sb)合金具备高的耐热性，另一方面热传导率比较低。通过对实施方式的功率半导体模块100的第1焊料层20应用锡(Sn)－锑(Sb)合金，能够兼顾高耐热性和高散热性。
以上，根据实施方式的半导体模块100，能够使半导体芯片正下方的绝缘电路基板16与金属基底板14之间的第1焊料层20的厚度变薄。因而，能够实现半导体模块100的散热性的提高。
在实施方式中，作为半导体芯片而以MOSFET为例进行了说明，但半导体芯片既可以是IGBT，也可以是二极管。此外，例如也可以是MOSFET与二极管、或者IGBT与二极管的组合。
此外，被安装到1片绝缘电路基板16之上的半导体芯片的数量并不限定于2个，也可以是1个，也可以是3个以上。此外，也可以在半导体模块100中包含2片以上的绝缘电路基板16。
在实施方式中，以使用硅胶34作为密封材料的情况为例进行了说明，但也可以代替硅胶34而使用例如环氧树脂等其他的树脂材料。
以上，例示了本发明的一些实施方式，但这些实施方式是作为例子提示的，不是要限定发明的范围。这些新的实施方式能够以其他的各种各样的形态实施，在不脱离发明的主旨的范围内能够进行各种各样的省略、替换、变更等。例如，也可以将一实施方式的构成要素替换或变更为其他实施方式的构成要素。这些实施方式及其变形例包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明和其等价的范围中。

Claims (10)

1.一种半导体装置，其中，具备：
半导体芯片；
金属板；
绝缘基板，设在上述半导体芯片与上述金属板之间，具有第1金属层、第2金属层、和上述第1金属层与上述第2金属层之间的绝缘层，上述第2金属层具备具有第1膜厚的第1区域、具有第2膜厚的第2区域、具有比上述第1膜厚及上述第2膜厚厚的第3膜厚的第3区域，上述第3区域位于上述第1区域与上述第2区域之间；以及
焊料层，设在上述第2金属层与上述金属板之间。
2.如权利要求1所述的半导体装置，其中，
上述第1膜厚及上述第2膜厚是上述第3膜厚的0.4倍以上且0.9倍以下。
3.如权利要求1或2所述的半导体装置，其中，
上述第2金属层和上述绝缘层的界面与第1线段之间的角度是45度以下，所述第1线段是将上述第1区域和上述第3区域的边界部与上述半导体芯片的第1端部虚拟地连结而得到的；
上述第2金属层和上述绝缘层的界面与第2线段之间的角度是45度以下，所述第2线段是将上述第1区域和上述第3区域的边界部与上述半导体芯片的第2端部虚拟地连结而得到的。
4.如权利要求1或2所述的半导体装置，其中，
上述金属板以与上述绝缘基板对置的面的相反面为凸形状的方式弯曲。
5.如权利要求1或2所述的半导体装置，其中，
还具备设在上述半导体芯片与上述第1金属层之间的粘接层。
6.如权利要求1或2所述的半导体装置，其中，
上述绝缘层是氧化铝、氮化硅或氮化铝。
7.如权利要求1或2所述的半导体装置，其中，
上述金属板含有铜(Cu)。
8.如权利要求1或2所述的半导体装置，其中，
上述第1金属层及上述第2金属层含有铜(Cu)。
9.如权利要求1或2所述的半导体装置，其中，
上述焊料层含有锑(Sb)。
10.如权利要求1或2所述的半导体装置，其中，
还具备将上述绝缘基板的周围包围的框体、盖、和设在上述绝缘基板与上述框体之间以及上述绝缘基板与上述盖之间的密封材料，上述盖与上述金属板之间夹着上述绝缘基板。
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