CN109509721A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN109509721A
CN109509721A CN201710826586.0A CN201710826586A CN109509721A CN 109509721 A CN109509721 A CN 109509721A CN 201710826586 A CN201710826586 A CN 201710826586A CN 109509721 A CN109509721 A CN 109509721A
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layer
hole
interlayer dielectric
metal gates
dielectric layer
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CN109509721B (zh
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江俊霆
杨杰甯
李季儒
林智伟
苏柏羽
吴彦良
张翊凡
杨瑞铭
张文聪
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法，该半导体元件包含一基底、一金属栅极，设于基底上、一第一层间介电层，设于金属栅极周围，其中金属栅极的上表面低于第一层间介电层的上表面，在金属栅极上构成一凹陷区域。一掩模层，设于凹陷区域内。一孔隙，位于凹陷区域内的掩模层中。一第二层间介电层，设于掩模层及第一层间介电层上。一接触洞，穿过第二层间介电层及掩模层，其中接触洞显露出金属栅极的上表面，并且与孔隙连通。一导电层，填入接触洞内，并延伸进入孔隙中。

Description

半导体元件及其制作方法
技术领域
本发明涉及半导体技术领域，特别是涉及一种半导体元件及其制作方法。
背景技术
在现有的高介电常数金属栅极(high-k metal gate)制作工艺中，特别是在用于制造自对准接触(SAC)的阶段，通常先去除金属栅极的一部分，并在金属栅极正上方沉积一保护掩模层。然后，通过化学机械研磨(CMP)制作工艺将沉积的保护掩模层平坦化，使得剩余掩模层的表面与层间电介质(ILD)层的表面平整共面。
然而，上述设计会导致其后形成的接触插塞太靠近金属栅极，从而影响元件的性能。此外，随着元件的微缩，如何降低金属栅极的阻值，以及如何降低接触插塞与金属栅极间的寄生电容，已成为目前该技术领域亟欲克服的问题。
发明内容
本发明的主要目的在于提供一种改良的半导体电结构，可以解决上述现有技术的不足与缺点。
根据本发明一实施例，本发明提供一半导体元件，包含一基底、一金属栅极，设于基底上、一第一层间介电层，设于金属栅极周围，其中金属栅极的上表面低于第一层间介电层的上表面，在金属栅极上构成一凹陷区域。一掩模层，设于凹陷区域内。一孔隙，位于凹陷区域内的掩模层中。一第二层间介电层，设于掩模层及第一层间介电层上。一接触洞，穿过第二层间介电层及掩模层，其中接触洞显露出金属栅极的上表面，并且与孔隙连通。一导电层，填入接触洞内，并延伸进入孔隙中。
根据本发明一实施例，本发明提供一种制作半导体元件的方法，包含：提供一基底；在基底上形成一金属栅极；在金属栅极周围形成一第一层间介电层，其中金属栅极的上表面低于第一层间介电层的上表面，在金属栅极上构成一凹陷区域；在凹陷区域内形成一掩模层；在凹陷区域内的掩模层中形成一孔隙；在掩模层及第一层间介电层上沉积一第二层间介电层；在第二层间介电层及掩模层中形成一接触洞，其中接触洞显露出金属栅极的上表面，并且与孔隙连通；及于接触洞及孔隙内填入一导电层。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图3为本发明一实施例所绘示的一种制作半导体元件的方法的示意图；
图4至图6为本发明另一实施例所绘示的一种制作半导体元件的方法的示意图。
主要元件符号说明
1、1a 半导体元件
10 金属栅极
10a 上表面
10b 凹陷区域
30 接触插塞
100 基底
101 高介电常数介电层
102 导电层
103 钨金属层
104 掩模层
105、106、107 孔隙
110 第一层间介电层
110a 上表面
112 间隙壁
120 第二层间介电层
210 接触洞
300 导电层
301 钛硅化物层
302 钨金属层
具体实施方式
接下来的详细叙述是参照相关附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例已提供足够的细节，可使本领域技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，仍可做结构、步骤或电性上的修改，并应用在其他实施例上。
因此，以下详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具均等意义者，也应属本发明涵盖的范围。
请参阅图1至图3，其为依据本发明一实施例所绘示的一种制作半导体元件1的方法的示意图。如图1所示，首先提供一基底100，例如硅基底，但不限于此。基底100上沉积有一第一层间介电层110，例如，硅氧层，但不限于此。在基底100上的第一层间介电层110中形成一金属栅极10。
熟悉该技术领域者应理解，基底100可以包括掺杂区或离子阱(图未示)。此外，基底100还可以包括鳍状结构(图未示)，以形成鳍式场效晶体管(FinFET)。
根据本发明一实施例，金属栅极10的上表面10a低于第一层间介电层110的上表面110a，在金属栅极10上构成一凹陷区域10b。
根据本发明一实施例，金属栅极10可以包含一高介电常数介电层101、至少一导电层102以及一钨金属层103，其中钨金属层103凸出于金属栅极10的上表面10a。其中，导电层102还可以包括阻障层及功函数金属层。
根据本发明一实施例，金属栅极10与第一层间介电层110之间可以有一间隙壁112，例如氮化硅、氮碳化硅(SiCN)或氮氧化硅(SiON)等，但不限于此。
上述金属栅极10的制作方法可以利用现有的高介电常数金属栅极(high-k metalgate，HKMG)制作工艺来形成，由于HKMG制作工艺为周知技术，故其细节不另赘述。
接着，在金属栅极10上方的凹陷区域10b内沉积一掩模层104，例如氮化硅或氮碳化硅。根据本发明一实施例，掩模层104可以利用化学气相沉积法、原子层沉积法或其他方法沉积而成。
在沉积掩模层104的过程中，可以在凹陷区域10b内的掩模层104中形成孔隙105及106。其中，孔隙105及106分别形成在钨金属层103的两侧，介于钨金属层103与间隙壁112之间。此外，孔隙105及106低于第一层间介电层110的上表面110a。
根据本发明一实施例，在沉积掩模层104之后，可以利用一化学机械研磨(CMP)制作工艺，平坦化掩模层104，使掩模层104的上表面与层间介电层110的上表面110a齐平。
接着，在掩模层104及第一层间介电层110上沉积一第二层间介电层120，例如，硅氧层，但不限于此。
如图2所示，接着于第二层间介电层120及掩模层104中形成一接触洞210。根据本发明一实施例，形成接触洞210的方式可以利用光刻及蚀刻制作工艺。接触洞210的形状不限于图2所示的圆形，可以包含椭圆形、方形、长方形等。此外，接触洞210的形状若为长方形，长轴的方向可平行或垂直于金属栅极10的延伸方向。
根据本发明一实施例，接触洞210显露出金属栅极10的上表面10a及凸出于金属栅极10的上表面10a的钨金属层103，其中接触洞210与孔隙105及106连通。
如图3所示，在接触洞210及孔隙105、106内填入一导电层300。根据本发明一实施例，导电层300可以利用化学气相沉积法、原子层沉积法或其他方法沉积而成。根据本发明一实施例，导电层300可以包含一钛硅化物层301。根据本发明一实施例，导电层300可以包含一钨金属层302。根据本发明一实施例，沉积导电层300后，可以利用一化学机械研磨(CMP)制作工艺，平坦化导电层300，构成一接触插塞30。
结构上，从图3可看出本发明半导体元件1包含基底100、金属栅极10，设于基底100上、第一层间介电层110，设于金属栅极10周围，其中金属栅极10的上表面10a低于第一层间介电层110的上表面110a，在金属栅极10上构成一凹陷区域10b。掩模层104，设于凹陷区域10b内。孔隙105、106，位于凹陷区域10b内的掩模层104中。第二层间介电层120，设于掩模层104及第一层间介电层110上。接触洞210，穿过第二层间介电层120及掩模层104，其中接触洞210显露出金属栅极10的上表面10a，并且与孔隙105、106连通。导电层300，填入接触洞210内，并延伸进入孔隙105、106中。
根据本发明一实施例，掩模层104包含氮化硅或氮碳化硅。根据本发明一实施例，孔隙105、106低于第一层间介电层110的上表面110a。金属栅极10包含一钨金属层103，凸出于金属栅极10的上表面10a。孔隙105、106分别设于钨金属层103的一侧。根据本发明一实施例，导电层300包含一钛硅化物层301及一钨金属层302。
本发明的优点在于，导电层300，填入接触洞210内，并延伸进入孔隙105、106中可以降低金属栅极10及接触插塞30的阻值，且延伸进入孔隙105、106中导电层300可以降低金属栅极10与邻近的其他插塞(图未示)之间的寄生电容，如此提升半导体元件1的效能。
请参阅图4至图6，其为依据本发明另一实施例所绘示的一种制作半导体元件1a的方法的示意图，其中相同的元件、区域或材料层仍沿用相同的符号来表示。
如图4所示，首先提供一基底100，例如硅基底。基底100上沉积有一第一层间介电层110，例如，硅氧层。在基底100上的第一层间介电层110中形成一金属栅极10。金属栅极10的上表面10a低于第一层间介电层110的上表面110a，在金属栅极10上构成一凹陷区域10b。
根据本发明一实施例，金属栅极10可以包含一高介电常数介电层101、至少一导电层102以及一钨金属层103，其中钨金属层103仅略高于金属栅极10的上表面10a。其中，导电层102还可以包括阻障层及功函数金属层。金属栅极10与第一层间介电层110之间可以有一间隙壁112，例如氮化硅、氮碳化硅(SiCN)或氮氧化硅(SiON)等，但不限于此。
接着，在金属栅极10上方的凹陷区域10b内沉积一掩模层104，例如氮化硅或氮碳化硅。根据本发明一实施例，掩模层104可以利用化学气相沉积法、原子层沉积法或其他方法沉积而成。
在沉积掩模层104的过程中，可以在凹陷区域10b内的掩模层104中形成孔隙107。其中，孔隙107形成在钨金属层103的正上方，掩模层104的中央。此外，孔隙107低于第一层间介电层110的上表面110a。
根据本发明一实施例，在沉积掩模层104之后，可以利用一化学机械研磨(CMP)制作工艺，平坦化掩模层104，使掩模层104的上表面与层间介电层110的上表面110a齐平。接着，在掩模层104及第一层间介电层110上沉积一第二层间介电层120，例如，硅氧层，但不限于此。
如图5所示，接着于第二层间介电层120及掩模层104中形成一接触洞210。接触洞210的形状不限于图5所示的圆形，可以包含椭圆形、方形、长方形等。此外，接触洞210的形状若为长方形，长轴的方向可平行或垂直于金属栅极10的延伸方向。
根据本发明一实施例，接触洞210显露出金属栅极10的上表面10a及略微凸出于金属栅极10的上表面10a的钨金属层103，其中接触洞210与孔隙107连通。
如图6所示，在接触洞210及孔隙107内填入一导电层300。根据本发明一实施例，导电层300可以利用化学气相沉积法、原子层沉积法或其他方法沉积而成。根据本发明一实施例，导电层300可以包含一钛硅化物层301。根据本发明一实施例，导电层300可以包含一钨金属层302。根据本发明一实施例，沉积导电层300后，可以利用一化学机械研磨(CMP)制作工艺，平坦化导电层300，构成一接触插塞30。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (18)

1.一种半导体元件，包含：
基底；
金属栅极，设于该基底上；
第一层间介电层，设于该金属栅极周围，其中该金属栅极的上表面低于该第一层间介电层的上表面，在该金属栅极上构成一凹陷区域；
掩模层，设于该凹陷区域内；
孔隙，位于该凹陷区域内的该掩模层中；
第二层间介电层，设于该掩模层及该第一层间介电层上；
接触洞，穿过该第二层间介电层及该掩模层，其中该接触洞显露出该金属栅极的上表面，并且与该孔隙连通；及
导电层，填入该接触洞内，并延伸进入该孔隙中。
2.如权利要求1所述的半导体元件，其中该掩模层包含氮化硅或氮碳化硅。
3.如权利要求1所述的半导体元件，其中该孔隙低于该第一层间介电层的上表面。
4.如权利要求1所述的半导体元件，其中该金属栅极包含钨金属层，凸出于该金属栅极的上表面。
5.如权利要求4所述的半导体元件，其中该孔隙设于该钨金属层的一侧。
6.如权利要求4所述的半导体元件，其中该孔隙位于该钨金属层上方的该掩模层中央。
7.如权利要求1所述的半导体元件，其中该导电层包含钛硅化物层。
8.如权利要求7所述的半导体元件，其中该导电层另包含钨金属层。
9.如权利要求1所述的半导体元件，其中该掩模层的上表面与该第一层间介电层的上表面齐平。
10.一种制作半导体元件的方法，包含：
提供一基底；
在该基底上形成一金属栅极；
在该金属栅极周围形成一第一层间介电层，其中该金属栅极的上表面低于该第一层间介电层的上表面，在该金属栅极上构成一凹陷区域；
在该凹陷区域内形成一掩模层；
在该凹陷区域内的该掩模层中形成一孔隙；
在该掩模层及该第一层间介电层上沉积一第二层间介电层；
在该第二层间介电层及该掩模层中形成一接触洞，其中该接触洞显露出该金属栅极的上表面，并且与该孔隙连通；及
在该接触洞及该孔隙内填入一导电层。
11.如权利要求10所述的方法，其中该掩模层包含氮化硅或氮碳化硅。
12.如权利要求10所述的方法，其中该孔隙低于该第一层间介电的上表面。
13.如权利要求10所述的方法，其中该金属栅极包含钨金属层，凸出于该金属栅极的上表面。
14.如权利要求13所述的方法，其中该孔隙设于该钨金属层的一侧。
15.如权利要求13所述的方法，其中该孔隙位于该钨金属层上方的该掩模层中央。
16.如权利要求10所述的方法，其中该导电层包含钛硅化物层。
17.如权利要求16所述的方法，其中该导电层另包含钨金属层。
18.如权利要求10所述的方法，其中该掩模层的上表面与该第一层间介电层的上表面齐平。
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