CN109494246A - 超结mosfet结构及其制造方法 - Google Patents

超结mosfet结构及其制造方法 Download PDF

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CN109494246A
CN109494246A CN201811187899.7A CN201811187899A CN109494246A CN 109494246 A CN109494246 A CN 109494246A CN 201811187899 A CN201811187899 A CN 201811187899A CN 109494246 A CN109494246 A CN 109494246A
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CN109494246B (zh
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肖晓军
周宏伟
张园园
徐永年
任文珍
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Longteng Semiconductor Co.,Ltd.
Xi'an Longxiang Semiconductor Co.,Ltd.
Xusi semiconductor (Shanghai) Co.,Ltd.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

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Abstract

本发明涉及一种超结MOSFET结构及其制造方法，该方法通过对具有高深宽比超结结构的P柱进行间隔刻蚀，刻蚀后再进行N型外延，使被刻蚀的P柱浮置于Pbody下方，为上方的Pbody浓度调整及阈值电压调整提供可优化空间，减少pbody间的颈区电阻。本发明结构的栅漏电容相对常规超结结构偏大，并且随漏源电压变化平缓，可有效降低器件的EMI影响，同时本发明结构可有效降低器件的Coss,减小Eoss,提升器件工作的转换效率，为阈值电压及雪崩耐久性的优化调整提供了设计和工艺空间。

Description

超结MOSFET结构及其制造方法
技术领域
本发明涉及一种车体表面防护附件，具体涉及一种超结MOSFET结构及其制造方法。
背景技术
传统功率VDMOS器件的导通电阻和击穿电压存在2.5次方的关系，这种关系被人们称为“硅限”，这种“极限”是器件功耗进一步降低的瓶颈。为了突破硅限，器件理论提出了超结结构，超结结构其耐压层由构成超结层的 P 柱与 N 柱交叠周期排列，在横向上 N 柱与P 柱需满足电荷平衡，当超结层全部耗尽时，其扮演着类似PIN结构的支撑电压层的角色。如果电压进一步升高，电场就会在空间电荷层没有进一步扩展的情况下线性的增强，这使得可以在耐压相同的基础上，将漂移区中n型柱状半导体的浓度做的比传统功率MOSFET的漂移区的浓度高。但如果漂移区浓度过大，会导致器件反偏时超结结构中P柱和N柱之间很难横向耗尽，横向的电场强度增大，从而影响器件的击穿电压。因此为了在保证耐压的基础上，提高器件的功率密度，提升效率，就必须使横向的P柱及N柱尺寸尽可能缩减。
目前，随着超结技术的发展，元胞尺寸的不断降低，功率密度在不断提升，开关速度在加快。但功率MOSFET作为功率开关管，由于工作在on-off的快速循环转换的状态，其电压电流都在急剧变化，是电场耦合和磁场耦合的主要干扰源，是开关电源等电路EMI的主要来源之一。
发明内容
本发明的目的是提供一种超结MOSFET结构及其制造方法，在保障耐压及功率密度提升的基础上，通过优化的电容特性降低器件的EMI影响，同时为阈值电压及雪崩耐久性的优化调整提供了设计和工艺空间。
本发明所采用的技术方案为：
超结MOSFET结构的制造方法，其特征在于：
该方法通过对具有高深宽比超结结构的P柱进行间隔刻蚀，刻蚀后再进行N型外延，使被刻蚀的P柱浮置于Pbody下方，为上方的Pbody浓度调整及阈值电压调整提供可优化空间，减少pbody间的颈区电阻。
具体由以下步骤实现：
步骤一：在N+衬底上生长一层电阻率稍高的外延N-；
步骤二：通过Trench光刻板，刻蚀出深沟槽；
步骤三：在N-外延表面，生长P型外延，使之填充满沟槽；
步骤四：对P柱进行间隔刻蚀，刻蚀出3um-5um的浅槽；
步骤五：在表面生长N型外延，使之填满浅槽，并进行CMP工艺，将沟槽外的P型外延及N型外延一并去掉，形成N柱P柱相交替的超结结构；
步骤六：通过Body光刻板注入体区并退火形成body区，淀积场氧层成并回刻，通过栅氧、多晶硅淀积回刻形成gate，再注入As或P并推阱形成N-source；
步骤七：淀积ILD并回刻，孔注，最后淀积金属并回刻，形成器件的最终结构。
如所述的制造方法制得的超结MOSFET结构。
本发明具有以下优点：
本发明结构的栅漏电容相对常规超结结构偏大，并且随漏源电压变化平缓，可有效降低器件的EMI影响，同时本发明结构可有效降低器件的Coss,减小Eoss,提升器件工作的转换效率，为阈值电压及雪崩耐久性的优化调整提供了设计和工艺空间。
附图说明
图1为步骤一示意图。
图2为步骤二示意图。
图3为步骤三示意图。
图4为步骤四示意图。
图5为步骤五示意图。
图6为步骤六示意图。
图7为步骤七示意图。
图8为本发明结构仿真对比示意图（一）。
图9为本发明结构仿真对比示意图（二）。
具体实施方式
下面结合具体实施方式对本发明进行详细的说明。
本发明涉及一种超结MOSFET结构及其制造方法，通过对具有高深宽比超结结构的P柱进行间隔刻蚀，刻蚀后再进行N型外延，使被刻蚀的P柱浮置于Pbody下方，为上方的Pbody浓度调整及阈值电压调整提供可优化空间，减少pbody间的颈区电阻，具体的实现方法如下：
步骤一：在N+衬底上生长一层电阻率稍高的外延N-（图1）。
步骤二：通过Trench光刻板，刻蚀出深沟槽（图2）。
步骤三：在N-外延表面，生长一定浓度的P型外延，使之填充满沟槽（图3）。
步骤四：对P柱进行间隔刻蚀，刻蚀出3um-5um的浅槽（图4）。
步骤五：在表面生长一定浓度的N型外延，使之填满浅槽，并进行CMP工艺，将沟槽外的P型外延及N型外延一并去掉，形成N柱P柱相交替的超结结构（图5）。
步骤六：通过Body光刻板注入体区并退火形成body区，淀积场氧层成并回刻，通过栅氧、多晶硅淀积回刻形成gate，再注入As（或P）并推阱形成N-source（图6）。
步骤七：淀积ILD并回刻，孔注，最后淀积金属并回刻，形成器件的最终结构（图7）。
通过对本发明结构(相邻body颈区下方有P柱)进行仿真（图8和9），并与常规超结结构进行对比，本发明结构的栅漏电容相对常规超结结构偏大，并且随漏源电压变化平缓，可有效降低器件的EMI影响，同时本发明结构可有效降低器件的Coss，减小Eoss，提升器件工作的转换效率。
本发明的内容不限于实施例所列举，本领域普通技术人员通过阅读本发明说明书而对本发明技术方案采取的任何等效的变换，均为本发明的权利要求所涵盖。

Claims (3)

1.超结MOSFET结构的制造方法，其特征在于：
该方法通过对具有高深宽比超结结构的P柱进行间隔刻蚀，刻蚀后再进行N型外延，使被刻蚀的P柱浮置于Pbody下方，为上方的Pbody浓度调整及阈值电压调整提供可优化空间，减少pbody间的颈区电阻。
2.根据权利要求1所述的超结MOSFET结构的制造方法，其特征在于：
具体由以下步骤实现：
步骤一：在N+衬底上生长一层电阻率稍高的外延N-；
步骤二：通过Trench光刻板，刻蚀出深沟槽；
步骤三：在N-外延表面，生长P型外延，使之填充满沟槽；
步骤四：对P柱进行间隔刻蚀，刻蚀出3um-5um的浅槽；
步骤五：在表面生长N型外延，使之填满浅槽，并进行CMP工艺，将沟槽外的P型外延及N型外延一并去掉，形成N柱P柱相交替的超结结构；
步骤六：通过Body光刻板注入体区并退火形成body区，淀积场氧层成并回刻，通过栅氧、多晶硅淀积回刻形成gate，再注入As或P并推阱形成N-source；
步骤七：淀积ILD并回刻，孔注，最后淀积金属并回刻，形成器件的最终结构。
3.如权利要求1或2所述的制造方法制得的超结MOSFET结构。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116031303A (zh) * 2023-02-09 2023-04-28 上海功成半导体科技有限公司 超结器件及其制作方法和电子器件
CN116613190A (zh) * 2023-06-02 2023-08-18 上海功成半导体科技有限公司 一种超结器件及电子器件
CN116613190B (zh) * 2023-06-02 2024-05-31 上海功成半导体科技有限公司 一种超结器件及电子器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1317833A (zh) * 2000-04-12 2001-10-17 株式会社东芝 半导体器件及其制造方法
JP2009200264A (ja) * 2008-02-21 2009-09-03 Fuji Electric Device Technology Co Ltd 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1317833A (zh) * 2000-04-12 2001-10-17 株式会社东芝 半导体器件及其制造方法
JP2009200264A (ja) * 2008-02-21 2009-09-03 Fuji Electric Device Technology Co Ltd 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116031303A (zh) * 2023-02-09 2023-04-28 上海功成半导体科技有限公司 超结器件及其制作方法和电子器件
CN116031303B (zh) * 2023-02-09 2023-11-21 上海功成半导体科技有限公司 超结器件及其制作方法和电子器件
CN116613190A (zh) * 2023-06-02 2023-08-18 上海功成半导体科技有限公司 一种超结器件及电子器件
CN116613190B (zh) * 2023-06-02 2024-05-31 上海功成半导体科技有限公司 一种超结器件及电子器件

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