CN109494212B - 电子部件 - Google Patents

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Publication number
CN109494212B
CN109494212B CN201811062926.8A CN201811062926A CN109494212B CN 109494212 B CN109494212 B CN 109494212B CN 201811062926 A CN201811062926 A CN 201811062926A CN 109494212 B CN109494212 B CN 109494212B
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pad
device chips
substrate
bumps
electronic component
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CN109494212A (zh
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山内基
远藤祐喜
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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Abstract

电子部件。一种电子部件包括：四个器件芯片，其具有矩形平面形状并且被布置在基板上，使得一个器件芯片的作为构成矩形的四个角中的一个角部与其余三个器件芯片的所述角部相邻；位于四个器件芯片的表面上并且最靠近所述角部的第一焊盘；在四个器件芯片中将第一焊盘接合到基板的一个或更多个第一凸块；位于四个器件芯片的表面上的第二焊盘，第二焊盘是除第一焊盘之外的焊盘中的一个；以及在四个器件芯片中将第二焊盘接合到基板的一个或更多个第二凸块，一个或更多个第二凸块与第二焊盘之间的接合面积的和小于第一焊盘与一个或更多个第一凸块之间的接合面积的和。

Description

电子部件
技术领域
本发明的某个方面涉及一种电子部件。
背景技术
例如，如日本专利申请公开No.2015-41760(以下称为专利文献1)中所公开的，已知通过使用具有不同尺寸的凸块(bump)将器件芯片安装在基板上来改善凸块和焊盘之间的连接。例如，如日本专利申请公开No.H11-111771(以下称为专利文献2)中所公开的，已知通过在器件芯片的四个角处提供大的焊料凸块来消除对安装机器的高精度位置控制的需要。
发明内容
根据本发明的一个方面，提供了一种电子部件，所述电子部件包括：基板；四个器件芯片，每个器件芯片都具有矩形平面形状，四个器件芯片被布置在基板上，使得四个器件芯片中的一个器件芯片的作为构成矩形的四个角中的一个角部与四个器件芯片中的其余三个器件芯片中的每一个的所述角部相邻；位于四个器件芯片中的每一个的基板侧的表面上并且最靠近所述角部的第一焊盘；在四个器件芯片中的每一个中将第一焊盘接合到基板的一个或更多个第一凸块；位于四个器件芯片中的每一个的基板侧的表面上的第二焊盘，第二焊盘是除第一焊盘之外的焊盘中的一个；以及在四个器件芯片中的每一个中将第二焊盘接合到基板的一个或更多个第二凸块，一个或更多个第二凸块与第二焊盘之间的接合面积的和小于第一焊盘与一个或更多个第一凸块之间的接合面积的和。
附图说明
图1是根据第一实施方式的电子部件的电路图；
图2A和图2B分别是第一实施方式的电子部件的截面图和平面图；
图3是第一实施方式中的滤波器的电路图；
图4是第一实施方式中的器件芯片的平面图；
图5A和图5B例示了示例性声波谐振器；
图6A和图6B是用于描述第一实施方式中的优点的示意性截面图；
图7是模拟1中的样品的截面图；
图8A是模拟1中的基板10的上表面的平面图，并且图8B是布线22c的平面图；
图9A和图9B是模拟1中应力相对于凸块的直径
Figure BDA0001797567140000021
的图；
图10是模拟2中的样品的平面图；
图11A至图11D是模拟2中应力相对于凸块的直径
Figure BDA0001797567140000022
的图(No.1)；
图12A至图12D是模拟2中应力相对于凸块的直径
Figure BDA0001797567140000023
的图(No.2)；以及
图13是根据第一实施方式的第一变型的电子部件的平面图。
具体实施方式
在专利文献1和2中，没有考虑温度载荷的影响。当多个器件芯片被安装在基板上时，由于温度载荷等而对凸块施加大应力。因此，基板和器件芯片之间的接合的可靠性可能降低。随着凸块的直径增加，施加到凸块的应力减小。然而，凸块的较大直径增加了电子部件的尺寸。
下文中，将参考附图给出实施方式的描述。
第一实施方式
第一实施方式是作为电子部件的示例性的四路复用器(quadplexer)。图1是根据第一实施方式的电子部件的电路图。如图1所示，四路复用器包括滤波器51至54。滤波器51至54分别连接在公共端子Ant和信号端子T1至T4之间。例如，滤波器51和54分别是用于频带B1的发送滤波器和接收滤波器。滤波器52和53分别是用于频带B2的发送滤波器和接收滤波器。频带B1和频带B2是长期演进(LTE)频带(演进型通用陆地无线接入(E-UTRA)工作频带)的频带。
滤波器51将输入到信号端子T1的高频信号中的、频带B1的发送频带中的信号输出到公共端子Ant，并且抑制其他信号。滤波器54将输入到公共端子Ant的高频信号中的、频带B1的接收频带中的信号输出到信号端子T4，并且抑制其他信号。滤波器52将输入到信号端子T2的高频信号中的、频带B2的发送频带中的信号输出到公共端子Ant，并且抑制其他信号。滤波器53将输入到公共端子Ant的高频信号中的、频带B2的接收频带中的信号输出到信号端子T3，并且抑制其他信号。
图2A和图2B分别是第一实施方式的电子部件的截面图和平面图。图2B是基板20的顶视图，并且用虚线表示器件芯片11a至11d。如图2A所示，基板20包括一个或更多个绝缘层20a和20b。绝缘层20a和20b例如是由高温共烧陶瓷(HTCC)或低温共烧陶瓷(LTCC)制成的陶瓷层、或树脂层。
焊盘24和24a以及环形金属层28位于基板20的上表面上。端子26位于基板20的下表面上。端子26例如是公共端子Ant、信号端子T1至T4以及连接到滤波器51至54的地的接地端子。内部布线22包括通孔布线22a和22b以及布线22c。通孔布线22a和22b分别穿透绝缘层20a和20b。布线22c位于绝缘层20a和20b之间。内部布线22将焊盘24和24a电连接到端子26。内部布线22、焊盘24和24a、端子26和环形金属层28例如由诸如铜层、铝层、金层或钨层的金属层形成。
器件芯片11对应于器件芯片11a至11d中的每一个，并且包括基板10、功能元件12以及焊盘14和14a。功能元件12以及焊盘14和14a位于基板10的下表面上。功能元件12对应于滤波器51至54中的每一个，并且隔着气隙32面向基板20。基板10例如是钽酸锂基板或铌酸锂基板。焊盘14和14a例如由诸如铜层、铝层或金层的金属层形成。器件芯片11通过凸块16和16a按照倒装芯片方式被安装(面朝下安装)在基板20上。凸块16和16a例如是金凸块、焊料凸块或铜凸块。凸块16接合焊盘24和14，并且凸块16a接合焊盘24a和14a。
密封部30位于基板20上以便覆盖器件芯片11。密封部30被接合到环形金属层28。密封部30例如由焊料制成的金属层或树脂层形成。盖可以位于密封部30和器件芯片11上。通过密封部30将功能元件12密封在气隙32中。
如图2B所示，四个器件芯片11a至11d按照倒装芯片方式被安装在基板20上。器件芯片11a至11d中的每一个的平面形状是矩形(例如，矩形或正方形)。作为功能元件12的滤波器51至54分别位于器件芯片11a至11d的下表面上。器件芯片11a至11d中的每一个的四个角中的一个面向其余器件芯片中的每一个的四个角中的一个。例如，器件芯片11a的四个边中的两个边面向相邻的器件芯片11b和11c。相对的边大体上平行。
焊盘24包括信号焊盘Pt2和接地焊盘Pg2。焊盘24a包括公共焊盘Pa2。在四个器件芯片11a至11d中的每一个中，靠近基板20的中心的焊盘24a是公共焊盘Pa2，并且与公共焊盘Pa2成对角设置的焊盘24是信号焊盘Pt2。其他焊盘24是接地焊盘Pg2。公共焊盘Pa2通过内部布线22电连接到公共端子Ant。信号焊盘Pt2通过内部布线22电连接到信号端子T1至T4。接地焊盘Pg2通过内部布线22电连接到接地端子。
器件芯片11a至11d的公共焊盘Pa2一起位于基板20的中心周围。该结构使得滤波器51至54与公共端子Ant之间的电气长度彼此大致相等。因此，滤波器51至54易于匹配。在器件芯片11a至11d中的每一个中，信号焊盘Pt2与公共焊盘Pa2对角地定位。该结构阻止了输入到信号焊盘Pt2的发送信号泄漏到公共焊盘Pa2。另外，阻止了从公共焊盘Pa2输出的发送信号泄漏到信号焊盘Pt2。因此，改善了从发送端子到接收端子的隔离。用于相同频带的发送滤波器和接收滤波器优选彼此对角地定位。例如，滤波器51至54分别被安装到器件芯片11a至11d。该配置改善了从相同频带的发送端子到接收端子的隔离。
将通过利用器件芯片11a的滤波器51作为示例来描述器件芯片11a至11d和滤波器51至54。图3是第一实施方式中的滤波器的电路图。如图3所示，串联谐振器S1至S5串联连接在公共端子Ant和信号端子T1之间，并且并联谐振器P1至P4并联连接在公共端子Ant和信号端子T1之间。串联谐振器S1至S5串联地分别分为S1a和S1b、S2a和S2b、S3a和S3b、S4a和S4b以及S5a和S5b。
图4是第一实施方式中的器件芯片的平面图。图4透视地示出了从上方观察的基板10的下表面。如图4所示，声波谐振器40、布线13以及焊盘14和14a位于基板10的下表面上。声波谐振器40包括叉指换能器(IDT)41和反射器42。布线13电连接声波谐振器40或将声波谐振器40电连接到焊盘14和14a。凸块16和16a分别接合到焊盘14和14a。声波谐振器40包括串联谐振器S1至S5和并联谐振器P1至P4。焊盘14包括信号焊盘Pt1、接地焊盘Pg1和虚设焊盘Pd1。焊盘14a包括公共焊盘Pa1。虚设焊盘Pd1未连接到器件芯片11中的声波谐振器40，并且与凸块接合以确保机械强度。
公共焊盘Pa1通过凸块16a电连接到公共焊盘Pa2。信号焊盘Pt1通过凸块16电连接到信号焊盘Pt2。接地焊盘Pg1和虚设焊盘Pd1通过凸块16连接到接地焊盘Pg2。
图5A和图5B示出了示例性声波谐振器。在图5A中声波谐振器是表面声波谐振器，并且在图5B中是压电薄膜谐振器。
如图5A所示，在基板10上形成IDT 41和反射器42。IDT 41包括面向彼此的一对梳形电极41a。梳形电极41a包括电极指41b和连接电极指41b的汇流条41c。反射器42位于IDT41的两侧。IDT 41在基板10上激发表面声波。基板10例如是诸如钽酸锂基板或铌酸锂基板的压电基板。IDT 41和反射器42例如由铝膜或铜膜形成。基板10可以接合到支撑基板(诸如，蓝宝石基板、氧化铝基板、尖晶石基板、结晶基板或硅基板)。可以提供覆盖IDT 41和反射器42的保护膜或温度补偿膜。在这种情况下，表面声波滤波器和保护膜或温度补偿膜整体上用作声波谐振器40。
如图5B所示，压电膜46位于基板10上。下电极44和上电极48被定位成夹着压电膜46。在下电极44和基板10之间形成气隙45。下电极44和上电极48以厚度延伸模式在压电膜46中激励声波。下电极44和上电极48例如由诸如钌膜的金属膜形成。压电膜46例如是氮化铝膜。基板10例如是半导体基板(诸如，硅基板或砷化镓)或绝缘基板(诸如，蓝宝石基板、氧化铝基板、尖晶石基板或玻璃基板)。如图5A和图5B所示，声波谐振器40包括激励声波的电极。因此，声波谐振器40利用气隙32覆盖，以便不限制声波的振动。
在第一实施方式中，位于器件芯片11a至11d的彼此面向的角部处的凸块16a的直径大于其他凸块16的直径。例如，凸块16和16a的直径分别为60μm和120μm。
图6A和图6B是用于描述第一实施方式中的优点的示意性截面图。如图6A所示，基板10通过凸块16或16a接合在基板20上。由于基板20和10之间的线性热膨胀系数的差异，大的力60被施加于靠近基板20的中心的凸块16或16a。应力由力/横截面积表示。因此，使施加大的热应力的、靠近基板20的中心的凸块16a比凸块16大。该配置减小了施加到凸块16a的应力。
如图6B所示，来自作为热源的IDT 41的热量通过凸块16或16a流到基板20。当使凸块16a的横截面积大于凸块16的横截面积时，从IDT 41到基板20的热流从由箭头62表示的热流变为由箭头62a表示的增加的热流。因此，降低了基板10的温度升高。在基板20的外围，可以通过密封部30释放热量，但是在基板20的中心附近难以通过密封部30释放热量。第一实施方式提高了基板20的中心附近的散热性能。
另一方面，通过减小施加小应力的凸块16的横截面积，减小了电子部件的尺寸。
模拟1
模拟了第一实施方式中施加到凸块16a的应力。作为第一比较例，还模拟了使用具有小直径的凸块16而非凸块16a的样品。
图7是模拟1中的样品的截面图，图8A是基板10的上表面的平面图，并且图8B是布线22c的平面图。在图8A中，用虚线表示器件芯片11a至11d。如图7至图8B所示，基板20的较长边的延伸方向被定义为X方向，较短边的延伸方向被定义为Y方向，并且基板20的上表面的法线方向被定义为Z方向。布线22c被布置成跨绝缘层20a和20b之间的整个表面。焊盘24具有与器件芯片11a至11d相同的平面形状。
第一实施方式的模拟1的条件如下。
基板10：长度Lx1＝2.5mm，长度Ly1＝2.0mm
绝缘层20a：厚度t1为85μm的HTCC
绝缘层20b：厚度t3为10μm的HTCC
布线22c：厚度t2为10μm的钨
焊盘24、环形金属层28：厚度t4为15μm的钨
凸块16：高度t5为12.5μm、直径
Figure BDA0001797567140000061
为60μm的金
凸点16a：高度t5为12.5μm、直径
Figure BDA0001797567140000062
为120μm的金
器件芯片11a至11d：42°旋转Y向切割X向传播的钽酸锂基板，其厚度t6为0.15mm，长度Lx2为1.01mm，长度Ly2为0.77mm，其中，Y方向对应于晶体取向的X轴取向。
模拟1中使用的每种材料的杨氏模量、泊松比和线性热膨胀系数如下。金具有7.72×1010GPa的杨氏模量、0.42的泊松比以及1.44×10-5/℃的线性热膨胀系数。钽酸锂具有2.54×1011GPa的杨氏模量、0.21的泊松比以及0.95×10-5/℃(X方向)、1.61×10-5/℃(Y方向)和1.07×10-5/℃(Z方向)的线性热膨胀系数。HTCC具有3.1×1011GPa的杨氏模量、0.24的泊松比以及0.71×10-5/℃的线性热膨胀系数。钨具有4.0×1011GPa的杨氏模量、0.28的泊松比以及0.44×10-5/℃的线性热膨胀系数。由于器件芯片11a至11d的焊盘14和14a很薄，所以它们忽略不计。
计算出凸块16a和焊盘24之间的边界面中的Z方向上的应力的最大值以及凸块16a和器件芯片11a至11d之间的边界面中的Z方向上的应力的最大值。它们是针对150℃和-65℃的温度计算出的。作为第一比较例，还计算出当使用具有60μm的直径的凸块16代替凸块16a时的应力。
图9A和图9B是模拟1中应力相对于凸块的直径
Figure BDA0001797567140000071
的图。图9A例示了凸块16a和器件芯片11a至11d之间的边界面(表示为“器件芯片侧”)中的应力，并且图9B例示了凸块16a和焊盘24a之间的边界面(表示为“基板侧”)中的应力。器件芯片11a至11d的尺寸Lx2×Ly2是相同的，并且因此，在器件芯片11a至11d中施加到凸块16a的应力是相同的。
如图9A和图9B所示，在凸块16a的直径
Figure BDA0001797567140000072
为120μm的第一实施方式中的应力小于在直径
Figure BDA0001797567140000073
为60μm的第一比较例中的应力。
模拟2
作为模拟2，计算出在器件芯片11a至11d的平面形状彼此不同的情况下施加到凸块16a的应力。
图10是模拟2中的样品的平面图。器件芯片11a至11d的平面形状彼此不同。焊盘24具有与各个器件芯片11a至11d相同的平面形状。假设器件芯片11a至11d的尺寸如下。
器件芯片11a：Lx2a＝1.07mm，Ly2a＝0.77mm
器件芯片11b：Lx2b＝0.94mm，Ly2b＝0.70mm
器件芯片11c：Lx2c＝0.84mm，Ly2c＝0.77mm
器件芯片11d：Lx2d＝1.01mm，Ly2d＝0.60mm
其他模拟条件与模拟1中的那些条件相同。
图11A至图12D是模拟2中应力相对于凸块的直径
Figure BDA0001797567140000074
的图。图11A和图11B例示了器件芯片11a的凸块16a中的应力。图11C和图11D例示了器件芯片11b的凸块16a中的应力。图12A和图12B例示了器件芯片11c的凸块16a中的应力。图12C和图12D例示了器件芯片11d的凸块16a中的应力。图11A、图11C、图12A和图12C分别例示了凸块16a和器件芯片11a至11d之间的边界面(表示为“器件芯片侧”)中的应力。图11B、图11D、图12B和图12D例示了凸块16a和焊盘24a之间的边界面(表示为“基板侧”)中的应力。
如图11A至图12D所示，在器件芯片11a至11d中的任何一个中，凸块16a的直径
Figure BDA0001797567140000075
为120μm的第一实施方式中的应力小于直径
Figure BDA0001797567140000076
为60μm的第一比较例中的应力。如上所述，不管器件芯片11a至11d的尺寸如何，第一实施方式中施加到凸块16a的应力小于第一比较例中的应力。
如模拟1和2中所述，第一实施方式减小了施加到凸块16a的应力。
第一实施方式的第一变型
图13是根据第一实施方式的第一变型的电子部件的平面图，并且是基板20的顶视图，并且用虚线表示器件芯片。如图13所示，具有与其他凸块16相同直径的凸块16b位于焊盘24a上。其他结构与第一实施方式的结构相同，并且因此省略其描述。
如在第一实施方式的第一变型中，多个凸块16b可以位于焊盘24a上。也就是说，如果位于单个焊盘24a上的凸块16a或16b的总面积大于另一个凸块16的面积就足够了。
在第一实施方式及其变型中，器件芯片11a至11d中的每一个的四个角中的一个与其余器件芯片中的每一个的四个角中的一个相邻。也就是说，四个器件芯片11a至11d被布置在基板10上，使得一个器件芯片的作为构成矩形的四个角中的一个角的角部与其他三个器件芯片中的每一个的作为构成矩形的四个角中的一个角的角部相邻。焊盘14a(第一焊盘)是位于器件芯片11a至11d中的每一个的基板10侧的表面上的焊盘14和14a中、最靠近相邻角部的焊盘。一个或更多个凸块16a或16b(第一凸块)将焊盘14a接合到基板20。焊盘14(第二焊盘)是焊盘14和14a中除焊盘14a之外的焊盘中的一个。凸块16(第二凸块)将焊盘14接合到基板20。
在这种结构中，使平面图中的一个凸块16的面积小于平面图中接合到一个焊盘14a的一个或更多个凸块16a或16b的面积的和。例如，在单个焊盘14上可以设置多个凸块16。例如，使焊盘14与位于单个焊盘14上的一个或更多个凸块16之间的接合面积的和小于焊盘14a与一个或更多个凸块16a或16b之间的接合面积的和。
该结构减小了施加到位于基板20的中心附近的凸块16a或16b的应力，由于温度载荷，对该凸块施加了大应力。另外，通过使施加了小应力的凸块16变小，减小了电子部件的尺寸。例如，可以使焊盘14比焊盘14a小。另外，改善了散热性能。
当平面图中的凸块16和16a的面积在Z方向上彼此不同时，平面图中的面积例如可以是最大面积、最小面积或平均面积。在生产误差的程度上，平面图中的凸块16的面积可以彼此大致相等或者彼此不同。在生产误差的程度上，在器件芯片11a至11d中，平面图中的一个或更多个凸块16a或16b的面积(例如，接合面积)的和可以彼此大体上相等或彼此不同。
在四个器件芯片11a至11d中的一个中，焊盘14与一个或更多个凸块16之间的接合面积的和优选地等于或小于焊盘14a与一个或更多个凸块16a或16b之间的接合面积的和的三分之二、更优选地等于或小于其一半，进一步优选地等于或小于其三分之一。焊盘14与一个或更多个凸块16中的一个之间的接合面积优选地小于焊盘14a与一个或更多个凸块16a或16b的接合面积的和，更优选地为焊盘14a与一个或更多个凸块16a或16b之间的接合面积的和的三分之二、进一步优选地为其一半、更进一步优选地为其三分之一。
如在第一实施方式中，仅一个凸块16a被接合到每个焊盘14a。该结构减小了施加到凸块16a的应力。例如，当通过电镀形成凸块16和16a时，容易使平面图中的凸块16和16a的面积彼此不同。
如在第一实施方式的第一变型中，多个凸块16b被接合到每个焊盘14a。该结构减小了施加到凸块16b的应力。
在生产误差的程度上，凸块16b中的一个与焊盘14a之间的接合面积大致等于凸块16与焊盘14之间的接合面积。例如，当凸块16和16b由柱形凸块(stud bumps)形成时，难以使平面图中的面积不同。因此，通过将具有与凸块16相同面积的凸块16b设置到焊盘14a来减少了制造步骤的数量。
四个器件芯片11a至11d中的相邻两个器件芯片(例如，器件芯片11a和11b)的相邻的两个边大体上平行。该结构减小了器件芯片11a至11d的安装面积。
器件芯片11a至11d中的每一个都包括作为隔着气隙32面向基板20的功能元件12的声波元件。功能元件12可以是连接在输入端子(例如，公共端子或接收端子)和输出端子(例如，发送端子或公共端子)之间的声波滤波器。
当连接到输入端子或输出端子的凸块劣化时，高频特性劣化。因此，焊盘14a优选地连接到输入端子或输出端子。
滤波器51至54分别连接在公共端子Ant和信号端子T1至T4之间。在这种情况下，焊盘14a优选地连接到公共端子Ant。该配置减少了高频特性的劣化。
如图2B所示，在平面图中器件芯片11a和11d被对角地布置。在平面图中，器件芯片11b和11c被对角地布置。滤波器51和54分别是用于频带B1(第一频带)的接收滤波器和发送滤波器。滤波器52和滤波器53分别是用于与频带B1不同的频带B2(第二频带)的接收滤波器和发送滤波器。该配置允许将接收滤波器的接收端子布置得远离用于同一频带的发送滤波器的发送端子。因此，使发送和接收之间的隔离变大。特别地，当频带B1和/或B2是频分双工(FDD)方法的频带时，由于在频带上接收频带不与发送频带交叠，所以发送和接收之间的隔离是重要的。因此，滤波器51和54优选地是用于频带B1的接收滤波器和发送滤波器，并且滤波器52和53优选地是用于频带B2的接收滤波器和发送滤波器。
作为功能元件12的示例已经描述了声波元件，但是功能元件12可以是诸如电感或电容的无源元件、诸如功率放大器或开关的有源元件或者微机电系统(MEMS)元件。
作为使用四个滤波器的示例，已经描述了四路复用器，但是可以采用其他多路复用器。在基板20上可以安装五个或更多个器件芯片。
尽管已经详细描述了本发明的实施方式，但是应该理解，在不脱离本发明的精神和范围的情况下，可以对其进行各种改变、替换和变更。

Claims (12)

1.一种电子部件，包括：
基板；
四个器件芯片，每个器件芯片都具有矩形平面形状，所述四个器件芯片被布置在所述基板上，使得所述四个器件芯片中的一个器件芯片的作为构成矩形的四个角中的一个角的角部与所述四个器件芯片中的其余三个器件芯片中的每一个的所述角部相邻；
位于所述四个器件芯片中的每一个的基板侧的表面上并且最靠近所述角部的第一焊盘；
在所述四个器件芯片中的每一个中将所述第一焊盘接合到所述基板的一个或更多个第一凸块；
位于所述四个器件芯片中的每一个的所述基板侧的表面上的第二焊盘，所述第二焊盘是除所述第一焊盘之外的焊盘中的一个；以及
在所述四个器件芯片中的每一个中将所述第二焊盘接合到所述基板的一个或更多个第二凸块，所述第二焊盘与所述一个或更多个第二凸块之间的接合面积的和小于所述第一焊盘与所述一个或更多个第一凸块之间的接合面积的和，
其中，所述第二焊盘位于所述四个器件芯片中的每一个的所述基板侧的表面上并且最靠近相对于所述角部呈对角的角部，并且
其中，在所述四个器件芯片中的每一个中，与所述一个或更多个第二凸块相比，所述一个或更多个第一凸块更靠近所述基板的中心。
2.根据权利要求1所述的电子部件，其中，
在所述四个器件芯片中的一个中，所述第二焊盘与所述一个或更多个第二凸块之间的接合面积的和等于或小于所述第一焊盘与所述一个或更多个第一凸块之间的接合面积的和的三分之二。
3.根据权利要求1或2所述的电子部件，其中，
在所述四个器件芯片中的每一个中，仅一个第一凸块与所述第一焊盘接合。
4.根据权利要求1或2所述的电子部件，其中，
在所述四个器件芯片中的每一个中，多个第一凸块与所述第一焊盘接合。
5.根据权利要求4所述的电子部件，其中，
在所述四个器件芯片中的每一个中，所述第一焊盘与多个所述第一凸块中的一个之间的接合面积等于所述第二焊盘与所述一个或更多个第二凸块中的一个之间的接合面积。
6.根据权利要求1或2所述的电子部件，其中，
所述四个器件芯片中的相邻两个器件芯片的相邻的两个边平行。
7.根据权利要求1或2所述的电子部件，其中，
所述四个器件芯片中的每一个都包括隔着气隙面向所述基板的声波元件。
8.根据权利要求1或2所述的电子部件，其中，
所述四个器件芯片中的每一个都包括隔着气隙面向所述基板并且连接在输入端子和输出端子之间的声波滤波器。
9.根据权利要求8所述的电子部件，其中，
所述第一焊盘连接至所述输入端子或所述输出端子。
10.根据权利要求1或2所述的电子部件，其中，
所述四个器件芯片中的每一个都包括隔着气隙面向所述基板并且连接在公共端子和信号端子之间的声波滤波器，并且
所述第一焊盘连接至所述公共端子。
11.根据权利要求1或2所述的电子部件，其中，
在所述四个器件芯片中的每一个中，所述第二焊盘与所述一个或更多个第二凸块中的一个之间的接合面积小于所述第一焊盘与所述一个或更多个第一凸块之间的接合面积的和。
12.根据权利要求1或2所述的电子部件，其中，
在所述四个器件芯片中的每一个中，仅一个第二凸块与所述第二焊盘接合。
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