CN109427907B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN109427907B
CN109427907B CN201810985594.4A CN201810985594A CN109427907B CN 109427907 B CN109427907 B CN 109427907B CN 201810985594 A CN201810985594 A CN 201810985594A CN 109427907 B CN109427907 B CN 109427907B
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substrate
pattern
active
layer
semiconductor device
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CN109427907A (zh
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李商文
金正泽
金利桓
宋宇彬
申东石
李承烈
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本公开提供了半导体器件及其制造方法。该半导体器件包括：衬底；有源图案，与衬底间隔开并在第一方向上延伸；以及栅极结构，在有源图案上并在与第一方向交叉的第二方向上延伸，其中有源图案的下部在第一方向上延伸并包括相对于衬底的上表面倾斜的第一下表面。

Description

半导体器件及其制造方法
技术领域
实施方式涉及半导体器件及其制造方法。
背景技术
半导体器件可以包括由多个金属氧化物半导体场效应晶体管(MOSFET)构成的集成电路(IC)。
发明内容
实施方式可以通过提供一种半导体器件来实现，该半导体器件包括：衬底；有源图案，与衬底间隔开并在第一方向上延伸；以及栅极结构，在有源图案上并在与第一方向交叉的第二方向上延伸，其中有源图案的下部在第一方向上延伸并包括相对于衬底的上表面倾斜的第一下表面。
实施方式可以通过提供一种半导体器件来实现，该半导体器件包括：衬底；一对有源图案，与衬底间隔开；以及栅极结构，跨过所述一对有源图案延伸，其中所述一对有源图案中的每个有源图案的下部包括相对于衬底的上表面倾斜的下表面，所述一对有源图案中的每个有源图案的下部在与栅极结构的延伸方向交叉的方向上延伸。
实施方式可以通过提供一种制造半导体器件的方法来实现，该方法包括：在衬底上形成绝缘图案，使得绝缘图案包括暴露衬底的上表面的一部分的开口；使用衬底的上表面的被暴露部分作为籽晶顺序地生长牺牲半导体层和有源层；执行平坦化工艺以暴露牺牲半导体层的上表面并将有源层分成间隔开的有源图案而使牺牲半导体层在其间；去除牺牲半导体层；以及在有源图案上形成栅极结构。
附图说明
通过参照附图详细描述示范性实施方式，特征对于本领域技术人员将是明显的，附图中：
图1A示出根据示例实施方式的半导体器件的透视图。
图1B示出沿着图1A的线A-A'、B-B'和C-C'截取的截面图。
图2和图3示出根据示例实施方式的有源图案的透视图。
图4A、图5A、图6A、图7A、图8A、图9A、图10A和图11A示出根据示例实施方式的制造半导体器件的方法中的阶段的透视图。
图4B、图5B、图6B、图7B、图8B和图9B分别示出沿着图4A、图5A、图6A、图7A、图8A、图9A的线A-A'和D-D'截取的截面图。
图10B和图11B分别示出沿着图10A和图11A的线A-A'、B-B'和C-C'截取的截面图。
图12A和图13A示出根据示例实施方式的制造半导体器件的方法中的阶段的透视图。
图12B和图13B分别示出沿着图12A和图13A的线A-A'和D-D'截取的截面图。
图14示出根据示例实施方式的制造半导体器件的方法中的阶段的截面图。
图15A示出根据示例实施方式的半导体器件的透视图。
图15B示出沿着图15A的线A-A'、B-B'和C-C'截取的截面图。
图16A和图17A示出根据示例实施方式的制造半导体器件的方法中的阶段的透视图。
图16B和图17B分别示出沿着图16A和图17A的线A-A'、B-B'和C-C'截取的截面图。
具体实施方式
图1A示出根据示例实施方式的半导体器件的透视图。图1B示出沿着图1A的线A-A'、B-B'和C-C'截取的截面图。图2和图3示出根据示例实施方式的有源图案的透视图。
参照图1A和图1B，隔离图案110可以设置在衬底100上。衬底100可以是半导体衬底。例如，衬底100可以是硅衬底。衬底100的上表面100u可以是(100)面。隔离图案110可以在平行于衬底100的上表面100u的第一方向D1上延伸(例如纵向地)。隔离图案110可以包括例如氧化物、氮化物和/或氮氧化物。隔离图案110可以暴露衬底100。
衬底100可以包括从其上表面100u突出并在隔离图案110的面对的侧壁之间的突出部分PP。相对于衬底100的上表面100u，突出部分PP的上表面PS可以低于隔离图案110的上表面110u(例如比隔离图案110的上表面110u更靠近衬底100)。
突出部分PP可以在第一方向D1上延伸。在平面图中，突出部分PP可以在第一方向D1上在将在下面描述的一对有源图案AP之间延伸。突出部分PP可以具有相对于衬底100的上表面100u倾斜的上表面PS。突出部分PP的上表面PS可以在第一方向D1上延伸。突出部分PP可以具有V形截面。
第一层间绝缘层115和第二层间绝缘层117可以设置在衬底100上以覆盖隔离图案110。在一实施中，第一层间绝缘层115和第二层间绝缘层117可以包括相同的材料。例如，第一层间绝缘层115和第二层间绝缘层117可以每个包括硅氧化物层。在一实施中，第一层间绝缘层115和第二层间绝缘层117可以包括不同的材料。
有源图案AP可以设置在衬底100上。有源图案AP可以每个包括掩埋在(或延伸到)第一层间绝缘层115和第二层间绝缘层117中的下部以及突出在第一层间绝缘层115和第二层间绝缘层117上方(例如远离衬底100)的上部。多个有源图案AP可以设置在隔离图案110上，并可以在第二方向D2(与第一方向D1交叉且平行于衬底100的上表面100u)上彼此间隔开。在下文，将主要关于一对有源图案AP来描述。有源图案AP可以每个在第一方向D1上延伸。有源图案AP可以每个具有例如鳍形状或板形状。有源图案AP可以与隔离图案110的上表面110u间隔开。
有源图案AP可以每个具有下表面AF，下表面AF在第一方向D1上延伸并相对于衬底100的上表面100u倾斜或偏斜。参照图2和图3，每个有源图案AP的下表面AF可以包括第一下表面BS1。例如，第一下表面BS1可以在第一方向D1上延伸并相对于衬底100的上表面100u具有第一倾斜角。在一实施中，第一倾斜角可以为例如约45°至约65°。
第一下表面BS1可以是垂直于每个有源图案AP的优选取向的表面。例如，每个有源图案AP的优选取向可以是[111]取向。第一下表面BS1可以是(111)面。第一下表面BS1可以是密堆积表面。
在一实施中，如图3所示，每个有源图案AP的下表面AF还可以包括第二下表面BS2，第二下表面BS2连接到第一下表面BS1或与第一下表面BS1连续并具有小于第一倾斜角的第二倾斜角。在一实施中，第二下表面BS2可以基本上平行于衬底100的上表面100u。在一实施中，第二下表面BS2可以是(100)面。
每个有源图案AP可以具有相反的第一侧表面SS1和第二侧表面SS2。第一侧表面SS1和第二侧表面SS2可以每个是平行于第一方向D1的表面。第一侧表面SS1可以在垂直于衬底100的上表面100u的第三方向D3上具有第一长度(或高度，例如自衬底100)L1。第二表面SS2可以在第三方向D3上具有小于第一长度L1的第二长度(或高度)L2。在一实施中，第二长度L2可以比第一长度L1短约5％至20％。
有源图案AP可以每个包括由栅极结构GS覆盖的第一区域R1以及相对于衬底100的上表面100u具有比第一区域R1的上表面低的上表面的第二区域R2。第二区域R2的上表面可以是从第一区域R1的上表面凹陷的凹陷区域RS的底表面。
该对有源图案AP的第一侧表面SS1可以在第二方向D2上彼此面对。例如，该对有源图案AP的第一侧表面SS1可以在第二方向D2上在其第二侧表面SS2之间。
有源图案AP可以包括彼此相对的第一有源图案AP1和第二有源图案AP2。第一有源图案AP1可以具有面向第二方向D2的第一侧表面SS1和面向其相反方向的第二侧表面SS2。第二有源图案AP2可以具有面向第二方向D2的第二侧表面SS2和面向其相反方向的第一侧表面SS1。第一有源图案AP1和第二有源图案AP2可以关于相对于衬底100的上表面100u的垂直平面(例如关于与衬底100的上表面100u正交且与每个有源图案AP等距离的平面)镜像对称地布置。在一实施中，有源图案AP可以包括多个第一有源图案AP1和多个第二有源图案AP2。第一有源图案AP1和第二有源图案AP2可以在第二方向D2上交替地布置。在平面图中，突出部分PP可以设置在相应的第一有源图案AP1和相应的第二有源图案AP2之间。
有源图案AP可以包括与衬底100不同的材料。在一实施中，有源图案AP可以包括例如InGaAs、InAs、InSb和/或InGaSb。在一实施中，有源图案AP可以包括例如Si、Ge、SiGe、SiSn、GeSn、GeC、SnC和/或SiC。
栅极结构GS可以设置在有源图案AP上并在第二方向D2上延伸。栅极结构GS可以交叉有源图案AP。栅极结构GS可以包括栅电极GE和栅极绝缘图案GI。栅极绝缘图案GI可以插设在栅电极GE和有源图案AP之间，并在栅电极GE与第一层间绝缘层115和第二层间绝缘层117之间延伸。栅电极GE和栅极绝缘图案GI可以在第二方向D2上延伸。栅极间隔物125可以设置在栅极结构GS的两个相反的侧壁上。栅极绝缘图案GI可以在栅电极GE和栅极间隔物125之间延伸。栅极盖图案136可以设置在栅极结构GS上。栅极间隔物125和栅极盖图案136可以沿着栅电极GE在第二方向D2上延伸。
栅电极GE可以包括导电的金属氮化物(例如钛氮化物或钽氮化物)和/或金属(例如铝或钨)。栅极绝缘图案GI可以包括高k电介质材料。在一实施中，栅极绝缘图案GI可以包括例如铪氧化物、铪硅酸盐、锆氧化物和/或锆硅酸盐。栅极间隔物125可以包括氮化物，例如硅氮化物。栅极盖图案136可以包括例如硅氧化物。
源极/漏极区域SD可以设置在栅极结构GS的相反两侧。源极/漏极区域SD可以设置在有源图案AP的第二区域R2上。源极/漏极区域SD可以彼此横向地间隔开，使第一区域R1在其间。源极/漏极区域SD的下表面可以相对于衬底100的上表面100u低于第一区域R1的上表面。
源极/漏极区域SD可以每个包括使用相应的有源图案AP作为籽晶生长的外延层。源极/漏极区域SD可以包括例如硅锗(SiGe)、硅(Si)和/或硅碳化物(SiC)。在一实施中，当根据实施方式的半导体器件是互补金属氧化物半导体场效应晶体管(CMOSFET)时，可以形成第一外延层以形成n型MOSFET(NMOSFET)的源极/漏极区域SD，并且可以形成第二外延层以形成p型MOSFEF(PMOSFET)的源极/漏极区域SD。第一外延层可以将拉伸应变施加到NMOSFET的沟道区域(例如每个有源图案AP)。第二外延层可以将压缩应变施加到PMOSFET的沟道区域(例如每个有源图案AP)。在一实施中，第一外延层可以包括例如Si和/或SiC。在一实施中，第二外延层可以包括例如SiGe。
源极/漏极区域SD还可以包括杂质。在NMOSFET中，源极/漏极区域SD中的杂质可以是例如磷(P)。在PMOSFET中，源极/漏极区域SD中的杂质可以是例如硼(B)。
图4A、图5A、图6A、图7A、图8A、图9A、图10A和图11A示出根据示例实施方式的制造半导体器件的方法中的阶段的透视图。图4B、图5B、图6B、图7B、图8B和图9B分别示出沿着图4A、图5A、图6A、图7A、图8A、图9A的线A-A'和D-D'截取的截面图。图10B和图11B分别示出沿着图10A和图11A的线A-A'、B-B'和C-C'截取的截面图。
参照图4A和图4B，隔离图案110可以形成在衬底100上。隔离图案110可以通过蚀刻衬底100的上部以形成沟槽、然后形成绝缘层以填充沟槽以及平坦化该绝缘层而形成。隔离图案110可以包括例如氧化物、氮化物和/或氮氧化物。隔离图案110可以每个在第一方向D1上延伸并暴露衬底100的一部分。在一实施中，隔离图案110可以彼此间隔开。在一实施中，隔离图案110可以彼此连接。
衬底100的在隔离图案110之间的暴露部分可以被蚀刻以在隔离图案110之间形成开口OP。开口OP可以具有在第一方向D1上延伸的线性形状。开口OP可以通过例如湿蚀刻工艺形成。因此，突出部分PP可以形成在开口OP之下或在开口OP中。突出部分PP可以形成在隔离图案110之间并可以突出在隔离图案110的下表面之上。
突出部分PP可以覆盖隔离图案110的下部。相对于衬底100的上表面100u，突出部分PP的最上表面可以低于隔离图案110的最上表面。突出部分PP可以具有倾斜的上表面PS。突出部分PP可以具有V形的截面。突出部分PP的上表面PS与衬底100的上表面100u之间的倾斜角可以为例如约45°至约65°。
可以执行上述湿蚀刻工艺以具有基于衬底100的晶体学特性的取向。例如，可以执行湿蚀刻工艺以暴露衬底100的密堆积表面。在一实施中，突出部分PP的上表面PS可以是例如(111)面。在一实施中，突出部分PP可以通过外延生长形成。例如，突出部分PP可以通过从衬底100的上表面100u生长而形成。在这种情况下，突出部分PP的形状可以与图4A和图4B所示的形状不同。
参照图5A和图5B，牺牲半导体层SC可以通过使用突出部分PP作为籽晶生长来形成。牺牲半导体层SC可以通过外延生长工艺形成。外延生长工艺可以包括化学气相沉积(CVD)工艺或分子束外延(MBE)工艺。
牺牲半导体层SC可以包括与衬底100相同的材料。例如，牺牲半导体层SC可以是硅层。在一实施中，牺牲半导体层SC可以包括与衬底100不同的半导体材料。例如，牺牲半导体层SC可以是包括IV族元素(诸如SiGe或Ge)的半导体层。牺牲半导体层SC可以包括半导体化合物，例如III-V族半导体诸如GaAs或InP。
牺牲半导体层SC可以包括在开口OP中的第一部分SC1和在隔离图案110的上表面110u上方或之上的第二部分。第一部分SC1可以从突出部分PP的上表面PS在第三方向D3上生长以填充开口OP。牺牲半导体层SC的晶体缺陷可以不在隔离图案110的上表面110u之上扩展，而是可以被捕获在开口OP中。
在隔离图案110的上表面110u之上生长的第二部分SC2可以具有晶体取向。在一实施中，第二部分SC2的与隔离图案110的上表面110u相邻或接触的下侧表面SF可以在第一方向D1上延伸并相对于衬底100的上表面100u倾斜。第二部分SC2的下侧表面SF与衬底100的上表面100u之间的倾斜角可以为例如约45°至约65°。
第二部分SC2的下侧表面SF可以是垂直于牺牲半导体层SC的优选取向的表面。牺牲半导体层SC的优选取向可以是[111]取向。第二部分SC2的下侧表面SF可以是(111)面。第二部分SC2的下侧表面SF可以是密堆积表面。
第二部分SC2的上侧表面SU可以从其下侧表面SF延伸，并且是具有在第二方向D2上或在与其相反的方向上的法线的表面。第二部分SC2的上侧表面SU可以基本上垂直于隔离图案110的上表面110u。在一实施中，第二部分SC2的上侧表面SU可以是(110)面。
下侧表面SF的尺寸与上侧表面SU的尺寸的比率可以通过调整垂直外延生长速率(在第三方向D3上)和水平外延生长速率(在第一方向D1和/或第二方向D2上)来确定。例如，通过调节外延工艺条件(例如温度、压力和气流中的至少一个)，第二部分SC2的下侧表面SF可以以增大的垂直外延生长速率形成。在一实施中，第二部分SC2的下侧表面SF的尺寸与上侧表面SU的尺寸的比率可以随着工艺温度更高并且工艺压力更低而增大。
参照图6A和图6B，蚀刻停止层ES和有源层AL可以顺序地生长在牺牲半导体层SC上。蚀刻停止层ES可以包括对牺牲半导体层SC和/或有源层AL具有蚀刻选择性的材料。在一实施中，当牺牲半导体层SC是GaAs层时，蚀刻停止层ES可以是InGaP或InP层并且有源层AL可以是InGaAs层。在一实施中，当牺牲半导体层SC是GsAs层并且蚀刻停止层ES是InGaP或InP层时，有源层AL可以是InAs、InSb或InGaSb层。在一实施中，牺牲半导体层SC、蚀刻停止层ES和有源层AL可以是从Si、Ge、SiGe、SiSn、GeSn、GeC、SnC和SiC层中选择的不同层。
牺牲半导体层SC、蚀刻停止层ES和有源层AL可以在同一工艺室中连续地生长(即原位地)。蚀刻停止层ES和有源层AL可以沿着牺牲半导体层SC的上侧表面SU和上表面ST形成。蚀刻停止层ES和有源层AL可以覆盖牺牲半导体层SC的上侧表面SU和上表面ST，而不覆盖其下侧表面SF。蚀刻停止层ES的下表面EF和有源层AL的下表面AF可以与牺牲半导体层SC的下侧表面SF基本上平行或共平面。例如，蚀刻停止层ES的下表面EF和有源层AL的下表面AF的每个与每个隔离图案110的上表面110u之间的倾斜角可以为例如约45°至约65°。蚀刻停止层ES的下表面EF和有源层AL的下表面AF可以是(111)面。蚀刻停止层ES的下表面EF和有源层AL的下表面AF可以是密堆积表面。
参照图7A和图7B，在形成第一层间绝缘层115以覆盖有源层AL之后，可以执行平坦化工艺直到牺牲半导体层SC的上表面ST被暴露。平坦化工艺可以包括化学机械抛光工艺。第一层间绝缘层115可以包括例如硅氧化物、硅氮化物和/或硅氮氧化物。通过平坦化工艺，蚀刻停止层ES和有源层AL可以每个被分成一对间隔开的图案而使牺牲半导体层SC在其间。当有源层AL被分开时，可以形成有源图案AP。有源图案AP可以每个具有鳍形状或板形状。
参照图8A和图8B，牺牲半导体层SC和蚀刻停止层ES可以被顺序地去除。可以使用不同的蚀刻配方去除牺牲半导体层SC和蚀刻停止层ES。在一实施中，当牺牲半导体层SC是GaAs层时，牺牲半导体层SC可以使用包括硫酸和/或柠檬酸的蚀刻剂来蚀刻。在一实施中，当蚀刻停止层ES是InGaP层时，蚀刻停止层ES可以使用包括盐酸的蚀刻剂来蚀刻。在一实施中，有源图案AP的一部分可以在去除牺牲半导体层SC和蚀刻停止层ES期间被蚀刻。
通过去除牺牲半导体层SC和蚀刻停止层ES，可以在有源图案AP之间形成沟槽TC。沟槽TC可以暴露衬底100，例如突出部分PP。
参照图9A和图9B，第二层间绝缘层117可以形成在沟槽TC中。在一实施中，第二层间绝缘层117可以包括例如与第一层间绝缘层115相同的材料。在一实施中，第二层间绝缘层117可以包括例如硅氧化物、硅氮化物和/或硅氮氧化物。第二层间绝缘层117可以通过CVD工艺形成。
第一层间绝缘层115的上部和第二层间绝缘层117的上部可以被去除以暴露有源图案AP的上部。例如，第一层间绝缘层115的上部和第二层间绝缘层117的上部可以使用包括磷酸的蚀刻剂选择性地去除。有源图案AP的下部可以掩埋在第一层间绝缘层115和第二层间绝缘层117中。第一层间绝缘层115和第二层间绝缘层117可以支撑有源图案AP而不倒塌。例如，每个有源图案AP的掩埋在第一层间绝缘层115和第二层间绝缘层117中的下部在第三方向D3上的长度(或高度)可以是每个有源图案AP在第三方向上的长度(或高度)的约20％至50％。
参照图10A和图10B，牺牲栅极结构SGS可以形成在有源图案AP上。牺牲栅极结构SGS可以跨过有源图案AP在第二方向D2上延伸。牺牲栅极结构SGS可以包括牺牲栅极图案123、蚀刻停止图案121、栅极间隔物125和牺牲盖图案127。
牺牲栅极图案123可以在第二方向D2上延伸。牺牲栅极图案123可以覆盖有源图案AP的上表面和侧表面并延伸到第一层间绝缘层115的上表面和第二层间绝缘层117的上表面上。蚀刻停止图案121可以沿着牺牲栅极图案123的下表面延伸。蚀刻停止图案121可以在有源图案AP和牺牲栅极图案123之间以及在牺牲栅极图案123与第一层间绝缘层115和第二层间绝缘层117之间延伸。
牺牲栅极图案123和蚀刻停止图案121可以通过在第一层间绝缘层115和第二层间绝缘层117上顺序地形成蚀刻停止层和牺牲栅极层以覆盖有源图案AP以及顺序地图案化牺牲栅极层和蚀刻停止层来形成。蚀刻停止层可以包括例如硅氧化物。牺牲栅极层可以包括对蚀刻停止层具有蚀刻选择性的材料，例如多晶硅。
牺牲栅极层可以通过使用对蚀刻停止层具有蚀刻选择性的蚀刻条件的蚀刻工艺来图案化以形成牺牲栅极图案123。在形成牺牲栅极图案123之后，在牺牲栅极图案123的相反两侧处的蚀刻停止层可以被去除以在牺牲栅极图案123下面形成蚀刻停止图案121。牺牲盖图案127可以用作用于形成牺牲栅极图案123的掩模图案。牺牲盖图案127可以包括例如硅氧化物。
栅极间隔物125可以形成在牺牲栅极图案123的两个相反的侧壁上。栅极间隔物125可以通过形成绝缘层以覆盖牺牲栅极图案123以及对该绝缘层执行各向异性蚀刻工艺来形成。栅极间隔物125可以包括例如硅氮化物和/或硅氮氧化物。
参照图11A和图11B，源极/漏极区域SD可以形成在牺牲栅极结构SGS的相反两侧。源极/漏极区域SD的形成可以包括去除有源图案AP的由牺牲栅极结构SGS暴露的上部以形成凹陷区域RS。可以使用由凹陷区域RS暴露的有源图案AP的上表面作为籽晶来执行选择性外延生长工艺，以生长用作源极/漏极区域SD的外延层。源极/漏极区域SD可以每个包括例如Si、SiGe和/或SiC。源极/漏极区域SD可以由具有比有源图案AP大或小的晶格常数的材料形成，以将压缩应变或拉伸应变施加到有源图案AP。在一实施中，源极/漏极区域SD可以具有例如如图11B所示的五边形截面。
源极/漏极区域SD的形成还可以包括在选择性外延生长工艺期间或之后将杂质掺杂到源极/漏极区域SD中。杂质可以提高包括源极/漏极区域SD的晶体管的电特性。当晶体管是NMOSFET时，杂质可以是例如磷。当晶体管是PMOSFET时，杂质可以是例如硼。
再次参照图1A和图1B，在去除牺牲盖图案127、牺牲栅极图案123和蚀刻停止图案121以在栅极间隔物125之间形成间隙区域之后，栅极绝缘图案GI、栅电极GE和栅极盖图案136可以形成在该间隙区域中。该间隙区域可以通过在衬底100上形成第三层间绝缘层、对第三层间绝缘层执行平坦化工艺以暴露牺牲盖图案127、以及顺序地去除栅极间隔物125之间的牺牲盖图案127、牺牲栅极图案123和蚀刻停止图案121来形成。
在间隙区域中顺序地形成栅极绝缘层和栅电极层之后，可以对栅极绝缘层和栅电极层执行回蚀刻工艺以形成栅极绝缘图案GI和栅电极GE。栅极绝缘图案GI可以包括高k电介质材料。在一实施中，栅极绝缘图案GI可以包括例如铪氧化物、铪硅酸盐、锆氧化物和/或锆硅酸盐。栅极绝缘层可以通过例如原子层沉积工艺形成。
栅电极GE可以包括导电的金属氮化物(例如钛氮化物或钽氮化物)和/或金属(例如铝或钨)。
栅极盖图案136可以形成在栅极绝缘图案GI和栅电极GE上以填充栅极间隔物125之间的间隙区域。栅极盖图案136可以包括例如硅氧化物、硅氮化物和/或硅氮氧化物。
当使用蚀刻工艺形成用作用于形成有源图案的模子的牺牲半导体层时，牺牲半导体层的被蚀刻表面的界面特性可以根据蚀刻工艺的特性来确定。从被蚀刻表面生长的有源图案的晶体学特性可能变差或不均匀。
根据示例实施方式，牺牲半导体层SC、蚀刻停止层ES和有源层AL可以原位地连续形成。因此，形成有源图案AP的有源层AL可以形成在牺牲半导体层SC的侧表面(其不是被蚀刻表面)上，从而可以提高有源图案AP的晶体学特性和电特性。牺牲半导体层SC、蚀刻停止层ES和有源层AL可以连续地形成而不用至少一个居间的非半导体层的沉积或蚀刻工艺，制造工艺可以被简化。另外，有源图案AP可以利用牺牲半导体层SC形成，并且每个有源图案AP的形状和厚度可以被调节。
图12A和图13A示出根据示例实施方式的制造半导体器件的方法中的阶段的透视图。图12B和图13B分别示出沿着图12A和图13A的线A-A'和D-D'截取的截面图。
参照图12A和图12B，牺牲半导体层SC和有源层AL可以形成在图5A和图5B的所得结构上。在本实施方式中，可以省略图6A和图6B所示的蚀刻停止层ES。牺牲半导体层SC和有源层AL可以每个由相对于彼此具有蚀刻选择性的材料形成。在一实施中，牺牲半导体层SC是InP层，并且有源层AL可以是InGaAs层。在一实施中，牺牲半导体层SC和有源层AL可以是从Si、Ge、SiGe、SiSn、GeSn、GeC、SnC和SiC层中选择的不同层。
参照图13A和图13B，在形成第一层间绝缘层115以覆盖有源层AL之后，可以执行平坦化工艺直到牺牲半导体层SC的上表面被暴露。因此，有源层AL可以被分成一对间隔开的有源图案AP而使牺牲半导体图案SC在其间。可以执行参照图8A至图11A和图8B至图11B描述的工艺。
图14示出根据示例实施方式的制造半导体器件的方法中的阶段的截面图。图14示出沿着图1的线A-A'和D-D'截取的截面图。
参照图14，可以在衬底100上形成下绝缘图案111。下绝缘图案111可以通过形成覆盖衬底100的下绝缘层以及图案化该下绝缘层以形成暴露衬底100的上表面FS的开口OP来形成。衬底100的被暴露的上表面FS可以是基本上平坦的。牺牲半导体层SC可以使用衬底100的上表面FS作为籽晶来形成。在一实施中，下绝缘图案111可以是绝缘体上硅(SOI)衬底的一部分。此后，可以执行与参照图6A至图11A和图6B至图11B描述的相同的工艺。
图15A示出根据示例实施方式的半导体器件的透视图。图15B示出沿着图15A的线A-A'、B-B'和C-C'截取的截面图。
参照图15A和图15B，栅极绝缘图案GI和栅电极GE可以在有源图案AP下面延伸。栅极绝缘图案GI和栅电极GE可以顺序地覆盖有源图案AP的下表面AF。栅极绝缘图案GI和栅电极GE中的每个的下部的形状可以根据随后描述的制造工艺而变化。在一实施中，栅极绝缘图案GI和栅电极GE可以延伸到开口OP中。在一实施中，第一层间绝缘层115和第二层间绝缘层117的一部分可以保留在隔离图案110上，并且栅极绝缘图案GI和栅电极GE可以延伸到第一层间绝缘层115和第二层间绝缘层117中，在有源图案AP的下表面AF下面。
图16A和图17A示出根据示例实施方式的制造半导体器件的方法中的阶段的透视图。图16B和图17B分别示出沿着图16A和图17A的线A-A'、B-B'和C-C'截取的截面图。
参照图16A和图16B，在图11A和图11B的所得结构中，牺牲盖图案127、牺牲栅极图案123和蚀刻停止图案121可以被顺序地去除以形成间隙区域GR。间隙区域GR的形成可以包括：在衬底100上形成第三层间绝缘层119、平坦化第三层间绝缘层119以暴露牺牲盖图案127、以及顺序地去除牺牲盖图案127、牺牲栅极图案123和蚀刻停止图案121。
参照图17A和图17B，可以形成包括间隙区域GR和在隔离图案110与有源图案AP之间延伸的空间的延伸间隙区域GRE。延伸间隙区域GRE可以通过去除第一和第二层间绝缘层115和117的在栅极间隔物125之间由间隙区域GR暴露的部分来形成。延伸间隙区域GRE可以通过例如选择性蚀刻工艺形成。有源图案AP的下表面AF可以通过延伸间隙区域GRE暴露。
在一实施中，隔离图案110可以与第一层间绝缘层115和第二层间绝缘层117一起被至少部分地去除。在一实施中，第一层间绝缘层115和第二层间绝缘层117的一部分可以保留在有源图案AF下面。
再次参照图15A和图15B，栅极绝缘图案GI、栅电极GE和栅极盖图案136可以形成在延伸间隙区域GRE中。栅极绝缘图案GI和栅电极GE可以填充有源图案AP的下表面AF与隔离图案110之间的空间。此后，栅极盖图案136可以形成在栅极绝缘图案GI和栅电极GE上以填充栅极间隔物125之间的空间。
通过总结和回顾，为了提高这样的器件的集成密度，会希望减小半导体器件的尺寸和设计规则。这会需要按比例缩小MOS晶体管。MOS晶体管的按比例缩小会导致半导体器件的操作特性的劣化。因此，旨在制造提供更好性能的高度集成的半导体器件的各种技术被考虑。
在此背景下，实施方式可以提供包括场效应晶体管的半导体器件。
这里已经公开了示例实施方式，并且尽管特定的术语被使用，但是它们仅以一般性和描述性的含义来使用和解释，而不是为了限制的目的。在一些情况下，如直至本申请提交时为止对于本领域普通技术人员将是显然的，结合特定实施方式描述的特征、特性和/或元件可以单独地使用，或与结合其它实施方式描述的特征、特性和/或元件组合地使用，除非另外地明确指示。因此，本领域技术人员将理解，可以进行形式和细节上的各种改变，而没有脱离本发明的在权利要求书中阐述的精神和范围。
于2017年8月30日在韩国知识产权局提交且名称为“半导体器件及其制造方法”的韩国专利申请第10-2017-0110353号通过引用整体地结合于此。

Claims (25)

1.一种半导体器件，包括：
衬底；
有源图案，与所述衬底间隔开并在第一方向上延伸；
栅极结构，在所述有源图案上并在与所述第一方向交叉的第二方向上延伸；以及
隔离图案，形成在所述衬底的上表面上，其中所述有源图案在所述隔离图案上方且与所述隔离图案间隔开，
其中所述有源图案的下部在所述第一方向上延伸并包括相对于所述衬底的上表面倾斜的第一下表面。
2.根据权利要求1所述的半导体器件，其中所述第一下表面垂直于所述有源图案的[111]取向。
3.根据权利要求1所述的半导体器件，其中所述第一下表面是(111)面。
4.根据权利要求1所述的半导体器件，其中所述衬底的所述上表面是(100)面。
5.根据权利要求1所述的半导体器件，其中所述有源图案的所述下部还包括在所述第一方向上延伸的第二下表面，所述第二下表面平行于所述衬底的所述上表面。
6.根据权利要求1所述的半导体器件，其中所述有源图案包括：
第一侧表面，在垂直于所述衬底的所述上表面的第三方向上具有第一高度；和
第二侧表面，与所述第一侧表面相反并在所述第三方向上具有第二高度，所述第二高度小于所述第一高度。
7.根据权利要求1所述的半导体器件，其中所述有源图案具有鳍形状或板形状。
8.根据权利要求1所述的半导体器件，还包括在所述衬底上的层间绝缘层，其中所述有源图案的所述下部掩埋在所述层间绝缘层中。
9.根据权利要求8所述的半导体器件，其中所述隔离图案在所述衬底和所述层间绝缘层之间。
10.根据权利要求1所述的半导体器件，其中所述有源图案包括与所述衬底的材料不同的材料。
11.一种半导体器件，包括：
衬底；
一对有源图案，与所述衬底间隔开；
栅极结构，延伸跨过所述一对有源图案，以及
隔离图案，形成在所述衬底的上表面上，其中所述一对有源图案在所述隔离图案上方且与所述隔离图案间隔开，
其中所述一对有源图案中的每个有源图案的下部包括相对于所述衬底的上表面倾斜的下表面，所述一对有源图案中的每个有源图案的所述下部在与所述栅极结构的延伸方向交叉的方向上延伸。
12.根据权利要求11所述的半导体器件，其中所述一对有源图案关于与所述衬底的所述上表面正交且与每个所述有源图案等距离的平面镜像对称。
13.根据权利要求11所述的半导体器件，其中所述一对有源图案中的每个有源图案包括：
第一侧表面，在相对于所述衬底的所述上表面的垂直方向上具有第一长度；和
第二侧表面，与所述第一侧表面相反并在所述垂直方向上具有第二长度，所述第二长度小于所述第一长度。
14.根据权利要求13所述的半导体器件，其中所述一对有源图案中的一个有源图案的所述第一侧表面面对所述一对有源图案中的另一个有源图案的所述第一侧表面。
15.根据权利要求11所述的半导体器件，还包括在所述衬底上的层间绝缘层，其中所述一对有源图案中的每个有源图案的所述下部掩埋在所述层间绝缘层中。
16.根据权利要求15所述的半导体器件，其中所述隔离图案在所述衬底和所述层间绝缘层之间并且彼此间隔开，其中每个所述隔离图案位于所述一对有源图案中的对应一个下面。
17.根据权利要求16所述的半导体器件，其中：
所述衬底包括在所述隔离图案之间突出的突出部分，并且
在平面图中，所述突出部分在所述一对有源图案之间且平行于所述一对有源图案延伸。
18.根据权利要求11所述的半导体器件，其中：
所述栅极结构包括栅极绝缘图案和栅电极，并且
所述栅极绝缘图案和所述栅电极在所述衬底与所述一对有源图案之间延伸。
19.根据权利要求11所述的半导体器件，其中：
所述衬底的所述上表面是(100)面，并且
所述一对有源图案中的每个有源图案的所述下表面是(111)面。
20.一种制造半导体器件的方法，该方法包括：
在衬底上形成绝缘图案，使得所述绝缘图案包括暴露所述衬底的上表面的一部分的开口；
在开口中形成突出部分，所述突出部分具有相对于所述衬底的上表面倾斜的上表面；使用所述衬底的所述上表面的被暴露部分和所述突出部分的所述倾斜的上表面作为籽晶顺序地生长牺牲半导体层和有源层；
执行平坦化工艺以暴露所述牺牲半导体层的上表面并将所述有源层分成间隔开的有源图案而使所述牺牲半导体层在其间；
去除所述牺牲半导体层；以及
在所述有源图案上形成栅极结构。
21.根据权利要求20所述的方法，其中所述牺牲半导体层包括在所述绝缘图案上的倾斜表面，所述倾斜表面相对于所述衬底的所述上表面倾斜。
22.根据权利要求21所述的方法，其中所述牺牲半导体层的所述倾斜表面是(111)面。
23.根据权利要求21所述的方法，其中所述有源层的下表面平行于所述牺牲半导体层的所述倾斜表面。
24.根据权利要求20所述的方法，其中所述有源层沿着所述牺牲半导体层的所述上表面和侧表面生长。
25.根据权利要求20所述的方法，还包括：在生长所述有源层之前，在所述牺牲半导体层上生长蚀刻停止层。
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