CN109427906B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109427906B
CN109427906B CN201810952249.0A CN201810952249A CN109427906B CN 109427906 B CN109427906 B CN 109427906B CN 201810952249 A CN201810952249 A CN 201810952249A CN 109427906 B CN109427906 B CN 109427906B
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CN109427906A (zh
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高谷秀史
浦上泰
副岛成雅
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Toyota Motor Corp
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Abstract

本发明提供一种半导体装置，具备半导体基板、上表面电极、下表面电极及经由栅极绝缘膜而设于沟槽内的栅电极。半导体基板具有与上表面电极接触的P型体层、介于体层与下表面电极之间的n型漂移层、沿着沟槽的底面设置的p型浮置区及沿着沟槽的侧面在体层与浮置区之间延伸的p型连接区。沟槽沿着俯视时的长边方向具有未设置连接区的第一区间及设置有连接区的第二区间。而且，第二区间中的沟槽的侧面的倾倒角度比第一区间中的沟槽的侧面的倾倒角度大。

Description

半导体装置
技术领域
本说明书中公开的技术涉及一种半导体装置，特别涉及一种沟槽栅极型半导体装置。在此所谓的沟槽栅极型半导体装置是指在半导体基板设置的沟槽内具有与半导体基板绝缘的栅电极的半导体装置。沟槽栅极型半导体装置包含例如MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor：金属氧化物半导体场效应晶体管)和IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极晶体管)。
背景技术
日本特开2007-242852号公报公开了一种沟槽栅极型MOSFET。该MOSFET具备在上表面具有沟槽的半导体基板、设置于半导体基板的上表面的上表面电极、设置于半导体基板的下表面的下表面电极及经由栅极绝缘膜而设置于沟槽内的栅电极。半导体基板具有与上表面电极接触的p型体层、介于体层与下表面电极之间的n型漂移层、位于漂移层内并沿着沟槽的底面设置的p型浮置区及沿着沟槽的侧面在体层与浮置区之间延伸的p型连接区。
在上述MOSFET中，沿着沟槽的底面形成浮置区，并沿着沟槽的侧面形成对浮置区和体层之间进行连接的连接区。根据这种结构，在MOSFET被断开时，电场强度在沟槽的底面附近缓和，所以提高了MOSFET的耐压性。而且，在MOSFET被导通时，通过连接区迅速地将空穴从体层导入至浮置区，从而浮置区的充电被抑制。
另一方面，沿着沟槽的侧面形成连接区比较困难。为了沿着沟槽的侧面形成连接区，需要通过沟槽的开口，向沟槽的侧面进行p型杂质的离子注入。在此，由于沟槽的开口宽度比较狭窄，所以针对沟槽的侧面(特别是，沟槽的除了长边方向的两端部分之外的侧面)的离子注入必然只能以浅入射角实施。在浅入射角的离子注入中，离子难以被注入到半导体基板中，所以例如必须增加施加到离子的加速能量。然而，如果增加施加到离子的加速能量，则出现例如半导体基板内的结晶缺陷增多的问题。以这种方式沿着沟槽的侧面形成连接区比较困难。
发明内容
在本说明书中，提供一种在沟槽栅极型半导体装置中能够沿着沟槽的侧面容易地形成连接区的技术。
本说明书公开的技术在半导体装置中被实现。该半导体装置具备：在上表面具有沟槽的半导体基板；设置于半导体基板的上表面的上表面电极；设置于半导体基板的位于上表面的相反侧的下表面的下表面电极；及经由栅极绝缘膜而设置于沟槽内的栅电极。半导体基板具有：与上表面电极接触的P型体层；介于体层与下表面电极之间的n型漂移层；设置于漂移层内并在沟槽的底面露出的p型浮置区；及沿着沟槽的侧面在体层与浮置区之间延伸的p型连接区。沟槽沿着俯视时的长边方向具有未设置连接区的第一区间及设置有连接区的第二区间。而且，第二区间中的沟槽的侧面的倾倒角度比第一区间中的沟槽的侧面的倾倒角度大。
在此，沟槽侧面的倾倒角度是指沟槽侧面相对于沟槽的深度方向所成的角度。特别是，以沟槽侧面与深度方向平行时为基准(即倾倒角度为0)，沟槽侧面朝向半导体基板的上表面侧越倾斜，则倾倒角度越大。
在上述半导体装置中，在沟槽的长边方向的一部分区间(即第二区间)中，沟槽侧面的倾倒角度变大，在该倾倒角度大的侧面形成连接区。根据这种结构，在通过p型杂质的离子注入来形成连接区时，能够使离子以比较深的入射角向沟槽侧面入射。因而，例如能够降低施加到离子的加速能量，由此，例如能够抑制半导体基板内生成的结晶缺陷。另一方面，沟槽的长边方向的其他区间(即第一区间)是沿着沟槽侧面形成沟道的区间，但在该区间，侧面的倾倒角度比较小。如此若在形成沟道的区间中沟槽侧面被陡峭地形成，则能够提高通过沟道的载流子的移动性。
附图说明
图1是实施例1的MOSFET10的俯视图。
图2是图1中的II-II线的剖视图，表示沟槽14的第一区间S1中的MOSFET10的截面结构。
图3是图1中的III-III线的剖视图，表示沟槽14的第二区间S2中的MOSFET10的截面结构。
图4示意性表示沟槽14的开口形状(即，俯视观察下的沟槽)。
图5是示意性表示沟槽14的形状的立体图。
图6是图4中的VI-VI线的剖视图，表示沟槽14在第一区间S1中的截面形状。
图7是图4中的VII-VII线的剖视图，表示沟槽14在第二区间S2中的截面形状。
图8是图4中的VIII-VIII线的剖视图，表示沟槽14在第三区间S3中的截面形状。
图9是说明形成沟槽14的工序的一例的第一步骤的图。
图10是图9中的Ⅹ-Ⅹ线的剖视图，表示第一步骤后的沟槽14的第二区间S2的截面形状。
图11是说明形成沟槽14的工序的一例的第二步骤的图。
图12是图11中的XII-XII线的剖视图，表示第二步骤后的沟槽14的第二区间S2的截面形状。
图13表示实施例2的IGBT110的截面结构，特别表示沟槽14的第一区间S1中的IGBT110的截面结构。
图14表示实施例2的IGBT110的截面结构，特别表示沟槽14的第二区间S2中的IGBT110的截面结构。
具体实施方式
在本发明的一实施方式中，第二区间中的沟槽的开口宽度可以比第一区间中的沟槽的开口宽度大。沟槽在第二区间的开口宽度越大，则在通过P型杂质的离子注入来形成连接区时，越能够使离子更深地入射到沟槽的侧面。因而，能够例如进一步降低施加到离子的加速能量，进一步抑制半导体基板中的结晶缺陷的生成。
在本发明的一实施方式中，沟槽还可以具有在长边方向上位于第一区间与第二区间之间且未设置连接区的第三区间。在此情况下，第三区间中的沟槽的开口宽度可以比第一区间的沟槽的开口宽度大，同时第三区间中的沟槽侧面的倾倒角度可以比第二区间中的沟槽侧面的倾倒角度小。根据这种结构，由于形成沟道的沟槽的侧面扩大，所以能够降低对于半导体装置的通电的电阻(所谓的导通电阻)。
上述第三区间中的开口宽度可以与第二区间中的开口宽度相等，且第三区间中的侧面的倾倒角度也可以与第一区间中的侧面的倾倒角度相等。根据这种结构，能够避免沟槽的形状变得过于复杂，并且能够充分扩大形成沟道的沟槽的侧面。
在本发明的一实施方式中，半导体装置可以是MOSFET。在此情况下，半导体基板可以具有：n型源极区，与上表面电极接触且经由栅极绝缘膜而与栅电极相对，并经由体层而与漂移层隔开；及n型漏极层，与下表面电极接触并经由漂移层而与体层隔开。
在本发明的一实施方式中，半导体装置可以是IGBT。在此情况下，半导体基板可以具有：n型发射极区，与上表面电极接触且经由栅极绝缘膜而与上述栅电极相对，并经由体层而与漂移层隔开；及p型集电极层，与下表面电极接触并经由漂移层而与所述体层隔开。而且，虽然未特别限定，但半导体基板还可以具有位于漂移层和集电极层之间的n型缓冲层。
以下，参照附图对本发明代表性且非限定的实施例进行详细说明。该详细说明单纯意图对本领域技术人员显示用于实施本发明的优选实施例的详细情况，并不限定本发明的范围。而且还应理解，以下公开的附加特征和发明可以单独使用或与其他特征和发明一起使用，以提供进一步改进后的半导体装置及其使用方法和制造方法。
另外，在以下的详细说明中公开的特征、步骤的组合在最广泛意义上实现本发明时不是必不可少的，仅特别为了说明本发明的代表性示例而记载。另外，在本说明书上文和下文所述的代表性具体例的各种特征、以及独立权利要求和从属权利要求中描述的各种特征在提供本发明的附加且有用的实施方式时不必根据在此记载的具体例或按所列顺序进行组合。
除了实施例和/或权利要求中记载的特征的结构之外，本说明书和/或权利要求中记载的所有特征作为对本申请的初始公开内容以及所要求保护的特定事项的限制，旨在单独地并且彼此独立地公开。另外，所有与数值范围和组或集合相关的记载作为对本申请的初始公开内容和所要求保护的特定事项的限制，旨在公开其中间结构。
【实施例】
(实施例1)参照附图，对实施例1的MOSFET10进行说明。本实施例的MOSFET10并未被特别限定，但属于功率半导体装置，例如在电动型的汽车中可以用作转换器、变换器的开关元件。在此所谓的电动型的汽车包含例如混合动力车辆、燃料电池车辆或电动汽车这样的、利用电动机驱动车轮的各种车辆。
如图1、图2和图3所示，MOSFET10具备半导体基板12、设置于半导体基板12的上表面12a的上表面电极16、设置于半导体基板12的下表面12b的下表面电极18及多个栅电极20。在半导体基板12的上表面12a设置有多个沟槽14，经由栅极绝缘膜22将栅电极20设置在各个沟槽14内。
在此，半导体基板12的上表面12a是指半导体基板12的一个表面，半导体基板12的下表面12b是指半导体基板12的另一个表面，是位于上表面12a的相反侧的表面。在本说明书中，所谓“上表面”和“下表面”用于方便地区分彼此位于相反侧的两个表面，对MOSFET10的制造时、使用时的姿势没有限定。
本实施例的半导体基板12是由碳化硅(SiC)构成的SiC基板。但是，半导体基板12并不局限于SiC基板，也可以是硅(Si)基板或由其他半导体材料构成的基板(晶体)。上表面电极16和下表面电极18由具有导电性的材料构成。该材料没有特别被限定，但可以采用诸如Al(铝)、Ni(镍)、Ti(钛)、Au(金)这样的金属材料。对上表面电极16和下表面电极18的具体结构没有特别限定。上表面电极16与半导体基板12的上表面12a欧姆接触，下表面电极18与半导体基板12的下表面12b欧姆接触。
栅电极20由具有导电性的材料构成，例如，该材料可以采用多晶硅。栅极绝缘膜22位于栅电极20和沟槽14的内表面14a、14b之间。栅电极20与半导体基板12电绝缘。栅极绝缘膜22可以由诸如氧化硅这样的绝缘材料形成。而且，在栅电极20和上表面电极16之间设置层间绝缘膜24，栅电极20也与上表面电极16电绝缘。层间绝缘膜24例如由诸如氧化硅这样的绝缘材料形成。
如图2、图3所示，半导体基板12具备漏极层32、漂移层34、体层36和源极区38。漏极层32是掺杂有n型杂质(例如磷)的n型半导体区。漏极层32沿着半导体基板12的下表面12b设置，并与下表面电极18接触。漏极层32中的n型杂质的浓度足够高，下表面电极18与漏极层32欧姆接触。而且，漏极层32的厚度、其n型杂质的浓度未被特别限定，可以适当地设计。
漂移层34是掺杂有n型杂质的n型半导体区。漂移层34层叠于漏极层32上，并在整个半导体基板12上扩展。漂移层34中的n型杂质的浓度比漏极层32中的n型杂质的浓度低。而且，漂移层34的厚度、n型杂质的具体浓度未被特别限定，可以适当地设计。
体层36是掺杂有p型杂质(例如Al)的p型半导体区。体层36层叠于漂移层34上并在整个半导体基板12上扩展。体层36在半导体基板12的上表面12a与上表面电极16接触。在此，在体层36中的与上表面电极16接触的部分36a(有时被称作接触区或体接触区)中，p型杂质的浓度高，由此，上表面电极16与体层36欧姆接触。而且，体层36的厚度、p型杂质的具体浓度未被特别限定，可以适当地设计。
源极区38是掺杂有n型杂质的n型半导体区。源极区38沿着半导体基板12的上表面12a设置，并与上表面电极16接触。虽然仅是一个示例，但在本实施例中，多个源极区38被形成为条状，各个源极区38沿与沟槽14的长边方向垂直的方向延伸。因此，在半导体基板12的上表面12a，沿着沟槽14的长边方向，体层36和源极区38交替地露出，体层36和源极区38均与上表面电极16接触。而且，源极区38也在沟槽14的侧面14a露出，并经由栅极绝缘膜22而与栅电极20相对。在半导体基板12内，源极区38被体层36包围，源极区38经由体层36而与漂移层34隔离。源极区38中的n型杂质的浓度足够高，上表面电极16与源极区38欧姆接触。而且，源极区38的形状、n型杂质的具体浓度未被特别限定，可以适当地设计。
半导体基板12还具备浮置区40和连接区42。浮置区40是掺杂有p型杂质的p型半导体区。浮置区40位于漂移层34内，并沿着沟槽14的底面14b设置。浮置区40与下文所述的连接区42一起被设置，用于抑制沟槽14的底面14b附近的电场强度。而且，浮置区40的形状、n型杂质的具体浓度未被特别限定，可以适当地设计。
连接区42是掺杂有p型杂质的p型半导体区。连接区42沿着沟槽14的侧面14a在体层36和浮置区40之间延伸。因而，浮置区40经由连接区42和体层36而与上表面电极16电连接。在此，如根据图2和图3理解的那样，连接区42仅设置于沟槽14的长边方向上的一部分区间。如图2所示，在其他区间未设置连接区42，栅电极20经由栅极绝缘膜22而与漂移层34相对。因而，在未设置连接区42的区间，当MOSFET10被导通时，形成载流子从源极区38向漂移层34流动的沟道。
接下来，参照图4～图8对沟槽14的结构进行说明。沿着俯视时的长边方向(图1和图4中的上下方向)，本实施例的沟槽14具有第一区S1、第二区间S2和第三区间S3。而且，第三区间S3是并非不可缺少的区间，沟槽14只要至少具有第一区S1和第二区间S2即可。而且，虽然在本实施例中设置多个第二区间S2，但沟槽14只要在离开其长边方向的两端12c(参照图1)的位置具有至少一个第二区间S2即可。
如上所述，连接区42仅设置于沟槽14的长边方向的一部分区间，第二区间S2是设置该连接区42的区间。与此相对，第一区间S1是未设置连接区42的区间。即，在第二区间S2，沿着沟槽14的侧面14a形成连接区42(参照图3)，但在第一区间S1未形成连接区42，漂移层34在沟槽14的侧面14a露出(参照图2)。
如图6和图7所示，对第一区间S1和第二区间S2进行比较，首先，沟槽14的侧面14a的倾倒角度C1、C2在两个区间S1、S2之间彼此不同。具体而言，第二区间S2的倾倒角度C2比第一区间S1的倾倒角度C1大。在此，沟槽14的侧面14a的倾倒角度是指沟槽14的侧面14a相对于沟槽14的深度方向D形成的角度。特别是，以沟槽14的侧面14a与深度方向D平行时为基准(即倾倒角度为0)，沟槽14的侧面14a朝向半导体基板12的上表面12a侧越倾斜，则倾倒角度越大。
在本实施例的MOSFET10中，在沟槽14的长边方向的一部分区间(即第二区间S2)中，沟槽14的侧面14a的倾倒角度C2变大，沿着该缓慢倾斜的侧面14a形成连接区42。根据这种结构，在通过p型杂质的离子注入来形成连接区42时，能够使离子以比较深的入射角(即比较小的入射角)向沟槽14的侧面14a入射。由此，例如能够降低施加到离子的加速能量，从而能够抑制在半导体基板12内生成的结晶缺陷。
另一方面，沟槽14的长边方向的其他区间(例如第一区间S1)是沿着沟槽14的侧面14a形成沟道的区间，但在该区间，侧面14a的倾倒角度C1比较小。虽然是个示例，但在第一区间S1中，沟槽14的侧面14a可以与沟槽14的深度方向D大致平行。即，第一区间S1的倾倒角度C1可以大致为0。从而，如果在形成有沟道的区间内沟槽14的侧面14a被形成得陡峭，则能够提高通过沟道的载流子的移动性。因而，例如能够降低或维持MOSFET10的导通电阻。另外，形成有连接区42的第二区间S2是原本未形成沟道的区间，因此在该区间即使增大沟槽14的侧面14a的倾倒角度C2，MOSFET10的导通电阻也不受影响。
在本实施例的MOSFET10中，如图6和图7所示，第二区间S2中的沟槽14的开口宽度W2比第一区间S1中的沟槽14的开口宽度W1大(即，W1＜W2)。沟槽14在第二区间S2中的开口宽度W2越大，则在通过p型杂质的离子注入来形成连接区42时，越能够使离子以比较深的入射角向沟槽14的侧面14a入射。由此，例如能够降低施加到离子的加速能量，进一步抑制在半导体基板12内的结晶缺陷的生成。
在本实施例的MOSFET10中，如上所述，沟槽14还具有第三区间S3。第三区间S3在沟槽14的长边方向上位于第一区间S1和第二区间S2之间。第三区间S3是未设置连接区42的区间，与第一区间S1相同，是在MOSFET10导通时形成沟道的区间。在此，第三区间S3中的沟槽14的开口宽度W3比第一区间S1中的沟槽14的开口宽度W1大。而且，第三区间S3的沟槽14的侧面14a的倾倒角度C3比第二区间S2中的倾倒角度C2小。根据这种结构，通过设置第三区间S3，形成沟道的沟槽14的侧面14a扩大。具体而言，沟槽14的侧面14a扩大图5中剖面线所示的部分，但该剖面线部分是漂移层34在沟槽14的侧面14a露出的范围，是在导通时形成沟道的范围。通过以这种方式在沟槽14中设置第三区间S3，能够扩大形成沟道的范围，能够降低MOSFET10的导通电阻。另外，图5中剖面线的部分是第三区间S3中的沟槽14的侧面14a的一部分，其倾倒角度与图8所示的角度C3相等，变得比较陡峭。因而，在该部分形成的沟道中，载流子的移动性变得比较高，所以MOSFET10的导通电阻能够被有效地降低。虽然是一个示例，但包含图5中剖面线部分在内的第三区间S3中的沟槽14的侧面14a可以与沟槽14的深度方向D大致平行。即，第三区间S3的倾倒角度C3可以大致为0。
虽然未特别限定，但在上述第三区间S3，开口宽度W3可以与第二区间S2的开口宽度W2相等。而且，侧面14a的倾倒角度C3可以与第一区间S1的倾倒角度C1相等。根据这种结构，能够避免沟槽14的形状变得过于复杂，并能充分增大形成沟道的沟槽14的侧面14a。
接下来，参照图9～图12，对形成沟槽14的工序的一例进行说明。首先，以如图9和10所示的形状将沟槽14形成在半导体基板12的上表面12a。沟槽14可以通过例如干蚀刻形成。在该阶段，第二部分S2形成为具有与第一部分S1相同的形状。即，第二区间S2中的倾倒角度C2’和开口宽度W2’可以与第一区间S1中的倾倒角度C1和开口宽度W1相等。如果是这种形状的沟槽14，则利用一次干蚀刻就能形成。在此，在形成沟槽14之前，可以在半导体基板12上先形成源极区38。在此情况下，通过形成沟槽14，能够使源极区38在沟槽14的侧面14a露出。
然后，如图11和图12所示，通过实施第二次干蚀刻，能够将第二区间S2形成为所希望的形状。即，增大第二区间S2中的开口宽度W2’，并增大侧面14a的倾倒角度C2’。在该步骤中，可以通过用例如氧化硅埋没整个沟槽14并随后除去第二区间S2中的氧化硅，对已完工的第一区间S1和第三区间S3进行掩蔽。因而，能够有选择地仅对沟槽14的第二区间S2进行蚀刻。而且，通过变更干蚀刻的条件，能够适当地调整侧面14a的倾倒角度C2。
(实施例2)
参照图13和图14，对实施例2的IGBT110进行说明。上述MOSFET10中的沟槽14的结构能够在沟槽栅极型半导体装置中广泛使用。虽然在下文说明应用于IGBT110的示例，但是通过对与MOSFET10共同的结构标注相同的附图标记，来适当地省略其说明。
与实施例1的MOSFET10相同，IGBT110包括半导体基板112、设置于半导体基板112的上表面112a的上表面电极16、设置于半导体基板112的下表面112b的下表面电极18及多个栅电极20。在半导体基板112的上表面112a设置有多个沟槽14，经由栅极绝缘膜22将栅电极20设置在各个沟槽14内。
与实施例1的MOSFET10相同，半导体基板112具有：与上表面电极16接触的p型体层36；位于体层36与下表面电极18之间的n型漂移层34；位于漂移层34内且沿沟槽14的底面14b设置的p型浮置区40；及沿着沟槽14的侧面14a在体层36与浮置区40之间延伸的p型连接区42。针对沟槽14，也与实施例1的MOSFET10相同，沿着俯视时的长边方向，具有未设置连接区42的第一区间S1及设置有连接区间42的第二区间S2。而且，第二区间S2中的沟槽14的侧面14a的倾倒角度C2比第一区间S1中的沟槽14的侧面14a的倾倒角度C1大(参照图4～图8)。在本实施例中，虽然沟槽14还具有第三区间S3，但第三区间S3并非是必不可少的。
另一方面，作为与实施例1的MOSFET10的不同之处，代替漏极层32，半导体基板112具有p型集电极层132，并且，代替源极区38，半导体基板112具有n型发射极区138。集电极层132沿着半导体基板112的下表面112b设置，并与下表面电极18接触。集电极层132中的p型杂质的浓度足够高，下表面电极18与集电极层132欧姆接触。另一方面，发射极区138沿着半导体基板112的上表面112a设置，并与上表面电极16接触。发射极区138中的n型杂质的浓度足够高，上表面电极16与发射极区138欧姆接触。虽然名称不同，但发射极区138在结构上可以与实施例1中的源极区38相同。半导体基板112在集电极层132和漂移层34之间还具有n型缓冲层133。缓冲层133的n型杂质的浓度比漂移层34中的n型杂质的浓度高。另外，缓冲层133并不是必不可少的。
在上述IGBT110中，沟槽14和与其相关的结构也与实施例1的MOSFET10通用，所以能够实现实施例1中说明的作用和效果。即，根据本实施例的IGBT110的结构，能够维持或降低导通电阻，并沿着沟槽14的侧面14a容易地形成连接区42。

Claims (10)

1.一种半导体装置，具备：
半导体基板，在上表面具有沟槽；
上表面电极，设置于所述半导体基板的所述上表面；
下表面电极，设置于所述半导体基板的位于所述上表面的相反侧的下表面；及
栅电极，经由栅极绝缘膜而设置于所述沟槽内，
所述半导体基板具有：
P型体层，与所述上表面电极接触；
n型漂移层，介于所述体层与所述下表面电极之间；
p型浮置区，位于所述漂移层内并且沿着所述沟槽的底面设置；及
p型连接区，沿着所述沟槽的侧面在所述体层与所述浮置区之间延伸，
所述沟槽沿着俯视时的长边方向具有未设置所述连接区的第一区间及设置有所述连接区的第二区间，
所述第二区间中的所述沟槽的所述侧面的倾倒角度比所述第一区间中的所述沟槽的所述侧面的倾倒角度大。
2.根据权利要求1所述的半导体装置，其中，
所述第二区间中的所述沟槽的开口宽度比所述第一区间中的所述沟槽的开口宽度大。
3.根据权利要求1或2所述的半导体装置，其中，
所述沟槽还具有第三区间，所述第三区间在所述长边方向上位于所述第一区间与所述第二区间之间，且未设置所述连接区，
所述第三区间中的所述沟槽的开口宽度比所述第一区间中的所述沟槽的开口宽度大，并且，所述第三区间中的所述侧面的所述倾倒角度比所述第二区间中的所述侧面的所述倾倒角度小。
4.根据权利要求3所述的半导体装置，其中，
所述第三区间中的所述沟槽的开口宽度与所述第二区间中的所述沟槽的开口宽度相等，所述第三区间中的所述侧面的所述倾倒角度与所述第一区间中的所述侧面的所述倾倒角度相等。
5.根据权利要求3所述的半导体装置，其中，
所述第三区间中的所述侧面的所述倾倒角度大致为0。
6.根据权利要求4所述的半导体装置，其中，
所述第三区间中的所述侧面的所述倾倒角度大致为0。
7.根据权利要求1～2、4～6中任一项所述的半导体装置，其中，
所述半导体装置是MOSFET，
所述半导体基板还具有：
n型源极区，与所述上表面电极接触并经由所述栅极绝缘膜而与所述栅电极相对，且经由所述体层而与所述漂移层隔开；及
n型漏极层，与所述下表面电极接触并经由所述漂移层而与所述体层隔开。
8.根据权利要求3所述的半导体装置，其中，
所述半导体装置是MOSFET，
所述半导体基板还具有：
n型源极区，与所述上表面电极接触并经由所述栅极绝缘膜而与所述栅电极相对，且经由所述体层而与所述漂移层隔开；及
n型漏极层，与所述下表面电极接触并经由所述漂移层而与所述体层隔开。
9.根据权利要求1～2、4～6中任一项所述的半导体装置，其中，
所述半导体装置是IGBT，
所述半导体基板还具有：
n型发射极区，与所述上表面电极接触并经由所述栅极绝缘膜而与所述栅电极相对，且经由所述体层而与所述漂移层隔开；及
p型集电极层，与所述下表面电极接触并经由所述漂移层而与所述体层隔开。
10.根据权利要求3所述的半导体装置，其中，
所述半导体装置是IGBT，
所述半导体基板还具有：
n型发射极区，与所述上表面电极接触并经由所述栅极绝缘膜而与所述栅电极相对，且经由所述体层而与所述漂移层隔开；及
p型集电极层，与所述下表面电极接触并经由所述漂移层而与所述体层隔开。
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