CN109427876A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN109427876A
CN109427876A CN201810953004.XA CN201810953004A CN109427876A CN 109427876 A CN109427876 A CN 109427876A CN 201810953004 A CN201810953004 A CN 201810953004A CN 109427876 A CN109427876 A CN 109427876A
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Prior art keywords
conductive film
film
semiconductor devices
devices according
crystal
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CN201810953004.XA
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利根川丘
稻川浩巳
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN109427876A publication Critical patent/CN109427876A/zh
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Abstract

为了提高半导体器件的可靠性。提供了半导体器件及其制造方法，该半导体包括：焊盘电极，形成在半导体衬底之上，并且包括第一导电膜和形成在第一导电膜之上的第二导电膜；以及镀膜，形成在第二导电膜之上，并且用于耦合至外部连接端子(TR)。第一导电膜和第二导电膜主要包含铝。第一导电膜的表面上的晶体表面不同于第二导电膜的表面上的晶体表面。

Description

半导体器件及其制造方法
相关申请的交叉引用
2017年8月24日提交的日本专利申请第2017-161043号的包括说明书、附图和摘要的公开通过引证引入本文。
技术领域
本发明涉及一种半导体器件及其制造方法，其例如可应用于具有OPM电极的半导体器件及其制造方法。
背景技术
近年来，基于提高半导体器件可靠性等的需求，提出了一种通过在半导体衬底上形成主要包含铝的焊盘电极、在焊盘电极上形成称为OPM(焊盘上金属)电极的导电层并将外部耦合端子(诸如夹或接合线)耦合至OPM电极而得到的结构。
例如，日本未审查专利申请公开第2000-235964号公开了一种使用化学镀在主要包含铝的焊盘电极上形成由镍膜和金膜制成的OPM电极的技术。
此外，日本未审查专利申请公开第2007-227412号公开了一种IGBT模块，其包括相互反平行耦合的二极管和IGBT(绝缘栅型双极晶体管)。
此外，“Zincate Treatment and Electroless Ni-P Plating on Al Single-Crystal Surface”(日本Journal of The Surface Finishing Society，第48卷，第8期，第820-825页，1997年)公开了以下技术：从单晶铝(Al)获得(100)表面、(110)表面和(111)表面，然后对这些表面执行使用含锌(Zn)水溶液的锌酸盐处理和化学镀Ni-P处理。上述文献描述了晶体表面的差异如何影响沉积Zn颗粒的尺寸和Ni-P镀膜的生长的研究。
发明内容
如“Zincate Treatment and Electroless Ni-P Plating on Al Single-Crystal Surface”(日本Journal of The Surface Finishing Society，第48卷，第8期，第820-825页，1997年)所公开的，当对铝的(100)表面执行锌酸盐处理时，存在相对较大的Zn颗粒被沉积并且形成于其上的Ni-P镀膜的厚度可能不均匀的问题。由于Ni-P镀膜的表面粗糙且不存在致密膜，所以湿气可容易地从半导体器件的外部进入。这可能导致如下问题：在Ni-P镀膜和铝膜之间的界面发生腐蚀，这增加了Ni-P镀膜与铝膜分离的可能性。在这种情况下，如日本未审查专利申请公开第2000-235964中所描述的，如果在主要包含铝的焊盘电极上形成由镍等的镀膜制成的OPM电极，则OPM电极容易从焊盘电极上除去，从而降低了半导体器件的可靠性。
其他的问题和新颖特征将从下面的描述和附图中变得明显。
下面简要地描述本文公开的一个代表性实施例的概要。
根据一个实施例的半导体器件及其制造方法，该半导体器件包括：焊盘电极，形成在在半导体衬底之上，并且包括第一导电膜和形成在第一导电膜之上的第二导电膜；以及镀膜，形成在第二导电膜之上并且用于耦合至外部连接端子。
根据一个实施例，可以提高半导体器件的可靠性。
附图说明
图1是根据第一实施例的半导体器件的截面图；
图2是图1之后的制造工艺期间的半导体器件的截面图；
图3是图2之后的制造工艺期间的半导体器件的截面图；
图4是图3之后的制造工艺期间的半导体器件的截面图；
图5是图4之后的制造工艺期间的半导体器件的截面图；
图6是图5之后的表示半导体器件的制造工艺的流程图；
图7是图6之后的制造工艺期间的半导体器件的截面图；
图8是模块化形式的根据第一实施例的半导体器件和IGBT的示意图；
图9是示出图8的半导体器件处于安装状态的平面图；
图10是沿图9中的线A-A截取的截面图；
图11是第三实施例的半导体器件的主要部分的截面图；
图12是图11之后的制造工艺期间的半导体器件的截面图；
图13是图12之后的制造工艺期间的半导体器件的截面图；以及
图14是示出图13的半导体器件处于安装状态的平面图。
具体实施方式
在下面的实施例中，尽管根据方便的需要对于每个部分或每个实施例给出了解释，但各部分或实施例并非彼此无关，而是一个可以是对另一个的修改、详细描述或补充说明的一部分或全部，除非另有说明。
此外，在以下实施例中，当引用元素的数量(包括数量、数值、量、范围等)时，它不限于具体数字，而是可以比具体数字多或少，除非另有指定或原理上明确限定为具体数字。
此外，在以下实施例中，除非另有指定或者原则上明确必要，否则部件(包括元素步骤)不一定是必需的。
类似地，在以下实施例中，当参照部件的形状、位置关系等时，除非原则上另有指定或明确不适用，否则包括基本近似或类似的形状。这也适用于上述数值和范围。
在用于示出实施例的附图中，类似于参考数字原则上指定类似的部分，并且不重复其描述。应注意，为了更好地理解，平面图可以具有阴影。
[第一实施例]
参考图1至图7，给出根据第一实施例的半导体器件及其制造方法的解释。该实施例提出了一种二极管DI，其被用作超快恢复二极管(快恢复二极管)，例如作为安装在半导体器件上的半导体元件。
如图1所示，首先制备衬底，其具有n型导电性并且包括诸如硅的半导体。衬底配置二极管DI的漂移区DR。然后，通过离子注入等，在漂移区DR的表面附近形成具有p型导电性的杂质区AN。杂质区AN配置二极管DI的阳极区。
该实施例描述了包括漂移区DR和阳极区AN的配置(作为半导体衬底SUB)。
这里，漂移区DR的表面上的晶体表面是(001)表面。由于通常使用具有(001)表面的硅衬底，所以与制备具有另一晶体表面的衬底相比，可以降低制造成本。此外，形成在漂移区DR的表面之上的阳极区AN的表面上的晶体表面也是(001)表面。即，半导体衬底SUB的表面上的晶体表面为(001)表面。
此外，图1示出了绝缘膜IF1形成在半导体衬底SUB的表面之上作为薄自然氧化膜或异物的状态。
接下来，如图2所示，半导体衬底SUB的表面例如经受作为清洁处理的使用含四氟化碳(CF4)气体的反应干蚀刻处理以及使用含氟化氢(HF)清洁液的湿蚀刻处理。清洁处理去除沉积在半导体衬底SUB(包括阳极区AN)的表面之上的绝缘膜IF1。执行清洁处理主要是为了减小二极管DI的正向电阻，并由此降低半导体衬底SUB与稍后将形成的焊盘电极PD之间的接触电阻。
接下来，如图3所示，例如，通过溅射，主要包含铝且掺有少量硅的导电膜AL1形成在半导体衬底SUB之上。导电膜AL1的厚度约为2500nm。通过溅射形成导电膜AL1的温度约为室温(23℃)至200℃，更优选约为150℃。应注意，导电膜AL1为什么掺有少量硅的原因在于：防止导电膜AL1与半导体衬底SUB之间的界面具有穗形。
这里，当导电膜AL1是铝膜时，通过上面提到的溅射形成铝膜使得铝膜的晶体结构是面心立方结构(FCC：面心立方)，因此导电膜AL1在其几乎所有不被其基础影响的表面上具有(111)表面或者紧密包裹的表面。然而，根据实施例的导电膜AL1被形成为接管半导体衬底SUB的晶体表面，由此导电膜AL1的表面上的晶体表面为(001)表面。这是因为在图2所示的清洁处理之后立即执行形成导电膜AL1的步骤，因此导电膜AL1趋于在形成步骤期间接管半导体衬底SUB的表面上的晶体表面。此外，通过根据该实施例的二极管DI，为了减小正向电阻的目的，比导电膜AL1具有更高电阻的包括氮化钛的阻挡金属膜不形成在导电膜AL1与半导体衬底SUB之间，而是将导电膜AL1直接形成在半导体衬底SUB之上。
考虑到结晶学，对于立方晶体，(001)表面相当于(100)表面和(010)表面作为晶体表面。因此，根据实施例的导电膜AL1的(001)表面被处理为在“Zincate Treatment andElectroless Ni-P Plating on Al Single-Crystal Surface”(日本Journal of TheSurface Finishing Society，第48卷，第8期，第820-825页，1997年)中公开的等效于(100)表面的晶体表面。这里，如上述文献所描述的，存在以下问题：当在以下步骤中对导电膜AL1的(001)表面执行锌酸盐处理时，具有相对较大尺寸的锌颗粒被沉积，导致在以下步骤中形成的镍等的镀膜的不均匀厚度。这会引起镀膜和导电膜AL1之间的分离，从而降低半导体器件的可靠性。
换言之，除非如该实施例执行清洁处理，否则薄自然氧化膜或异物存在于半导体衬底的表面之上。如果以这种状态形成导电膜AL1，则导电膜AL1会难以接管半导体衬底SUB的表面上的晶体表面，使得除了(001)表面以外的晶体表面更容易地形成在导电膜AL1的表面之上。然而，为了降低二极管DI的电阻，期望执行清洁处理以去除薄自然氧化膜或异物。这可以使配置焊盘电极PD的导电膜AL1的表面为(001)表面。
因此，发明人提出通过执行清洁处理降低二极管DI的电阻并使焊盘电极PD表面上的晶体表面与(001)表面不同的方法。
图4是图3之后的半导体器件的制造方法的截面图。
如参考图3所描述的，导电膜AL1的表面上的晶体表面是(001)表面。在这种状态下，如图4所示，首先在导电膜AL1之上形成绝缘膜BIF。绝缘膜BIF通过将导电膜AL1的表面暴露于包含氧气的氛围中而形成，例如通过从溅射设备中取出半导体衬底SUB并将半导体衬底SUB暴露于室温(23℃)的氛围中。也就是说，绝缘膜BIF包括形成导电膜AL1的材料的氧化物，诸如氧化铝。绝缘膜BIF的厚度范围为0.5nm到4.0nm，更优选为1.0nm到3.0nm。
接下来，例如，通过溅射，在绝缘膜BIF之上形成例如主要包含铝且掺有硅的导电膜AL2。导电膜AL2的厚度约为2500nm。用于通过溅射形成导电膜AL2的温度介于大约室温(23℃)和200℃之间，更优选为约150℃。
现在，由于绝缘膜BIF形成在导电膜AL2和导电膜AL1之间，所以导电膜AL2不接管作为导电膜AL1的表面上的晶体表面的(001)表面，因此且可以形成有不同于(001)表面的晶体表面。
在该实施例中，在通过溅射形成导电膜AL2的初始阶段，导电膜AL2的表面上的晶体表面主要是(111)表面。具体来说，导电膜AL2的90％以上的表面积是(111)表面。以这种方式，即使在膜形成的初始阶段之后在导电膜AL2的一部分上保留(110)表面，由于(110)表面上的颗粒被(111)表面(通过溅射在膜形成的随后阶段中配置导电膜AL2的大部分)的颗粒所覆盖，所以导电膜AL2的表面的大部分最终变为(111)表面。优选地，导电膜AL2的90％以上的表面最终为(111)表面，更优选地，导电膜AL2的99％以上的表面最终为(111)表面。
以这种方式，通过在具有(100)晶体表面的导电膜AL1的表面上方形成薄绝缘膜BIF，将成为焊盘电极PD表面的导电膜AL2的表面上的晶体表面可以为(111)表面。即，绝缘膜BIF是用作用于阻挡晶体的定向的膜的定向阻挡膜。
尽管实施例示出了具有导电膜AL1和导电膜AL2的两层结构的焊盘电极PD，但焊盘电极PD可以通过在导电膜AL1之上进一步形成绝缘膜(诸如绝缘膜BIF)且随后在其上形成导电膜(诸如导电膜AL2)来具有三层或更多层。
此外，如上所述，绝缘膜BIF的厚度不小于0.5nm且不大于4.0nm，更优选不小于1.0nm且不大于3.0nm。这是导电膜AL2不接管导电膜AL1的晶体表面并且足以在导电膜AL2和导电膜AL1之间保证导电性的厚度范围。即，由于在该实施例中所述，向该二极管DI施加了几百万伏的电压，所以具有上述厚度的绝缘膜BIF不会影响二极管DI的特性。
接下来，如图5所示，通过使用光刻和干蚀刻对导电膜AL2、绝缘膜BIF和导电膜AL1进行图案化，形成主要包含导电膜AL2和导电膜AL1的焊盘电极PD。
然后，在半导体衬底SUB之上形成包括有机树脂(诸如光敏聚酰亚胺)的绝缘膜IF2，以覆盖焊盘电极PD。然后，通过选择性地将绝缘膜IF2暴露于光，在绝缘膜IF2之上形成暴露焊盘电极PD的一部分的开口OP1。应注意，绝缘膜IF2的材料可以是无机绝缘膜，诸如氧化硅或氮化硅，而不是上述有机树脂。
图6示出了直到在稍后描述的图7中形成的导电层OPM的步骤的工艺流程，示出将在焊盘电极PD上执行的等离子体蚀刻处理S11和镀制处理S12-S20。在该实施例中，镀制处理被描述为包括表面处理S12-S14、锌酸盐处理S15-S17以及化学镀处理S18-S20。在S12-S20的每个工艺之后，可以执行纯水清洁处理。
在通过化学镀处理S18-S20在焊盘电极PD之上形成作为镀膜的导电膜PF1-PF3之前，在焊盘电极PD的表面上执行等离子体蚀刻处理S11和表面处理S12-S14。执行等离子体蚀刻处理S11和表面处理S12-S14，以去除焊盘电极PD表面之上存在的天然氧化膜、油脂、异物等。
如图6中的步骤S11所示，首先使用诸如氩气(Ar)的惰性气体在导电膜AL2的表面上执行等离子蚀刻处理。通过等离子体蚀刻处理去除导电膜AL2的表面之上的自然氧化膜。
接下来，以表面处理S12-S14、锌酸盐处理S15-S17以及化学镀处理S18-S20的顺序，在导电膜AL2的表面上执行镀制处理。
如图6中的步骤S12所示，使用含有氢氧化钠等的弱碱性水溶液，在导电膜AL2的表面上执行脱脂处理。主要通过脱脂处理去除导电膜AL2的表面之上的油脂以及导电膜AL2的表面之上的自然氧化膜。
接下来，如图6的步骤S13所示，使用例如包含铜(Cu)的碱性水溶液执行蚀刻处理。执行蚀刻处理以去除导电膜AL2表面附近的氧化铝，在如该实施例中导电膜AL2由掺有硅的铝制成的情况下这是有效的。即，通过利用碱性水溶液溶解导电膜AL2表面附近存在的氧化铝并且用铜置换铝(铜具有的标准电极电势高于铝的标准电极电势)，可以有效地减少导电膜AL2的表面附近存在的氧化铝。
接下来，如图6中的步骤S14所示，使用例如包含硝酸的水溶液对导电膜AL2的表面执行酸性清洁。酸性清洁使得在步骤S13中置换的铜被溶解在包含消散的水溶液中，并且用于从导电膜AL2的表面去除铜。
接下来，如图6中的步骤S15所示，在导电膜AL2的表面上执行第一锌酸盐处理。
如“Zincate Treatment and Electroless Ni-P Plating on Al Single-Crystal Surface”(日本Journal of The Surface Finishing Society，第48卷，第8期，第820-825页，1997年)所公开的，如果导电膜AL2的表面是(001)表面，则锌颗粒的生长将会更少，并且其尺寸可进一步增加。
接下来，如图6中的步骤S16所示，在导电膜AL2的表面上执行酸性清洁。例如，通过使用含有硝酸的水溶液，通过第一锌酸盐处理沉积的锌颗粒被溶解在包含硝酸的水溶液中。这种处理使得铝均匀地出现在导电膜AL2的表面上。
接下来，如图6中的步骤S17所示，在导电膜AL2的表面上执行第二锌酸盐处理。这使得锌颗粒被再次沉积到铝上。可以通过重复两次锌酸盐处理来形成致密且均匀的Zn膜。这使得将在稍后步骤中形成的镍等的镀膜被均匀地沉积。
接下来，如图6和图7中的步骤S18至S20所示，在焊盘电极PD的表面上执行化学镀处理，从而顺序地形成导电薄膜PF1至PF3。
首先，如图6中的步骤S18所示，通过化学镀，主要包含镍(Ni)等的导电膜PF1形成在焊盘电极PD的暴露表面(导电膜AL2的表面)之上。为了形成导电膜的PF1，导电膜AL2的表面被浸在包含镍离子等的镀制水溶液中。此时，通过图6中的锌酸盐处理沉积的锌颗粒溶解在镀制水溶液中。同时，通过从锌颗粒发射的电子还原并沉积镍。即，在沉积锌颗粒的区域中，镍被还原和沉积，并且镀膜将沉积的镍用作催化剂来生长，从而形成导电膜PF1。如上所述，由于每个锌颗粒的尺寸较小且横向，所以置换和沉积的镍膜也均匀地生长。因此，可以改进导电膜PF1的厚度的均匀性。
然后，如步骤S19和S20所示，通过化学镀在导电膜PF1之上顺序地形成主要包含钯(Pd)等的导电膜PF2以及主要包含金(Au)的导电膜PF3，导电层OPM包括镀膜的层压。因为形成在导电膜PF1之上的导电膜PF2和PF3具有高度均匀的厚度，所以导电膜PF2和导电膜PF3也形成有高度均匀的厚度。因此，可以改进导电层OPM的厚度均匀性。
应注意，导电膜PF1的厚度约为1000-4000nm，导电膜PF2的厚度约为100-400nm，以及导电膜PF3的厚度约为30-200nm。
由于导电膜PF1是导电层OPM的主膜，所以优选包括具有低表面电阻的材料。导电膜PF3被设置为主要提高与外部连接端子TR的粘附性，并且优选包括与导电膜PF1相比具有与外部连接端子TR更高的粘附性的材料。导电膜PF2被设置为防止导电膜PF1在导电膜PF3的表面之上扩散来腐蚀导电膜PF1和导电膜PF3之间的边界。
此外，导电层OPM可以为导电膜PF1和导电膜PF3的层压膜或者导电膜PF1和导电膜PF2的层压膜。此外，导电膜PF1和导电膜PF2可包含磷(P)。
以这种方式，包括镀膜的导电层OPM被形成在焊盘电极PD之上。应注意，导电层OPM配置二极管DI的阳极电极。
接下来，阴极区CT和背电极BE被形成在半导体衬底SUB的背侧上。
首先，对半导体衬底SUB的背侧进行抛光，以减小半导体衬底SUB的厚度。接着，使用离子注入从半导体衬底SUB的背侧引入n型杂质，以形成具有比漂移区DR更高的杂质浓度的阴极区CT。随后，通过热处理激活引入的杂质。然后，例如，使用溅射从邻接阴极区CT的一侧按顺序沉积包括镍(Ti)、钛(Ti)、金(Au)的金属膜，从而形成包括这些金属膜的阴极电极(背电极)BE。
在上面提到的步骤中制造根据该实施例的半导体器件。
图8是示出一种配置的示意图，其中根据该实施例的半导体器件形成于其上的半导体晶圆通过处理后的处理的切割步骤被切割成芯片CP1，然后包括根据该实施例的二极管DI和IGBT的半导体元件被模块化。在示意图中，诸如导电层OPM的配置的尺寸与参照图7所描述的尺寸不同。
在图8中，芯片CP1是包括形成于其上的包括根据该实施例的二极管DI的半导体器件，并且芯片CP2是包括形成于其上的IGBT的半导体元件的半导体器件。
IGBT包括在图8左侧示出的配置。如图8所示，在配置漂移区1的n型半导体衬底的表面之上形成p型基底层2。在基底层2的表面之上形成n型源极层3，并且基底层2和源极层3共同耦合至包括铝膜等的发射极电极6。布置在漂移区1和源极层3之间的基底层是沟道区，并且栅电极5经由栅极绝缘膜4形成在沟道区之上。在漂移区1的背侧之上形成掺杂n型杂质的缓冲层7、掺有p型杂质的发射极层8以及集电极9。
此外，如图8所示，二极管DI的阴极电极和IGBT的集电极电极9相互电耦合，并且二极管DI的阳极电极(导电层)OPM与IGBT的发射极电极6也相互电耦合。
图9和图10示出了图8所示配置IGBT的芯片CP1和芯片CP2被封装的示例。图10是沿着图9所示的平面图中的线A-A截取的截面图。应注意，为了更好地理解外部连接端子TR的形状，在图9中省略图10示出的密封树脂MR和裸片焊盘DP。这里示出了芯片CP1和芯片CP2使用例如包括铜片的夹子作为外部连接端子TR的示例耦合在单个封装中。
如图9和图10所示，芯片CP1和芯片CP2经由焊料BP1安装在裸片焊盘DP之上。裸片焊盘DP还用作向芯片CP1和芯片CP2提供电源电位的电源电位端子DT。即，芯片CP1的阴极电极BE和芯片CP2的集电极电极9经由焊料BP1电耦合至电源电位端子DT(裸片焊盘DP)。
此外，外部连接端子TR经由焊料BP2耦合至芯片CP1和芯片CP2。外部连接端子TR经由导电胶等电耦合至地电位端子ST。芯片CP1导电层OPM耦合至焊料BP2。即，芯片CP1的阳极电极(导电层)OPM和芯片CP2的发射极电极6经由焊料BP2和外部连接端子TR电耦合至地电位端子ST。
虽然没有提供详细的解释，但IGBT的栅电极5经由除外部连接端子TR外的接合线等耦合至另一端子.
耦合至裸片焊盘DP和外部连接端子TR的芯片CP1和芯片CP2用密封树脂MR来密封。以这种方式，根据该实施例的半导体器件被封装。
此外，外部连接端子TR可以是包括铜或金的接合线。然而，对于具有二极管DI的大面积的阳极电极(导电层)OPM和IGBT的大面积的发射极电极6并且如该实施例接收百万伏特的电压的这种半导体器件，期望使用具有较大面积的铜芯片以减小与另一芯片的耦合相关的电阻。还可以使用烧结银(Ag)来代替焊料BP1、BP2。
下面，将简要总结该实施例的主要特征。该实施例的特征在于，导电膜AL2的表面上的晶体表面由与导电膜AL1表面上的晶体表面不同的晶体表面形成。
例如，当焊盘电极PD的表面上的晶体表面形成有(001)表面时，在图6中的第一和第二锌酸盐处理中，存在以下问题：沉积的锌颗粒的尺寸如此大，以致于通过化学镀形成的诸如镍的镀膜的沉积不能均匀地执行，并且镀膜的表面变得粗糙。因此，湿气等进入焊盘电极PD与导电层OPM之间的截面，以促进该部分的分离，降低了半导体器件的可靠性。此外，在镀膜表面上观察到外观异常。
相反，在该实施例中，通过在具有(001)表面的导电膜AL1之上形成薄绝缘膜BIF，形成在绝缘膜BIF之上的导电膜AL2不受导电膜AL1表面上的晶体表面的影响，从而使得导电膜AL2的表面上的晶体表面具有(111)表面。因此，由于在图6所示的第一和第二锌酸盐处理期间沉积的每个锌粒子的尺寸均匀且细小，所以通过化学镀形成的包括镍等的导电膜PF1可以相对均匀地形成。这允许在焊盘电极PD和导电层OPM之间的界面上难以引起分离的配置，从而提高了半导体器件的可靠性。此外，可以使镀层的表面上的外观异常最小化。
具体地，在该实施例中，在用作导电膜AL1的基底的半导体衬底SUB上执行清洁处理，以保持半导体衬底SUB的表面清洁。这减小了半导体衬底SUB与导电膜AL1之间的接触电阻，从而降低了二极管DI的电阻。然而，由于导电膜Al1趋于接管半导体衬底SUB的表面上的晶体表面的(001)表面，所以导电膜AL1的表面上的晶体表面也趋于具有(001)表面。这里，通过如上所述经由绝缘膜BIF在导电膜AL1之上形成导电膜AL2，导电膜AL2的表面上的晶体表面可以具有(111)表面，这实现了难以在焊盘电极PD和导电层OPM之间的界面上引起分离的结构。即，使用该实施例的技术可以提高半导体器件的性能，并且还提高了半导体器件的可靠性。
[第一实施例的第一修改例]
在第一实施例中，如图4所示，绝缘膜BIF通过一次从溅射设备取出半导体衬底SUB并将其暴露于大气中而形成在导电膜AL1之上。
相反，根据第一修改例，半导体衬底SUB被转移到另一腔室而不将其从溅射设备中取出，将含氧气体引入溅射设备，并且导电膜AL1的表面暴露于氧气氛围，从而形成绝缘膜BIF。具体地，在室温下的氧气氛围中执行暴露给这种氧气氛围。氧化处理后可与热处理相结合，并且可通过使用氧气发射等离子体来进行。
随后，如第一实施例，导电膜铝AL2通过溅射形成在绝缘膜BIF上方，而不从溅射设备取出半导体衬底SUB。
以这种方式，由于无需从溅射设备取出半导体衬底SUB来形成绝缘膜BIF，所以可以立即执行形成导电膜AL2的下一步骤。因此，与第一实施例相比，可以简化制造半导体器件的工艺。
[第一实施例的第二修改例]
在第一实施例中，导电膜AL2使用与导电膜AL1相同的材料配置，该材料主要包含例如掺有硅的铝。
与此不同地，在第二修改例中，导电膜AL2使用与导电膜AL1不同的材料配置，该材料主要包含例如掺有铜的铝。即，掺杂到导电膜AL2中的元素不同于掺杂到导电膜AL1中的元素。
为了减少半导体衬底SUB与导电膜AL1之间的界面上的穗形，导电膜AL1与二极管DI直接接触，并且由掺有硅的铝膜制成。然而，由于导电膜AL2不与二极管DI直接接触，所以导电膜AL2的材料可以是除掺有硅的铝膜之外的材料。这里，因为掺铜铝膜比掺硅铝膜显示出更好的电迁移，所以掺铜铝膜被用作第二修改例的导电膜AL2。
此外，通过使用掺铜铝膜作为导电膜AL2，可以省略图6中的步骤S13的蚀刻处理。即，在上述步骤S13中，使用具有高标准电极电位的包含铜的水溶液来置换导电膜AL2的表面之上存在的氧化铝。然而，在第二修改例中，铜已经包括在导电膜AL2中。因此，可以通过步骤S12中使用碱性水溶液的脱脂处理或者随后的锌酸盐处理，可以更加有效地去除导电膜Al2的表面之上的氧化物。锌酸盐处理进一步有利于锌颗粒的沉积，并且化学镀处理进一步利于置换和沉积镍。因此，由于可以在第二修改例中省略图6所示的步骤S13，所以可以简化半导体器件的制造方法。
此外，导电膜AL2可由主要包含铝且掺有铜和硅的材料制成。
应注意，在第二修改例中公开的技术也可应用于上述第一修改例。
[第二实施例]
在第一实施例中，绝缘膜BIF形成在导电膜AL1之上，以将导电膜AL2的晶体表面与导电膜AL1的晶体表面区分开来。
相反，在第二实施例中，在导电膜AL1之上形成非晶膜，该非晶膜是由与导电膜AL1不同的材料制成的导电膜并且在导电膜AL1之上呈非晶态。应注意，非晶膜置换第一实施例中的绝缘膜BIF，因此没有在附图中显示。换句话说，图4等所示的参考符号“BIF”指定非晶膜。
这种非晶膜通过溅射或CVD形成，并且通过主要包含例如钽、氮化钛或氮化钨的膜配置。此外，非晶膜的厚度介于0.5nm和4.0nm之间，更优选地在1.0nm和3.0nm之间。即，只要具有如此小的膜厚，上述材料就可以显示出非晶状态。由于非晶膜处于非晶态，所以其不具有特定晶体表面。因此，当导电膜AL2通过溅射形成在非晶膜之上时，导电膜AL2不接管导电膜AL1的晶体表面，而是主要基于(111)表面生长，如第一实施例中那样。即，非晶膜是用作用于阻挡晶体的定向的膜的定向阻挡膜，如绝缘膜BIF。因此，根据第二实施例的半导体器件可以提供与第一实施例相同的效果。
应注意，上述第一实施例的第二修改例可应用于第二实施例公开的技术。
[第三实施例]
在第三实施例中，第一实施例中使用的导电膜AL1和导电膜AL2应用于功率MOS的布线。这里，作为功率MOS的布线的示例，描述了导电膜AL1和导电膜AL2被应用于源电极SPD的情况。
下面参照图11至图13描述根据第三实施例的半导体器件的结构及其制造方法。
图11示出了n型功率MOS，其包括n型栅电极GE、栅极绝缘膜GI、覆盖栅电极GE的绝缘膜IF3、p型沟道区CH、n型源极区SR、用作漏极区的n型漂移区NV以及n型衬底SB。
下面描述制造这种功率MOS的示例性方法。
首先制备具有n型导电性且包括诸如硅的半导体的衬底SB。接下来，通过外延等，在衬底SB之上形成具有n型导电性且杂质浓度低于衬底SB的漂移区NV(杂质区NV)。在该实施例中，假设包括衬底SB和漂移区NV的结构作为半导体衬底SUB来给出解释。
在漂移区NV中形成凹槽之后，包括氧化硅的栅极绝缘膜GI形成在凹槽的侧面和底面之上。接下来，包括多晶硅等的栅电极GE形成在栅极绝缘膜GI之上以填充凹槽。然后，通过离子注入在漂移区NV的顶部上形成具有p型导电性的沟道区CH。沟道区CH和漂移区NV之间的边界位于栅电极GE的底面上方。然后，通过离子注入在沟道区CH的顶部上形成具有n型导电性的源极区SR(杂质区SR)。然后，绝缘膜IF3选择性地形成在源极区SR的一部分之上以及栅电极GE之上。接下来，通过对绝缘膜IF3上暴露的部分执行干蚀刻，形成通过源极区SR到达沟道区CH的开口OP2。如上所述制造n型功率MOS。
接下来，如图12所示，用作源电极SPD的导电膜AL1和导电膜AL2形成在绝缘膜IF3之上。
首先，在开口OP2中以及绝缘膜IF3之上形成包括钛钨(TiW)、氮化钛(TiN)等的阻挡金属膜BM。然后，主要包含例如铝的导电膜AL1形成在阻挡金属膜BM之上以填充开口OP2。这使得用作源电极SPD的一部分的导电膜AL1电耦合至源极区SR和沟道区CH。
应注意，在第三实施例中，不同于上述第一实施例和第二实施例，阻挡金属膜BM形成在半导体衬底SUB和导电膜AL1之间。因此，导电膜AL1可以使用主要包含铝且掺有硅的材料或者主要包含铝且掺有铜的材料。
这里，通过溅射形成导电膜AL1，并且形成工艺中的最大温度的范围为250到400度，这高于第一实施例。这是为了防止当导电膜AL1填充到开口OP2中时在导电膜AL1中形成空隙。可以在两个步骤中执行导电膜AL1的形成，包括在从室温(23℃)到200℃的低温下执行初始膜形成，以及在250℃至400℃的高温下执行的用于填充的第二步骤。此外，在位于开口OP2的顶部上的导电膜AL1的表面与位于栅电极GE的顶部上的导电膜AL1的表面之间产生阶梯。为了使阶梯最小化以使得导电膜AL1的整个表面尽可能平坦，在高温下有效地形成导电膜AL1。对于根据该实施例的半导体器件，在稍后步骤中，在源电极SPD之上形成导电层OPM。因此，通过在用作源电极SPD的一部分的导电膜AL1中消除任何空隙并且平坦化其表面，可以使导电层OPM的厚度更加均匀。
然而，在以相对较高的温度形成的这种铝膜中，铝颗粒的尺寸与如第一实施例以相对较低的温度形成的铝膜相比较大。即，导电膜AL1的表面上的晶体表面趋于不仅具有(111)表面而且还具有(001)表面。因此，如果导电层OPM形成在导电膜AL1之上，则会如第一实施例，容易地在源电极SPD和导电层OPM之间发生分离。
因此，在第三实施例中，与第一实施例相同，薄绝缘膜BIF形成在导电膜AL1之上，然后导电膜AL2形成在导电膜AL1之上。这可以区分导电膜AL2的表面上的晶体表面与导电膜AL1的表面上的晶体表面。应注意，形成绝缘膜BIF和导电膜AL2的方法与第一实施例相同。因此，该实施例中的导电膜AL2的表面上的晶体表面也是(111)表面。
在该实施例中，形成导电膜AL2的温度低于形成导电膜AL1的温度，并且例如约为室温(23℃)到200℃，更优选约为150℃。即，由于导电膜AL1以相对较高的温度形成，所以改进了其表面的平坦度，生成具有大颗粒尺寸的(001)表面的可能性也增加。因此，可以通过以相对较低的温度形成导电膜AL2来抑制具有大颗粒尺寸的(001)表面的生成。换句话说，在第三实施例中，导电膜AL2的表面上的(111)表面的面积比高于导电膜AL1的表面上的(111)表面的面积比。
然后，使用光刻和干蚀刻，通过图案化导电膜AL2、绝缘膜BIF、导电膜AL1和阻挡金属膜BM来形成图12所示的源电极SPD。应注意，将耦合至功率MOS的栅电极GE的栅极焊盘电极GPD也形成在此时(图中未示出)。
接下来，如图13所示，具有开口OP1的绝缘膜IF2形成在导电膜AL2之上，以暴露用作源电极SPD的一部分的部分导电膜AL2。应注意，形成绝缘膜IF2的方法及其材料与第一实施例相同。
接下来，通过使用与第一实施例相同的技术顺序地形成导电膜PF1至PF3，导电层OPM形成在开口OP1中的导电膜AL2之上。
然后，与第一实施例相同，衬底SB的背侧被抛光以形成漏电极(背电极)BE。
根据上述步骤制造第三实施例的半导体器件。
如上所述，根据第三实施例，可以抑制源电极SPD和导电层OPM之间的分离，并且得到与第一实施例相同的效果。
图14示出了包括形成于其上的根据第三实施例的功率MOS的芯片CP3处于封装状态的示图。这里，作为将耦合至导电层OPM的外部连接端子TR的示例，描述了使用由铜片制成的夹子的情况。
如图14所示，芯片CP3经由焊料BP3安装在裸片焊盘DP之上。裸片焊盘DP还用作向芯片CP3提供电源电位的电源电位端子DT。即，芯片CP3的漏电极BE经由焊料BP3电耦合至电源电位端子DT(裸片焊盘DP)。
此外，外部连接端子TR经由焊料BP4耦合至芯片CP3。外部连接端子TR经由焊料BP5电耦合至地电位端子ST。这里，芯片CP3的导电层OPM耦合至焊料BP4。即，芯片CP3的源电极SPD经由导电层OPM、焊料BP4、外部连接端子TR和焊料BP5电耦合至地电位端子ST。
此外，功率MOS的栅极焊盘电极GPD经由接合线WB耦合至栅极电位端子GT。
这种芯片CP3用密封树脂MR密封。以这种方式，根据第三实施例的半导体器件被封装。
此外，还可以将第一和第二实施例的第一和第二修改例的技术应用于第三实施例中公开的技术。
此外，尽管导电膜AL1和导电膜AL2被用作第三实施例中的功率MOS的源电极SPD，但还可以将导电膜AL1和导电膜AL2用作IGBT的发射极电极。此外，当应用于IGBT时，功率MOS的沟道区CH是基极区域。
此外，当将第三实施例中公开的技术应用于IGBT时，可使用第三实施例中描述的芯片CP3来代替第一实施例的图8至图10所示的芯片CP2。
尽管参照实施例具体描述了发明人做出的本发明，但本发明不限于这些实施例，而是在不背离本发明的范围的情况下可以进行各种修改。

Claims (20)

1.一种半导体器件，包括：
焊盘电极，形成在半导体衬底之上，并且包括第一导电膜和形成在所述第一导电膜之上的第二导电膜；以及
镀膜，形成在所述第二导电膜之上，并且用于耦合至外部连接端子，
其中所述第一导电膜和所述第二导电膜中的每一个均包括主要包含铝的膜，并且
其中所述第二导电膜的表面上的晶体表面不同于所述第一导电膜的表面上的晶体表面。
2.根据权利要求1所述的半导体器件，
其中所述第二导电膜与所述镀膜直接接触，并且
其中所述第二导电膜的表面上的晶体表面为(111)表面。
3.根据权利要求2所述的半导体器件，
其中在所述第一导电膜和所述第二导电膜之间形成第一绝缘膜，所述第一绝缘膜包括配置所述第一导电膜的材料的氧化物。
4.根据权利要求2所述的半导体器件，
其中在所述第一导电膜和所述第二导电膜之间形成非晶膜，所述非晶膜包括与所述第一导电膜和所述第二导电膜不同的材料。
5.根据权利要求2所述的半导体器件，
其中掺入所述第二导电膜的元素不同于掺入所述第一导电膜的元素。
6.根据权利要求2所述的半导体器件，
其中所述半导体衬底包括形成于其上的二极管，
其中所述半导体衬底的设置有所述二极管的表面与所述第一导电膜直接接触，并且
其中所述半导体衬底的表面上的晶体表面和所述第一导电膜的表面上的晶体表面是(001)表面。
7.根据权利要求2所述的半导体器件，
其中所述第二导电膜的表面上的(111)表面的面积比大于所述第一导电膜的表面上的(111)表面的面积比。
8.根据权利要求7所述的半导体器件，
其中所述半导体衬底包括形成于其上的功率MOSFET，并且
其中所述功率MOSFET的源电极包括所述第一导电膜和所述第二导电膜。
9.一种制造半导体器件的方法，包括以下步骤：
(a)通过溅射在半导体衬底之上形成第一导电膜；
(b)通过溅射在所述第一导电膜之上形成第二导电膜；
(c)通过图案化所述第一导电膜和所述第二导电膜来提供焊盘电极；以及
(d)通过化学镀在所述焊盘电极之上形成用于耦合至外部连接端子的镀膜，
其中所述第一导电膜和所述第二导电膜中的每一个均包括主要包含铝的膜，并且
其中所述第二导电膜的表面上的晶体表面不同于所述第一导电膜的表面上的晶体表面。
10.根据权利要求9所述的制造半导体器件的方法，
其中所述第二导电膜与所述镀膜直接接触，并且
其中所述第二导电膜的表面上的晶体表面是(111)表面。
11.根据权利要求10所述的制造半导体器件的方法，还包括以下步骤：
(e)通过将所述第一导电膜的表面暴露给氧气氛围，在步骤(a)和(b)之间在所述第一导电膜之上形成第一绝缘膜。
12.根据权利要求11所述的制造半导体器件的方法，
其中通过从溅射设备中取出所述半导体衬底、并且将所述半导体衬底暴露给氛围气体来执行步骤(e)。
13.根据权利要求11所述的制造半导体器件的方法，
其中通过将氧气引入溅射设备、而不从步骤(a)中使用的所述溅射设备中取出所述半导体衬底来执行步骤(e)，并且
其中在步骤(e)之后，不从所述溅射设备中取出所述半导体衬底来执行步骤(b)。
14.根据权利要求11所述的制造半导体器件的方法，还包括以下步骤：
(f)在步骤(a)和(b)之间，通过溅射或CVD在所述第一导电膜之上形成非晶膜。
15.根据权利要求10所述的制造半导体器件的方法，
其中掺入所述第二导电膜的元素不同于掺入所述第一导电膜的元素。
16.根据权利要求10所述的制造半导体器件的方法，
其中所述半导体衬底包括形成于其上的二极管，
其中在步骤(a)之前，在所述半导体衬底的其上形成有所述二极管的表面上执行清洁处理，
其中在步骤(a)，所述第一导电膜被形成为与所述半导体衬底的表面直接接触，并且
其中所述半导体衬底的表面上的晶体表面和所述第一导电膜的表面上的晶体表面是(001)表面。
17.根据权利要求10所述的制造半导体器件的方法，
其中用于形成所述第一导电膜的温度高于用于形成所述第二导电膜的温度，并且
其中所述第二导电膜的表面上的(111)表面的面积比大于所述第一导电膜的表面上的(111)表面的面积比。
18.根据权利要求17所述的制造半导体器件的方法，
其中所述半导体衬底包括形成于其上的功率MOSFET，并且
其中所述功率MOSFET的源电极包括所述第一导电膜和所述第二导电膜。
19.根据权利要求10所述的制造半导体器件的方法，
其中在步骤(c)和(d)之间执行两次锌酸盐处理。
20.根据权利要求19所述的制造半导体器件的方法，
其中所述镀膜主要包含镍。
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Application publication date: 20190305