CN109427682B - 半导体元件及其形成方法 - Google Patents

半导体元件及其形成方法 Download PDF

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CN109427682B
CN109427682B CN201711105357.6A CN201711105357A CN109427682B CN 109427682 B CN109427682 B CN 109427682B CN 201711105357 A CN201711105357 A CN 201711105357A CN 109427682 B CN109427682 B CN 109427682B
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dielectric layer
forming
fluorine
gate structure
dielectric
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CN109427682A (zh
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翁桐敏
吴宗翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体元件及其形成方法。半导体元件的形成方法包含：形成至少一栅极结构于基材上。栅极结构包含栅电极。栅极结构的栅电极包含第一导电材料；以及沿着栅极结构的栅极结构的侧壁而形成第一介电材料的第一介电层。第一介电材料的第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅或氟掺杂碳氧化硅。

Description

半导体元件及其形成方法
技术领域
本揭露是关于一种半导体元件，特别是关于一种半导体元件的形成方法。
背景技术
本揭示案是关于半导体元件及其制造方法。更特定而言，本揭示标的是关于用于半导体元件元件之的制造方法，此方法包含邻近于栅极结构形成介电层以及后续所形成的元件。
随着互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)元件缩小至更小尺寸，正在考虑新材料及概念以满足进阶效能目标。CMOS技术包含N型金属氧化物半导体(N-type metal oxide semiconductor,NMOS)及P型金属氧化物半导体(P-type metal oxide semiconductor,PMOS)。例如，金氧氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)为用于放大或切换电子信号的晶体管。N型金属氧化物半导体、P型金属氧化物半导体、金氧氧化物半导体场效应电晶、及各种其他元件的一个效能标准为元件切换频率。接触到晶体管的栅电极，及源极及漏极区两者。
诸如氧化物侧壁的薄介电层有时设置在栅电极与层间介电(interlayerdielectric；ILD)层之间。然而，氧化物侧壁的介电常数(dielectric constant,k)值一般为固定的且一旦形成不能改变。
发明内容
依据本揭露的一些实施方式，半导体元件的形成方法包含：形成至少一栅极结构于基材上。栅极结构包含栅电极。栅极结构的栅电极包含第一导电材料；以及沿着栅极结构的栅极结构的侧壁而形成第一介电材料的第一介电层。第一介电材料的第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅(fluorine doped silicon oxycarbonitride)或氟掺杂碳氧化硅(fluorine doped silicon oxycarbide)。
依据本揭露的另一些实施方式，半导体元件的形成方法包含：形成至少一栅极结构于基材上。栅极结构包含栅电极。栅电极包含第一导电材料；沿着栅极结构的侧壁形成第一介电层。第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅(fluorine dopedsilicon oxycarbonitride)；以及形成第二介电层。第二介电层包含氮化硅，横跨于第一介电层上，且接触第一介电层。
依据本揭露的再一些实施方式，半导体元件包含至少一栅极结构以及第一介电层。栅极结构于基材上方包含栅电极。栅电极包含导电材料。第一介电层沿着栅极结构的一或多个侧壁设置。第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅(fluorinedoped silicon oxycarbonitride)或氟掺杂碳氧化硅(fluorine doped siliconoxycarbide)。
附图说明
当结合附图阅读时，自以下详细描述很好地理解本揭示案的态样。应当注意，依据工业中标准实务，各特征未按比例绘制。事实上，为论述清楚，各特征的大小可任意地增加或缩小。在整个说明书和附图中，相同元件符号表示相同特征。
图1A绘示依据一些实施例的用于形成半导体元件的示范性方法的流程图；
图1B绘示依据一些实施例的用于形成第一介电层的示范性方法的流程图；
图2绘示在制造期间的示范性元件的部分的立体图，其中至少一个栅极结构依据一些实施例设置在基材上方；
图3绘示在第一介电层的基底层在图2的示范性元件上方形成之后的元件结构的立体图；
图4绘示依据一些实施例的经由分子离子植入使用前驱物组合物在图3的示范性元件中掺杂基底层的步骤；
图5绘示在第一介电层在图2的示范性元件上方形成之后的元件结构的立体图；
图6绘示在第二介电层在图5的示范性元件上方形成之后的元件结构；
图7绘示在一些实施例中的源极/漏极(source/drain；S/D)区域在图6的示范性元件的鳍片中形成之后的元件结构；
图8绘示依据一些实施例的在栅电极中的第一导电材料(例如，多晶硅(polysilicon))替换为第二导电材料(例如，金属)之后的图7的示范性元件的结构；
图9为绘示一些实施例的包含层间介电(interlayer dielectric；ILD)层的产生的示范性元件的立体图。
具体实施方式
应理解，以下揭示案提供许多不同实施例或例子，为实现本揭露的不同的特征。下文描述的组件及排列的特定的实例为了简化本揭示案。当然，此等仅仅为实例且不意指限制。举例而言，在随后描述中在第二特征上方或在第二特征上第一特征的形成可包含第一及第二特征形成为直接接触的实施例，以及亦可包含额外特征可形成在第一及第二特征之间，使得第一及第二特征可不直接接触的实施例。另外，本揭示案在各实例中可重复元件符号及/或字母。此重复为出于简易及清楚的目的，且本身不指示所论述各实施例及/或结构之间的关系。
另外，空间相对术语，诸如“在...之下”、“低于”、“下部”、“高于”、“上部”等，可在本文用以便于描述，以描述如在附图中绘示的一个元件或特征相对另一元件或特征的关系。除图形中描绘的方向外，空间相对术语意图是包含元件在使用或操作中的不同的方向。设备可为不同的朝向(旋转90度或在其他的方向)及在此使用的空间相对描述词可因此同样地解释。
在本揭示案中，单数形式“一”、“一”及“此”包含复数引用，以及对特定数值的引用包含至少特定数值，除非上下文另外明确指出。因此，例如，“纳米结构”的引用为对这种结构的一或多个及被彼等技术人员熟知的等同物的引用。当值通过使用前述“约”而表示为近似值时，应理解，特定值形成另一实施例。如本文使用，“约X”(其中X为数值)优选地指叙述值的±10％(包含首尾)。例如，短语“约8”优选地指7.2至8.8(包含首尾)的数值；作为另一实例，短语“约8％”优选地(但不总是)指7.2％至8.8％(包含首尾)的数值。如若存在，包含所有的范围且可将其组合使用。例如，当叙述“1至5”的范围时，叙述范围应看作包含范围“1至4”、“1至3”、“1-2”、“1-2及4-5”、“1-3及5”、“2-5”及其类似项。另外，当正面提供另一列表时，这种列表可解释为意谓可以排除任意替代者，例如通过权利要求中的负限制。例如，当叙述“1至5”的范围时，叙述范围可以看作为包含负排除1、2、3、4或5的任一个的情况；因此，“1至5”的叙述可以看作“1及3-5，但没有2”，或简单地“其中2不包含在内”。意欲本文中正面叙述的任何元件、元素、属性或步骤可以在请求项中被明确排除，无论这些元件、元素、属性或步骤是否被列为备选项，或者是否被隔离列出。
随着半导体元件的尺寸继续减小及包装密度继续增大，寄生电容变得愈来愈重要以提高元件(例如，晶体管)的工作速度。例如，晶体管的栅极结构包含邻近于栅极结构放置的一或多个侧壁。在一些实施例中，侧壁间隔物由氮化硅组成，其具有例如约7-8的相对较高介电常数值(即，高k值)。由于晶体管结构，高介电常数氮化硅间隔物通常趋向于增大栅电极与晶体管的源极/漏极区上的自偶遇接触之间的寄生电容，其减小晶体管的切换速度。需要低介电常数介电材料(例如，k<6)制造侧壁间隔物以改良晶体管效能。
为减少电阻-电容(resistance-capacitance；RC)延迟及增强轮廓控制，氧化硅置换为氮碳氧化硅(例如，silicon oxycarbonitride(SiOCN))作为层间介电质(interlayerdielectric,ILD)。氮碳氧化硅具有比氧化硅(silicon oxide)高的介电常数。例如，在一些实施例中，氧化硅具有约4.0的介电常数，而氮碳氧化硅具有约5的介电常数值。氮碳氧化硅亦具有比二氧化硅(silicon dioxide)高的蚀刻速率。另一方面，诸如侧壁间隔物的介电材料的介电常数值一般为固定的且一旦形成不能改变。因此，当层间介电质包含氮碳氧化硅时，适宜低介电常数介电材料需要设置在栅极结构与层间介电质之间，以及具有可调整的介电常数的低介电常数介电材料对于提供设计及制造挠性更为理想。
本揭示案提供用于形成半导体元件及之方法及产生之半导体元件。方法包含以下步骤：经由分子离子植入(molecular-ion implantation)形成第一介电层以获得可调整的及低介电常数值。这种第一介电层设置在具有栅电极的栅极结构与层间介电层之间。
参考在图2至图9中描述的示范性结构来描述在图1A至图1B中描述的方法。除非另外明确指出，执行流程图中的方法的步骤的顺序仅为绘示之用，未固定且可以改变或切换。在图2至图9中，通过相同元件符号指示的相同项，及为简洁起见，上文参考上述图提供的结构的描述不再重复。
为了简洁起见，除非另外明确指出，下文对“氮碳氧化硅(siliconoxycarbonitride)”的引用将被理解为包含组合物，此组合物包含任何适宜比率的硅、氧、碳及氮。具有化学式，SiOCN，的组合物仅为一个示范性组合物。这种组合物在一些实施例中可以含有少量(例如，<5重量％)氢。
下文对“碳氧化硅(silicon oxycarbide)”的引用将被理解为包含组合物，此组合物包含任何适宜比率的硅、氧及碳。具有化学式，SiOC，的组合物仅为一个示范性组合物。这种组合物在一些实施例中可以含有少量(例如，<5重量％)氢。
下文对“氟掺杂碳氮氧化硅(fluorine doped silicon oxycarbonitride)”或“氟掺杂碳氧化硅(fluorine doped silicon oxycarbide)”的引用将分别被理解为包含碳氮氧化硅(silicon oxycarbonitride)或碳氧化硅(silicon oxycarbide)，其含有适量的氟，并且视情况含有少量(<5重量％，2重量％或1重量％)氢。在一些实施例中，氟掺杂氮碳氧化硅或氟掺杂碳氧化硅不包含氢。
除非另外明确指出，下文对“氮化硅(silicon nitride)”的引用将被理解为包含材料，此材料包含任何比率的硅与氮(例如，Si3N4)。多晶硅(polysilicon)、或多硅为多晶硅，其为高纯度、多晶形式的硅(polycrystalline silicon)。
请参照图1A，绘示用于制造半导体元件的示范性方法10。在步骤12处，包含栅电极106及/或栅电极108的至少一个栅极结构115及/或栅极结构117(图2)在基材102上方形成。栅电极106及/或栅电极108包含第一导电材料。请参照图2，在一些实施例中，半导体元件100的部分包含在半导体基材102以上形成的栅极结构115、栅极结构117。
基材102可为包含半导体材料的晶圆。基材102的适宜材料的实例包含但不限于硅、锗、化合物半导体、及半导体绝缘体(semiconductor-on-insulator；SOI)基材。化合物半导体可为诸如砷化镓(gallium arsenide,GaAs)的III-V半导体化合物。半导体绝缘体基材可包含诸如玻璃的半导体绝缘体。
诸如浅沟槽隔离(shallow trench isolation；STI)区域104的隔离层或隔离结构在基材102以上形成。浅沟槽隔离区域104提供通过浅沟槽隔离区域104分隔的半导体区域的电绝缘。浅沟槽隔离区域104充满绝缘材料，其例如可为高密度等离子氧化物(highdensity plasma oxide；HDP)材料。
栅电极106或栅电极108包含第一导电(或半导体)材料。栅电极106及栅电极108可以包含同一材料。栅电极106或栅电极108的适宜材料的实例包含但不限于非晶硅、多晶硅、多晶硅/锗、或任何其他半导体材料，其可以视情况经掺杂。在一些实施例中栅电极106或栅电极108可以为半导体区域。在一些实施例中，栅电极106或栅电极108包含多晶硅或由多晶硅组成，并且在浅沟槽隔离区域104上或以上形成。包含多晶硅的这种栅电极在后续处理步骤之后替换为金属电极。在一些其他实施例中，栅电极106或栅电极108的第一导电材料包含金属。
如在图2中所示，栅极结构115及栅极结构117包含与栅电极106及栅电极108耦接的鳍片110，其可以包含多晶硅。具有鳍片110的这种栅极结构用于制造元件栅极。鳍片110可以包含诸如硅(例如，多晶硅)的半导体材料并转化为源极/漏极区。用于栅极结构115及栅极结构117的鳍片110可以相同，并掺杂有不同掺杂剂类型或浓度以在后续步骤处产生N型金属氧化物半导体晶体管或P型金属氧化物半导体晶体管。这些结构仅用以绘示。在一些实施例中，不具有鳍片的栅极结构115及栅极结构117可以用于制造虚设栅极，其可以包含电阻器-电容器(resistance-capacitance,RC)结构。在一些实施例中，诸如氮化硅层112及氧化硅层114的绝缘材料可以设置在栅电极106、栅电极108以上。
在图1A的步骤14处，第一介电材料的第一介电层122沿至少一个栅极结构115或栅极结构117的侧壁形成。第一介电材料的第一介电层122包含具有掺杂浓度的氟的氟掺杂氮碳氧化硅或氟掺杂碳氧化硅。
请参照图1B，在一些实施例中，形成第一介电材料的第一介电层122的步骤(即，步骤14)包含两个步骤。
在步骤24处，基底层120沿至少一个栅极结构115、栅极结构117的侧壁形成。基底层120可以在栅极结构115及栅极结构117上方，以及基材102上方形成。在图3中绘示产生的结构200。在一些实施例中基底层120包含氮碳氧化硅、碳氧化硅、类似物或任何其他适宜材料。基底层在一些实施例中由氮碳氧化硅(例如，SiOCN)组成。
请参照图3，在一些实施例中基底层120可以经由原子层沉积(atomic layerdeposition,ALD)制程或等离子增强化学气相沉积(plasma-enhanced chemical vapordeposition)制程来形成。厚度可以在埃(Angstrom)或若干纳米(nanometer)数量级。在一些实施例中，包含氮碳氧化硅(silicon oxycarbonitride)的基底层120可以使用含硅气体、含碳气体、含氮及含氧气体沉积。例如，适宜含硅气体的实例包含但不限于硅烷(silane)及四甲硅烷(tetramethyl silane)。适宜含碳气体的实例包含但不限于甲烷(methane)及C3H6气体。适宜含氮气体的实例包含但不限于NH3及氧化氮气体(nitrousoxide gas)。适宜含氧气体的实例包含但不限于O2气体。控制处理腔室中的压力或供气时间的处理条件等，可调整各别元素(即基底层120的硅元素、氧元素、碳元素及氮元素)的比率，即硅浓度、氧浓度、碳浓度及氮浓度以控制氮碳氧化硅膜的组合物比率。基底层120可以在从约100℃至约400℃的范围中的升高温度下生长。基底层120可以视情况包含少量氢。
在一些实施例中，可以首先形成碳氮化硅(例如，SiCN)的薄膜。作为基底层120的氮碳氧化硅薄膜可以通过用氧来氧化氮碳化硅的薄膜来形成。包含碳氧化硅(siliconoxycarbide)的基底层120可以使用如上所述的含硅气体、含碳气体及含氧气体沉积。
在步骤26处，经由分子离子植入(molecular ion implantation)使用包含含氟前驱物的前驱物组合物掺杂基底层120。图4绘示正在步骤26处处理的示范性元件300。在图5中绘示在步骤26之后的产生的元件结构400。基底层120转化为第一介电层122。掺杂剂离子的植入通过分子离子植入来进行。在一些实施例中，碳及氧可以植入有氟。
在一些实施例中，含氟前驱物包含氟化氢(hydrogen fluoride,HF)。前驱物组合物可以进一步包含诸如一氧化碳(CO)的含碳或氧前驱物。在一些实施例中，使用任何适宜配比的氟化氢(HF)与一氧化碳(CO)的混合物。在一些实施例中，HF:CO(或HF+:CO+)的体积比例或莫耳比例在从约1:5至5:1，例如约1:1的范围中。HF:CO的比率可通过调整两种气体的流动速率而调整。例如，在从0.2至1sccm(例如，0.5-0.7sccm)的范围中的相同流量范围用以获得1:1的HF:CO比率。反应温度可以在从约0℃至约100℃，例如，从约0℃至约50℃的范围中。用于生成分子离子的能量可以在从0.5KeV至约100KeV，例如，从10KeV至约60KeV的范围中。
在步骤26处，包含氮碳氧化硅(例如，SiOCN)、碳氧化硅(例如，SiOC)的基底层120掺杂有氟。产生的第一介电层122包含氟掺杂氮碳氧化硅(例如，fluorine doped siliconoxycarbonitride,F-SiOCN)、或氟掺杂碳氧化硅(例如，fluorine doped siliconoxycarbide,F-SiOC)。在一些实施例中，存在少量氢，例如，氟掺杂氢氮碳氧化硅(F-SiOCNH)、或氟掺杂氢碳氧化硅(F-SiOCH)。在一些实施例中，在第一介电层122中不存在氢。
步骤26亦可包含调整诸如氟化氢(HF)的含氟前驱物的含量的步骤。经由掺杂浓度的氟调整第一介电层122的介电常数。在一些实施例中，第一介电层中的氟的掺杂浓度在从约1x103至约1x106原子/cm3的范围中。第一介电层的介电常数在从约2至约3的范围中(例如，在从约2.3至约2.8，或从约2.4至约2.6的范围中)。在一些实施例中，第一介电层122的介电常数可通过调整含氟前驱物的含量(由此在第一介电层122掺杂氟的浓度)而符合预定水准或数值。氮碳氧化硅可以具有在从约4至约6(例如，约5)的范围中的介电常数。当氮碳氧化硅(silicon oxycarbonitride)掺杂有氟时，在一些实施例中介电常数减少了至少50％。
回看图1A，在步骤16处，形成横跨第一介电层122并与第一介电层122接触的第二介电材料的第二介电层130。第二介电层130可以在示范性元件400上方形成。在图6中绘示产生的元件结构500。
第二介电材料包含诸如氮化硅的适宜材料，其可以使用原子层沉积(atomiclayer deposition,ALD)制程形成。包含氮化硅(silicon nitride)的第二介电层130可以具有在从约6至8(例如，7-8)的范围中的介电常数。
方法10亦可包含在基材102上或以上形成半导体元件的其他部分(未绘示)的步骤。例如，其他部分可包含缓冲层、通道层、源极区及漏极区的一或多个。方法可包含原位掺杂以在基材102的表面中形成源极区及漏极区。例如，鳍片110可以包含诸如硅的半导体材料并转化为源极/漏极区150、152、154及156。在图7中绘示产生的元件结构600。鳍片110可以被蚀刻，以及源极/漏极区150、152、154及156经磊晶生长及原位或后续掺杂而形成。源极/漏极区150及152可以形成至少一个N型金属氧化物半导体晶体管，而源极/漏极区154及156可以形成至少一个P型金属氧化物半导体晶体管，反的亦然。包含诸如氮化硅或氧化硅的材料的介电层131在源极/漏极区150、152、154及156上方形成。在一些实施例中通道层(未绘示)设置在源极及漏极区与整个栅电极106及栅电极108之间。请参照图7，在一些实施例中，可以蚀刻去除设置在层114上方的第二介电层130的顶端部分。
方法10亦可包含可选择的步骤18。在步骤18处，栅电极106及栅电极108中的第一导电材料替换为包含至少一个金属的第二导电材料以形成金属栅电极166及金属栅电极168。在图8中绘示产生的示范性元件结构700。
在一些实施例中，栅电极106或栅电极108中的第一导电材料包含多晶硅。这种多晶硅栅电极可以替换为包含至少一种金属的第二导电材料以形成金属栅极。在步骤18处，层间介电层可以首先在示范性元件600上方形成。诸如层112及层114的绝缘材料、及栅电极106及栅电极108随后经蚀刻以形成沟槽，沟槽充满第二导电材料以形成金属栅电极166及金属栅电极168。包含氮化硅层112及氧化硅层114的绝缘材料可以设置在金属栅电极166及金属栅电极168以上。
金属栅电极166及金属栅电极168的适宜材料的实例包含但不限于钨(tungsten)、铝(aluminum)、铜(copper)、钛(titanium)、钽(tantalum)、钼(molybdenum)、铂(platinum)、氮化钽(tantalum nitride,TaN)、氮化钛(titanium nitride,TiN)、氮化钨(tungsten nitride,WN)、钛铝(titanium aluminum,TiAl)、氮化铝钛(titanium aluminumnitride,TiAlN)、TaCN、TaC、TaSiN、其他导电材料或前述材料的任意组合。在一些实施例中，金属栅电极166及金属栅电极168由钨组成。
除了金属栅电极166及金属栅电极168，在金属栅电极166及金属栅电极168与第二介电层130或浅沟槽隔离区域104之间可以存在多个层。例如，金属栅极结构亦可包含诸如二氧化铪(hafnium oxide,HfO2)的高介电常数介电质、诸如氮化钛(titanium nitride)的功函数材料层。包含金属栅电极166及金属栅电极168的金属栅极当与鳍片耦接时为元件栅极，此鳍片具有源极/漏极区150、152、154及156的任一个。在一些其他实施例中，金属栅极可以为提供电阻-电容结构的虚设栅极。多层结构及电阻-电容结构在共同申请案、在2017年5月26日提交的第62/511,373号美国临时专利申请案中描述，其内容以引用的方式全部并入本文。
在步骤20处，形成横跨第二介电层130并与第二介电层130接触的层间介电层170。层间介电层170可以在示范性元件结构700上方形成。在图9中绘示产生的示范性元件800。第一介电层122及第二介电层130在栅电极166或栅电极168与层间介电质之间充当间隔物。层间介电层170的适宜材料的实例包含但不限于氮碳氧化硅(silicon oxycarbonitride)、氧化硅(silicon oxide)、氮氧化硅(silicon oxynitride)、磷硅玻璃(phosphosilicateglass；PSG)、硼磷硅玻璃(borophosphosilicate glass；BPSG)、前述材料的任意组合、或其适宜材料。层间介电层170可通过使用化学气相沉积(chemical vapor deposition,CVD)制程、高密度等离子化学气相沉积(high density plasma CVD)制程、旋涂(spin-on)制程、溅射(sputtering)制程或其他适宜方法而形成。在一些实施例中层间介电层170包含诸如氮碳氧化硅(silicon oxycarbonitride)的适宜材料。包含氮碳氧化硅(siliconoxycarbonitride)的层间介电层可以具有在从约4至约6(例如，约5)的范围中的介电常数。
请参照图9，示范性半导体元件800包含至少一个栅极结构165或栅极结构167，此至少一个栅极结构165或栅极结构167包含在基材102上方的栅电极166或栅电极168，及沿至少一个栅极结构165或栅极结构167的一或多个侧壁设置的第一介电层122。栅电极166或栅电极168包含导电材料。第一介电层122包含具有掺杂浓度的氟的氟掺杂氮碳氧化硅或碳氧化硅。在一些实施例中，氟的掺杂浓度在从约1x103至约1x106原子/cm3的范围中。第一介电层122具有在从约2至约3的范围中(例如，在从约2.3至约2.8，或从约2.4至约2.6的范围中)的介电常数。
示范性元件800可以进一步包含横跨第一介电层122并与第一介电层122接触的第二介电层130，及横跨第二介电层130并与第二介电层130接触的层间介电层170。在一些实施例中，第二介电材料130包含氮化硅，以及层间介电层170包含氮碳氧化硅(siliconoxycarbonitrid)。在一些实施例中，栅电极165或栅电极167包含多晶硅或金属。栅极结构165或栅极结构167可以在一些实施例中为元件栅极或在一些其他实施例中为虚设栅极。虚设栅极可以包含电阻器-电容器结构。
本揭示案提供用于形成半导体元件的方法及产生的半导体元件。这种方法包含以下步骤：在基材上方形成包含栅电极的至少一个栅极结构，以及沿此至少一个栅极结构的侧壁形成第一介电材料的第一介电层。栅电极包含第一导电材料。第一介电材料的第一介电层包含具有掺杂浓度的氟的氟掺杂氮碳氧化硅或碳氧化硅。
在一些实施例中，形成第一介电材料的第一介电层的步骤包含：沿至少一个栅极结构的侧壁形成包含氮碳氧化硅或碳氧化硅的基底层，以及经由分子离子植入使用包含含氟前驱物的前驱物组合物掺杂基底层。基底层可以使用原子层沉积制程形成。在一些实施例中，含氟前驱物包含氟化氢(HF)。
经由掺杂浓度的氟调整第一介电层的介电常数。在一些实施例中，第一介电层中的氟的掺杂浓度在从约1x103至约1x106原子/cm3的范围中。第一介电层的介电常数在从约2至约3的范围中(例如，在从约2.3至约2.8，或从约2.4至约2.6的范围中)。
方法进一步包含形成第二介电材料的第二介电层，此第二介电材料的第二介电层横跨第一介电层并与第一介电层接触。方法进一步包含形成层间介电层，此层间介电层横跨第二介电层并与第二介电层接触。第二介电材料包含诸如氮化硅的适宜材料，其可以使用原子层沉积(atomic layer deposition；ALD)制程形成。在一些实施例中层间介电层包含诸如氮碳氧化硅的适宜材料。包含氮碳氧化硅的层间介电层可以具有在从约4至约6(例如，约5)的范围中的介电常数。包含氮化硅的第二介电层可以具有在从约6至8(例如，7-8)的范围中的介电常数。
在一些实施例中，栅电极中的第一导电材料包含多晶硅。栅电极中的第一导电材料可以替换为包含至少一种金属的第二导电材料。
本揭示案提供用于形成半导体元件的方法。这种方法包含以下步骤：在基材上方形成包含栅电极的至少一个栅极结构，沿至少一个栅极结构的侧壁形成第一介电层。栅电极包含第一导电材料，以及形成包含氮化硅的第二介电层，此第二介电层横跨第一介电层并与第一介电层接触。第一介电层包含具有掺杂浓度的氟的氟掺杂氮碳氧化硅。在一些实施例中，形成第一介电材料的第一介电层的步骤包含：沿至少一个栅极结构的侧壁形成包含氮碳氧化硅的基底层，以及经由分子离子植入使用包含氟化氢(HF)的前驱物组合物掺杂基底层。前驱物组合物可以进一步包含诸如一氧化碳(CO)的含碳或氧前驱物。在一些实施例中，HF:CO(或HF+:CO+)的比率为1:1。在一些实施例中，这种方法进一步包含在形成横跨第二介电层并与第二介电层接触的层间介电层，以及使用包含至少一种金属的第二导电材料替换栅电极中的第一导电材料。在一些实施例中层间介电层包含氮碳氧化硅。
在另一态样中，本揭示案提供半导体元件。这种元件包含至少一个栅极结构，此至少一个栅极结构在基材上方包含栅电极，及第一介电层，此第一介电层沿至少一个栅极结构的一或多个侧壁设置。栅电极包含导电材料。第一介电层包含具有掺杂浓度的氟的氟掺杂氮碳氧化硅或碳氧化硅。在一些实施例中，氟的掺杂浓度在从约1x103至约1x106原子/cm3的范围中。第一介电层具有在从约2至约3的范围中(例如，在从约2.3至约2.8，或从约2.4至约2.6的范围中)的介电常数。
装置可以进一步包含横跨第一介电层并与第一介电层接触的第二介电层，及横跨第二介电层并与第二介电层接触的层间介电层。在一些实施例中，第二介电材料包含氮化硅，以及层间介电层包含氮碳氧化硅。在一些实施例中，栅电极包含多晶硅或金属。栅极结构可以在一些实施例中为元件栅极或在一些其他实施例中为虚设栅极。虚设栅极可以包含电阻器-电容器结构。
依据本揭露的一些实施方式，半导体元件的形成方法，其特征在于，包含：形成至少一栅极结构于基材上。栅极结构包含栅电极。栅极结构的栅电极包含第一导电材料；以及沿着栅极结构的栅极结构的侧壁而形成第一介电材料的第一介电层。第一介电材料的第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅(fluorine doped siliconoxycarbonitride)或氟掺杂碳氧化硅(fluorine doped silicon oxycarbide)。
于本揭露的一或多个实施方式中，其特征在于，前述的栅电极中的第一导电材料包含多晶硅。
于本揭露的一或多个实施方式中，其特征在于，前述的形成第一介电层包含：沿着至少一栅极结构的侧壁而形成基底层。基底层包含氮碳氧化硅(siliconoxycarbonitride)或碳氧化硅(silicon oxycarbide)；以及透过分子离子植入而使用前驱物组合物而掺杂基底层。前驱物组合物包含含氟前驱物。
于本揭露的一或多个实施方式中，其特征在于，前述的含氟前驱物包含氟化氢(hydrogen fluoride,HF)。
于本揭露的一或多个实施方式中，其特征在于，前述的第一介电层中的氟的掺杂浓度介于约1x103原子/cm3与约1x106原子/cm3之间。
于本揭露的一或多个实施方式中，其特征在于，前述的第一介电层具有介电常数，且透过氟的掺杂浓度调整第一介电层的介电常数。
于本揭露的一或多个实施方式中，其特征在于，前述的第一介电层的介电常数介于约2与约3之间。
于本揭露的一或多个实施方式中，其特征在于，前述的半导体元件的形成方法，还包含：形成第二介电材料的第二介电层。第二介电层横跨于第一介电层上，并接触第一介电层。
于本揭露的一或多个实施方式中，其特征在于，前述的半导体元件的形成方法，还包含：形成层间介电层。层间介电层横跨于第二介电层上，并接触第二介电层。
于本揭露的一或多个实施方式中，其特征在于，前述的第二介电材料包含氮化硅(silicon nitride)，且层间介电层包含氮碳氧化硅(silicon oxycarbonitride)。
于本揭露的一或多个实施方式中，其特征在于，前述的半导体元件的形成方法，还包含：通过一第二导电材料替换栅电极中的第一导电材料。第二导电材料包含至少一金属。
依据本揭露的另一些实施方式，其特征在于，半导体元件的形成方法包含：形成至少一栅极结构于基材上。栅极结构包含栅电极。栅电极包含第一导电材料；沿着栅极结构的侧壁形成第一介电层。第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅(fluorine doped silicon oxycarbonitride)；以及形成第二介电层。第二介电层包含氮化硅(silicon nitride)，横跨于第一介电层上，且接触第一介电层。
于本揭露的一或多个实施方式中，其特征在于，前述的形成第一介电材料的第一介电层包含：沿着至少一栅极结构的侧壁而形成基底层。基底层包含氮碳氧化硅(siliconoxycarbonitride)；以及透过分子离子植入使用包含氟化氢(hydrogen fluoride,HF)的前驱物组合物而掺杂基底层。
于本揭露的一或多个实施方式中，其特征在于，前述的前驱物组合物还包含氧化碳(carbon monoxide,CO)。
于本揭露的一或多个实施方式中，其特征在于，前述的半导体元件的形成方法，还包含：形成层间介电层。层间介电层横跨于第二介电层上，接触第二介电层，且包含氮碳氧化硅(silicon oxycarbonitride)；以及通过第二导电材料替换栅电极中的第一导电材料。第二导电材料包含至少一金属。
依据本揭露的再一些实施方式，其特征在于，半导体元件包含至少一栅极结构以及第一介电层。栅极结构包含于基材上方包含栅电极。栅电极包含导电材料。第一介电层沿着栅极结构的一或多个侧壁设置。第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅(fluorine doped silicon oxycarbonitride)或氟掺杂碳氧化硅(fluorine dopedsilicon oxycarbide)。
于本揭露的一或多个实施方式中，其特征在于，前述的氟的掺杂浓度介于约1x103原子/cm3与约1x106原子/cm3之间，且第一介电层的介电常数介于约2与约3之间。
于本揭露的一或多个实施方式中，其特征在于，前述的半导体元件还包含第二介电层以及层间介电层。第二介电层横跨于第一介电层上，且接触第一介电层。层间介电层横跨于第二介电层上，并接触第二介电层。
于本揭露的一或多个实施方式中，其特征在于，前述的第二介电材料包含氮化硅(silicon nitride)，且层间介电层包含氮碳氧化硅(silicon oxycarbonitride)。
于本揭露的一或多个实施方式中，其特征在于，前述的栅电极包含多晶硅或金属。
上文概述若干实施例的特征，使得熟悉此项技术者可更好地理解本揭示案的态样。熟悉此项技术者应了解，可轻易使用本揭示案作为设计或修改其他制程及结构的基础，以便实施本文所介绍的实施例的相同目的及/或实现相同优势。熟悉此项技术者亦应认识到，此类等效结构并未脱离本揭示案的精神及范畴，且可在不脱离本揭示案的精神及范畴的情况下产生本文的各种变化、替代及更改。

Claims (24)

1.一种半导体元件的形成方法，其特征在于，包含：
形成至少一栅极结构于一基材上，该至少一栅极结构包含一栅电极，且该栅电极包含一第一导电材料；以及
沿着该至少一栅极结构的一侧壁而形成一第一介电材料的一第一介电层，该第一介电材料的该第一介电层包含具有一掺杂浓度的氟的一氟掺杂氮碳氧化硅或一氟掺杂碳氧化硅，
其中该形成该第一介电层包含：
沿着该至少一栅极结构的该侧壁而形成一基底层，该基底层包含氮碳氧化硅或碳氧化硅；以及
透过分子离子植入而使用氟化氢(hydrogen fluoride,HF)掺杂该基底层。
2.根据权利要求1所述的半导体元件的形成方法，其特征在于，该栅电极中的该第一导电材料包含多晶硅。
3.根据权利要求1所述的半导体元件的形成方法，其特征在于，该第一介电层中的氟的该掺杂浓度介于1x103原子/cm3与1x106原子/cm3之间。
4.根据权利要求1所述的半导体元件的形成方法，其特征在于，该第一介电层具有一介电常数，且透过氟的该掺杂浓度调整该第一介电层的该介电常数。
5.根据权利要求4所述的半导体元件的形成方法，其特征在于，该第一介电层的该介电常数介于2与3之间。
6.根据权利要求1所述的半导体元件的形成方法，其特征在于，还包含：
形成一第二介电材料的一第二介电层，该第二介电层横跨于该第一介电层上，并接触该第一介电层。
7.根据权利要求6所述的半导体元件的形成方法，其特征在于，还包含：
形成一层间介电层，该层间介电层横跨于该第二介电层上，并接触该第二介电层。
8.根据权利要求7所述的半导体元件的形成方法，其特征在于，该第二介电材料包含氮化硅(silicon nitride)，且该层间介电层包含氮碳氧化硅(silicon oxycarbonitride)。
9.根据权利要求1所述的半导体元件的形成方法，其特征在于，还包含：
通过一第二导电材料替换该栅电极中的该第一导电材料，该第二导电材料包含至少一金属。
10.根据权利要求1所述的半导体元件的形成方法，其特征在于，当形成该第一介电层时，将碳(carbon)与氧(oxygen)伴随着氟一起植入。
11.根据权利要求1所述的半导体元件的形成方法，其特征在于，该至少一栅极结构提供电阻-电容(resistor-capacitor,RC)结构的一虚设栅极，且具有包含至少一金属的一第二导电材料。
12.根据权利要求1所述的半导体元件的形成方法，其特征在于，透过分子离子植入而使用氟化氢掺杂该基底层的步骤是使用氟化氢和一氧化碳(carbon monoxide,CO)的一混合物掺杂该基底层，该混合物的HF：CO的摩尔比(molar ratio)为自1：5至5：1。
13.根据权利要求12所述的半导体元件的形成方法，其特征在于，HF和CO的该混合物被提供能量以形成包含多个分子离子的一混合物，且包含所述多个分子离子的该混合物包括HF+和CO+。
14.根据权利要求12所述的半导体元件的形成方法，其特征在于，该第一介电层接触该栅电极。
15.一种半导体元件的形成方法，其特征在于，包含：
形成至少一栅极结构于一基材上，该至少一栅极结构包含一栅电极，且该栅电极包含一第一导电材料；
沿着该至少一栅极结构的一侧壁形成一第一介电层，该第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅；以及
形成一第二介电层，该第二介电层包含氮化硅，横跨于该第一介电层上，且接触该第一介电层，
其中该形成该第一介电层包含：
沿着该至少一栅极结构的该侧壁而形成一基底层，该基底层包含氮碳氧化硅；以及
透过分子离子植入而使用氟化氢掺杂该基底层。
16.根据权利要求15所述的半导体元件的形成方法，其特征在于，透过分子离子植入而使用氟化氢掺杂该基底层的步骤是使用氟化氢和一氧化碳(carbon monoxide,CO)掺杂该基底层。
17.根据权利要求15所述的半导体元件的形成方法，其特征在于，还包含：
形成一层间介电层，该层间介电层横跨于该第二介电层上，接触该第二介电层，且包含氮碳氧化硅(silicon oxycarbonitride)；以及
通过一第二导电材料替换该栅电极中的该第一导电材料，该第二导电材料包含至少一金属。
18.一种半导体元件，其特征在于，包含：
至少一栅极结构，于一基材上方包含一栅电极，该栅电极包含一导电材料；以及
一第一介电层，沿着该至少一栅极结构的一或多个侧壁设置，该第一介电层包含具有一掺杂浓度的氟的氟掺杂氮碳氧化硅或氟掺杂碳氧化硅。
19.根据权利要求18所述的半导体元件，其特征在于，氟的该掺杂浓度介于1x103原子/cm3与1x106原子/cm3之间，且该第一介电层的一介电常数介于2与3之间。
20.根据权利要求18所述的半导体元件，其特征在于，还包含：
一第二介电层，横跨于该第一介电层上，且接触该第一介电层；以及
一层间介电层，横跨于该第二介电层上，并接触该第二介电层。
21.根据权利要求20所述的半导体元件，其特征在于，该第二介电材料包含氮化硅(silicon nitride)，且该层间介电层包含氮碳氧化硅(silicon oxycarbonitride)。
22.根据权利要求18所述的半导体元件，其特征在于，该栅电极包含多晶硅或金属。
23.一种半导体元件的形成方法，其特征在于，包含：
形成至少一栅极结构于一基材上，该至少一栅极结构包含一栅电极，且该栅电极包含一第一导电材料；
沿着该至少一栅极结构的一侧壁而形成一第一介电层，该第一介电层的包含具有一掺杂浓度的氟的一氟掺杂氮碳氧化硅；以及
形成包含氮化硅(silicon nitride)的一第二介电层，其中该第二介电层横向地位于该第一介电层上方，且接触该第一介电层，
其中该形成包含一第一介电材料的该第一介电层，包含：
沿着该至少一栅极结构的该侧壁而形成一基底层，该基底层包含氮碳氧化硅；以及
透过分子离子植入而使用一前驱物组合物而掺杂该基底层，该前驱物组合物包含一混合物，该混合物包含属于HF+和CO+的多个分子离子。
24.根据权利要求23所述的半导体元件的形成方法，其特征在于，该混合物的HF+和CO+的比为1：1。
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