CN109408276A - 一种纠正码中规律交错器低延迟平行化架构位址绕线机制 - Google Patents

一种纠正码中规律交错器低延迟平行化架构位址绕线机制 Download PDF

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Publication number
CN109408276A
CN109408276A CN201811253539.2A CN201811253539A CN109408276A CN 109408276 A CN109408276 A CN 109408276A CN 201811253539 A CN201811253539 A CN 201811253539A CN 109408276 A CN109408276 A CN 109408276A
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CN
China
Prior art keywords
address
data
parallelization
framework
cable winding
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Pending
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CN201811253539.2A
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English (en)
Chinese (zh)
Inventor
郭书玮
李庭育
陈育鸣
魏智汎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Hua Cun Electronic Technology Co Ltd
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Jiangsu Hua Cun Electronic Technology Co Ltd
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Application filed by Jiangsu Hua Cun Electronic Technology Co Ltd filed Critical Jiangsu Hua Cun Electronic Technology Co Ltd
Priority to CN201811253539.2A priority Critical patent/CN109408276A/zh
Priority to PCT/CN2018/115511 priority patent/WO2020082450A1/fr
Publication of CN109408276A publication Critical patent/CN109408276A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
CN201811253539.2A 2018-10-25 2018-10-25 一种纠正码中规律交错器低延迟平行化架构位址绕线机制 Pending CN109408276A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201811253539.2A CN109408276A (zh) 2018-10-25 2018-10-25 一种纠正码中规律交错器低延迟平行化架构位址绕线机制
PCT/CN2018/115511 WO2020082450A1 (fr) 2018-10-25 2018-11-14 Mécanisme de circonvolution d'adresse d'architecture de parallélisation à faible retard pour entrelaceur régulier dans un code de correction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811253539.2A CN109408276A (zh) 2018-10-25 2018-10-25 一种纠正码中规律交错器低延迟平行化架构位址绕线机制

Publications (1)

Publication Number Publication Date
CN109408276A true CN109408276A (zh) 2019-03-01

Family

ID=65470011

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811253539.2A Pending CN109408276A (zh) 2018-10-25 2018-10-25 一种纠正码中规律交错器低延迟平行化架构位址绕线机制

Country Status (2)

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CN (1) CN109408276A (fr)
WO (1) WO2020082450A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800525A (en) * 1984-10-31 1989-01-24 Texas Instruments Incorporated Dual ended folded bit line arrangement and addressing scheme
CN1053693A (zh) * 1990-01-16 1991-08-07 艾利森电话股份有限公司 信号处理装置的地址处理器
CN1335561A (zh) * 2000-06-30 2002-02-13 先进数字芯片股份有限公司 扩展指令字折叠设备
US6370076B1 (en) * 1999-05-28 2002-04-09 Stmicroelectronics S.R.L. Folded addressing method for memory architectures
CN102957993A (zh) * 2011-08-30 2013-03-06 中国科学院微电子研究所 低功耗wola滤波器组及其分析和综合阶段电路
CN103853522A (zh) * 2012-12-06 2014-06-11 辉达公司 折叠式fifo存储器生成器
CN104349260A (zh) * 2011-08-30 2015-02-11 中国科学院微电子研究所 低功耗wola滤波器组及其综合阶段电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4800525A (en) * 1984-10-31 1989-01-24 Texas Instruments Incorporated Dual ended folded bit line arrangement and addressing scheme
CN1053693A (zh) * 1990-01-16 1991-08-07 艾利森电话股份有限公司 信号处理装置的地址处理器
US6370076B1 (en) * 1999-05-28 2002-04-09 Stmicroelectronics S.R.L. Folded addressing method for memory architectures
CN1335561A (zh) * 2000-06-30 2002-02-13 先进数字芯片股份有限公司 扩展指令字折叠设备
CN102957993A (zh) * 2011-08-30 2013-03-06 中国科学院微电子研究所 低功耗wola滤波器组及其分析和综合阶段电路
CN104349260A (zh) * 2011-08-30 2015-02-11 中国科学院微电子研究所 低功耗wola滤波器组及其综合阶段电路
CN103853522A (zh) * 2012-12-06 2014-06-11 辉达公司 折叠式fifo存储器生成器

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WO2020082450A1 (fr) 2020-04-30

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Application publication date: 20190301