CN109408276A - Regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code - Google Patents
Regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code Download PDFInfo
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- CN109408276A CN109408276A CN201811253539.2A CN201811253539A CN109408276A CN 109408276 A CN109408276 A CN 109408276A CN 201811253539 A CN201811253539 A CN 201811253539A CN 109408276 A CN109408276 A CN 109408276A
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- address
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- cable winding
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
Abstract
The invention discloses interleaver low latency parallelization framework address cable winding mechanisms regular in a kind of correction code, comprising the following steps: A, according to the quantity of decoding processor and the data quantity of entrance derives corresponding initial address；B, plus folding memory address on parallelization framework；C, folding memory address selector sequence is distinguished；D, according to the staggeredly address of address generator institute output, data is sorted, according to the data quantity of the quantity of decoding processor and entrance, derive corresponding initial address, parallel plus folding memory address, it is distinguished simultaneously by selector sequence again, its delay time is fixed on three cycle periods, do not increase with decoding processor and promotes delay time, the present invention utilizes parallelization adder and selector framework, it provides a kind of parallel framework of fixed delay to interlock cable winding mechanism, avoids parallelization framework bring delay time.
Description
Technical field
The present invention relates to the high parallelization architecture technology fields for supporting regularization address interleaving device in error correcting code, specifically
For interleaver low latency parallelization framework address cable winding mechanism regular in a kind of correction code.
Background technique
Bit correcting code now, is aided with bit more and upsets system and increase its bit and correct ability, corresponds to gulping down now
The amount of spitting, framework adapts to bit mostly with enciphered data at the most decoding processors of parallelization to be upset the address of system and generates
Device quantity increases as processor increases, this is represented under the bit correcting code system of height parallelization framework, and address interlocks
The complexity of coiling is also increased accordingly also with raising, data processing delay time.
Encoder (encoder) be signal (such as bit stream) or data are worked out, be converted to can be used to communicate, transmission
With the equipment of the signal form of storage.
Decoder is a kind of device that information is restored to its original form from the form of coding.Losing coded data
When, staff can use decoder and restore initial setting up, also be easy to be utilized by criminal.
Summary of the invention
The purpose of the present invention is to provide a kind of using parallelization adder and selector framework, provides a kind of fixation and prolongs
Parallel framework interlocks cable winding mechanism late, avoids regular interleaver in a kind of correction code of parallelization framework bring delay time
Low latency parallelization framework address cable winding mechanism, to solve the problems mentioned in the above background technology.
To achieve the above object, the invention provides the following technical scheme: regular interleaver low latency is flat in a kind of correction code
Rowization framework address cable winding mechanism, the following steps are included:
A, according to the data quantity of the quantity of decoding processor and entrance, corresponding initial address is derived；
B, plus folding memory address on parallelization framework；
C, folding memory address selector sequence is distinguished；
D, according to the staggeredly address of address generator institute output, data is sorted.
It preferably, include relay, communication chip, fuse, transformer on the step A decoding processor.
Preferably, include the initial address of parallelization on the step B parallelization framework, fold memory address, staggeredly address,
Selector, circuit sectionalizer, the folding memory address on parallelization framework connects with selector respectively, while all folding memory positions
Location is serially connected.
Preferably, the C calculates the initial address of parallelization framework again while in advance by adder and selector, and adopts
Data is ranked up with circuit sectionalizer.
Preferably, the fixed delay time of the step C parallelization framework is three cycle periods.
Preferably, the step D is according to the staggeredly address of address generator institute output, by data a, data b, data c,
Data d is data b, data a, data c, data d after sequence.
Compared with prior art, the beneficial effects of the present invention are:
(1) according to the data quantity of the quantity of decoding processor and entrance, corresponding initial address is derived, parallel plus folding
Folded memory address, then distinguish simultaneously by selector sequence, delay time is fixed on three cycle periods, not with decoding at
Reason device increases and promotes delay time；
(2) present invention is using parallelization adder and selector framework, provides a kind of parallel framework of fixed delay and interlocks coiling
Mechanism avoids parallelization framework bring delay time.
Detailed description of the invention
Fig. 1 is that the present invention is that the data that a parallelization framework is four staggeredly handles schematic diagram of mechanism；
Fig. 2 is the old winding structure schematic diagram that interlocks in parallel of the present invention；
Fig. 3 is the winding structure schematic diagram that interlocks in parallel of fixed delay of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The present invention provides a kind of technical solution: regular interleaver low latency parallelization framework address coiling in a kind of correction code
Mechanism, it is characterised in that: the following steps are included:
A, according to the data quantity of the quantity of decoding processor and entrance, corresponding initial address is derived；
B, plus folding memory address on parallelization framework；
C, folding memory address selector sequence is distinguished；
D, according to the staggeredly address of address generator institute output, data is sorted.
According to the data quantity of the quantity of decoding processor and entrance, corresponding initial address, decoding processor are derived
Upper includes relay, communication chip, fuse, transformer.
Plus memory address is folded on parallelization framework, includes the initial address of parallelization on parallelization framework, fold
Remember address, staggeredly address, selector, circuit sectionalizer, the folding memory address on parallelization framework connect with selector respectively, together
The folding memory address of Shi Suoyou is serially connected.
It is distinguished to the sequence of memory address selector is folded, the initial address for calculating parallelization framework in advance passes through simultaneously again
Adder and selector, and be ranked up data using circuit sectionalizer, the fixed delay time of parallelization framework is three circulations
Period.
According to the staggeredly address of address generator institute output, by data a, data b, data c, data d is after sequence
For data b, data a, data c, data d.
It is staggeredly handled referring to Fig. 1,1: one parallelization framework of embodiment obtains data for four, processing data quantity is 6144
Member, parallelization framework are equipped with address generator 1, address generator 2, address generator 3, address generator 4, minimum selection
Device, memory body 1, memory body 2, memory body 3, memory body 4, in parallel staggeredly coiling, processor 1, processor 2, processor 3, processing
Device 4, the address generator 1, address generator 2, address generator 3, address generator 4 are connect with minimum selector respectively,
Minimum selector respectively with memory body 1, memory body 2, memory body 3, memory body 4 connect, the memory body 1, memory body 2, memory
Body 3, memory body 4 with it is parallel staggeredly coiling connection, in parallel staggeredly coiling respectively with processor 1, processor 2, processor 3, place
It manages device 4 to connect, the node that the address generator 4 connects between memory body 4 and parallel staggeredly coiling connects, address generator 3
The node connected between memory body 3 and parallel staggeredly coiling connects, address generator, and 2 connect memory bodys 2 and parallel staggeredly coiling
Between node connection, address generator, 1 connection memory body 1 and the parallel staggeredly node connection between coiling.
Referring to Fig. 2, embodiment 2: the old winding structure that interlocks in parallel according to memory body depth address and folds address
Corresponding address can be found out in sequence and compared with staggeredly address, staggered-sequence is indicated with 4Bit signal, it is old it is parallel staggeredly
Winding structure is equipped with selector a, selector b, selector c, selector d, and one end of selector is connect with staggeredly address, selects
Device a is selected, the other end of selector b, selector c, selector d are connect with circuit sectionalizer, selector a, selector b, selector c,
Third connection end on selector d is connect with folding memory address, input data a at circuit sectionalizer, data b, data c,
Data d, output sequence is data b, data a, data c, data d after circuit sectionalizer sorts.
Referring to Fig. 3, embodiment 3: at the beginning of the winding structure that interlocks in parallel that the present invention provides fixed delay is equipped with parallelization
Beginning address, folds memory address, staggeredly address, selector, circuit sectionalizer, the selector on parallelization framework respectively with parallelization
Initial address connection, selector are connect with circuit sectionalizer, input the data a of circuit sectionalizer, data b, data c, data d, by area
Dividing output sequence after device sequence is data b, data a, data c, data d, the coiling that interlocks in parallel of present invention offer fixed delay
Framework, the initial address for calculating parallelization framework in advance pass through adder and selector simultaneously again, are finally carried out again by circuit sectionalizer
Sequence, this framework fixed delay time are three cycle periods.
According to the data quantity of the quantity of decoding processor and entrance, corresponding initial address is derived, adding in parallel
Memory address is folded, then is distinguished simultaneously by selector sequence, delay time is fixed on three cycle periods, not with decoding
Processor increases and promotes delay time, and the present invention provides a kind of fixation and prolongs using parallelization adder and selector framework
Parallel framework interlocks cable winding mechanism late, avoids parallelization framework bring delay time.
The beneficial effects of the present invention are:
(1) according to the data quantity of the quantity of decoding processor and entrance, corresponding initial address is derived, parallel plus folding
Folded memory address, then distinguish simultaneously by selector sequence, delay time is fixed on three cycle periods, not with decoding at
Reason device increases and promotes delay time；
(2) present invention is using parallelization adder and selector framework, provides a kind of parallel framework of fixed delay and interlocks coiling
Mechanism avoids parallelization framework bring delay time.
It although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, can be with
A variety of variations, modification, replacement can be carried out to these embodiments without departing from the principles and spirit of the present invention by understanding
And modification, the scope of the present invention is defined by the appended.
Claims (6)
1. regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code, it is characterised in that: including following
Step:
A, according to the data quantity of the quantity of decoding processor and entrance, corresponding initial address is derived；
B, plus folding memory address on parallelization framework；
C, folding memory address selector sequence is distinguished；
D, according to the staggeredly address of address generator institute output, data is sorted.
2. regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code according to claim 1,
It is characterized by: including relay, communication chip, fuse, transformer on the step A decoding processor.
3. regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code according to claim 1,
It is characterized by: including the initial address of parallelization on the step B parallelization framework, memory address is folded, staggeredly address, selection
Device, circuit sectionalizer, the folding memory address on parallelization framework connects with selector respectively, while all folding memory address phases
Mutually series connection.
4. regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code according to claim 1,
It is characterized by: the C calculates the initial address of parallelization framework again while in advance by adder and selector, and use area
Device is divided to be ranked up data.
5. regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code according to claim 1,
It is characterized by: the fixed delay time of the step C parallelization framework is three cycle periods.
6. regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code according to claim 1,
It is characterized by: staggeredly address of the step D according to address generator institute output, by data a, data b, data c, money
Expect that d is data b, data a, data c, data d after sequence.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811253539.2A CN109408276A (en) | 2018-10-25 | 2018-10-25 | Regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code |
| PCT/CN2018/115511 WO2020082450A1 (en) | 2018-10-25 | 2018-11-14 | Low-delay parallelization architecture address winding mechanism for regular interleaver in correction code |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811253539.2A CN109408276A (en) | 2018-10-25 | 2018-10-25 | Regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code |
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| Publication Number | Publication Date |
|---|---|
| CN109408276A true CN109408276A (en) | 2019-03-01 |
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| CN201811253539.2A Pending CN109408276A (en) | 2018-10-25 | 2018-10-25 | Regular interleaver low latency parallelization framework address cable winding mechanism in a kind of correction code |
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| WO (1) | WO2020082450A1 (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4800525A (en) * | 1984-10-31 | 1989-01-24 | Texas Instruments Incorporated | Dual ended folded bit line arrangement and addressing scheme |
| CN1053693A (en) * | 1990-01-16 | 1991-08-07 | 艾利森电话股份有限公司 | The address processor of signal processing apparatus |
| CN1335561A (en) * | 2000-06-30 | 2002-02-13 | 先进数字芯片股份有限公司 | Extended instruction word folding equipment |
| US6370076B1 (en) * | 1999-05-28 | 2002-04-09 | Stmicroelectronics S.R.L. | Folded addressing method for memory architectures |
| CN102957993A (en) * | 2011-08-30 | 2013-03-06 | 中国科学院微电子研究所 | Low-power-consumption WOLA (Weighted Overlap-Add) filterbank and analyzing and integrating stage circuit |
| CN103853522A (en) * | 2012-12-06 | 2014-06-11 | 辉达公司 | Folded fifo memory generator |
| CN104349260A (en) * | 2011-08-30 | 2015-02-11 | 中国科学院微电子研究所 | Low-power-consumption WOLA (Weighted Overlap Add) filter set and comprehensive phase circuit thereof |
-
2018
- 2018-10-25 CN CN201811253539.2A patent/CN109408276A/en active Pending
- 2018-11-14 WO PCT/CN2018/115511 patent/WO2020082450A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4800525A (en) * | 1984-10-31 | 1989-01-24 | Texas Instruments Incorporated | Dual ended folded bit line arrangement and addressing scheme |
| CN1053693A (en) * | 1990-01-16 | 1991-08-07 | 艾利森电话股份有限公司 | The address processor of signal processing apparatus |
| US6370076B1 (en) * | 1999-05-28 | 2002-04-09 | Stmicroelectronics S.R.L. | Folded addressing method for memory architectures |
| CN1335561A (en) * | 2000-06-30 | 2002-02-13 | 先进数字芯片股份有限公司 | Extended instruction word folding equipment |
| CN102957993A (en) * | 2011-08-30 | 2013-03-06 | 中国科学院微电子研究所 | Low-power-consumption WOLA (Weighted Overlap-Add) filterbank and analyzing and integrating stage circuit |
| CN104349260A (en) * | 2011-08-30 | 2015-02-11 | 中国科学院微电子研究所 | Low-power-consumption WOLA (Weighted Overlap Add) filter set and comprehensive phase circuit thereof |
| CN103853522A (en) * | 2012-12-06 | 2014-06-11 | 辉达公司 | Folded fifo memory generator |
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| WO2020082450A1 (en) | 2020-04-30 |
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Application publication date: 20190301 |