CN102957433A - Rd+ based 8b/10b coding circuit - Google Patents

Rd+ based 8b/10b coding circuit Download PDF

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CN102957433A
CN102957433A CN2011102390465A CN201110239046A CN102957433A CN 102957433 A CN102957433 A CN 102957433A CN 2011102390465 A CN2011102390465 A CN 2011102390465A CN 201110239046 A CN201110239046 A CN 201110239046A CN 102957433 A CN102957433 A CN 102957433A
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coding
encoder
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左耀华
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Shanghai Huahong Integrated Circuit Co Ltd
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Shanghai Huahong Integrated Circuit Co Ltd
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Abstract

The invention discloses an rd+ based 8b/10b coding circuit which is composed of an rd+ based 5b/6b coder, an rd+ based 3b/4b coder, a 5b post-processing module, a 3b post-processing module, a data merging module and two xor modules. The rd+ based 5b/6b coder performs 5b/6b coding to data lower 5 bits, inputs the coded data lower 5 bits to the 5b post-processing module for processing and inputs the processes data lower 5 bits to the data merging module, and the rd+ based 3b/4b coder performs 3b/4b coding to data higher 3 bits, inputs the coded data higher 3 bits to the 3b post-processing module for processing and inputs the processed data higher 3 bits to the data merging module. The processing of the 5b post-processing module is controlled by first polarity change identifier signals and current character polarity signals, and the processing of the 3b post-processing module is controlled by second polarity change identifier signals and second character polarity signals. The rd+ based 8b/10b coding circuit can greatly save storage resources.

Description

8b/10b coding circuit based on rd+
Technical field
The present invention relates to a kind of coding circuit, relate in particular to a kind of 8b/10b coding circuit based on rd+.
Background technology
8b/10b, also be called 8 bits/10 bits, the encoding mechanism that present many high-speed serial bus adopts, such as the bus such as 1394b, Serial ATA, PCI Express, Infini-band, Fibre Channel (netted passage), RapidIO or network etc.
One of characteristic of 8b/10b coding is to guarantee the DC balance, adopt the 8b/10b coded system, can be so that " 0 " that sends, " 1 " quantity keep basically identical, continuous " 1 " or " 0 " is no more than 5, be to insert one " 0 " or " 1 " behind per 5 continuous " 1 " or " 0 ", thereby guarantee signal DC balance, it in other words, unlikely generations DC lacks of proper care when link is overtime.Encode by 8b/10b, can guarantee that the serial data that transmits can correctly be restored at receiving terminal, in addition, utilize some special codes (in the PCI-Express bus, being the K code), the work that can help receiving terminal to reduce, and can find in early days the error of transmission of data bit, suppress wrong the continuation and occur.8b/10b coding is that one group of 8 continuous bit data is resolved into two groups of data, one group 3, one group 5, through becoming respectively one group 4 data and one group 6 data behind the coding, sends thereby form one group 10 data.On the contrary, decoding is 1 group 10 input data to be passed through conversion obtain 8 bit data positions.Data value can be unified is expressed as DX.Y or KX.Y, and wherein D is expressed as data character, and K is expressed as control character, and X represents low 5 EDCBA of the initial data inputted, and Y represents high 3 HGF of the initial data inputted.
Existing 8b/10b coding circuit adopts the method for tabling look-up to realize the 8b/10b coding mostly, 8b/10b with data character is encoded to example, the register that it is 10 bits that existing 8b/10b coding circuit needs 512 width is stored related data, and the memory resource that takies is more.
Summary of the invention
Technical problem to be solved by this invention provides a kind of 8b/10b coding circuit based on rd+, can save in a large number memory resource.
For solving the problems of the technologies described above, the 8b/10b coding circuit based on rd+ provided by the invention is by merging module and two XOR module compositions based on the 5b/6b encoder of rd+, the 3b/4b encoder based on rd+, 5b post-processing module, 3b post-processing module, data.
Outer input data is 8 Bit datas, and this 8 Bit data is split as low 5 Bit datas and high 3 Bit datas, and described low 5 Bit datas are input to described 5b/6b encoder based on rd+, and described high 3 Bit datas are input to described 3b/4b encoder based on rd+.
One indicator signal, described indicator signal are input to respectively described 5b/6b encoder based on rd+ and described 3b/4b encoder based on rd+; Described indicator signal is used for controlling the coding of described 5b/6b encoder based on rd+ and described 3b/4b encoder based on rd+; The first coding data of output the first change in polarity indications signal and one 6 bits after described 5b/6b encoder encodes based on rd+ is finished; The second coded data of output the second change in polarity indications signal and one 4 bits after described 3b/4b encoder encodes based on rd+ is finished.
Described first coding data is input to described 5b post-processing module, and described 5b post-processing module is carried out reprocessing to described first coding data under the control of the current character polar signal of described the first change in polarity indications signal and outside input; The first rear coded data of output one 6 bits after described 5b post-processing module is processed.
Described the second coded data is input to described 3b post-processing module, and described 3b post-processing module is carried out reprocessing to described the second coded data under the control of described the second change in polarity indications signal and the second character polar signal; The second rear coded data of output one 4 bits after described 3b post-processing module is processed.
The described first rear coded data and the described second rear coded data all are sent to described data and merge the output data that module is carried out 10 bits after data merge processing and export a merging.
First XOR module is used for described the first change in polarity indications signal and described current character polar signal are carried out the XOR processing and produce described the second character polar signal; Second XOR module is used for that described the second change in polarity indications signal and described the second character polar signal are carried out XOR and processes and produce next character polar signal and described next character polar signal is externally exported.
Further improving is that described 5b/6b encoder based on rd+ is based on the 5b/6b encoder that the rd+ coding method realizes; Described 8 Bit datas that described indicator signal is used to refer to outside input are data character or control character, if described 8 Bit datas are data characters, described 5b/6b encoder based on rd+ carries out the 5b/6b coding according to the rd+ coding rule of data character; If described 8 Bit datas are control characters, then described 5b/6b encoder based on rd+ carries out the 5b/6b coding according to the rd+ coding rule of control character; Described the first change in polarity indications signal is used for representing that described 5b/6b encoder based on rd+ is in the change in polarity situation of cataloged procedure.
Further improving is that described 3b/4b encoder based on rd+ is based on the 3b/4b encoder that the rd+ coding method realizes; Described 8 Bit datas that described indicator signal is used to refer to outside input are data character or control character, if described 8 Bit datas are data characters, described 3b/4b encoder based on rd+ carries out the 3b/4b coding according to the rd+ coding rule of data character; If described 8 Bit datas are control characters, then described 3b/4b encoder based on rd+ carries out the 3b/4b coding according to the rd+ coding rule of control character; Described the second change in polarity indications signal is used for representing that described 3b/4b encoder based on rd+ is in the change in polarity situation of cataloged procedure.
Further improve and be, if the described polarity of 5b/6b encoder in cataloged procedure based on rd+ of described the first change in polarity indications signal indication changes and described current character polar signal when employed polarity is not identical in cataloged procedure with described 5b/6b encoder based on rd+, described 5b post-processing module is to all step-by-step negates of described first coding data and generate the described first rear coded data; Under other condition, described 5b post-processing module is not processed described first coding data, but directly the described first rear coded data is taken as described first coding data.
Further improve and be, if the described polarity of 3b/4b encoder in cataloged procedure based on rd+ of described the second change in polarity indications signal indication changes and described the second character polar signal when employed polarity is not identical in cataloged procedure with described 3b/4b encoder based on rd+, described 3b post-processing module is to all step-by-step negates of described the second coded data and generate the described second rear coded data; Under other condition, described 3b post-processing module is not processed described the second coded data, but directly the described second rear coded data is taken as described the second coded data.
Further improve and be, described data merge module will the described first rear coded data as hanging down 6, the described second rear coded data being merged the described output data of generation as high 4.
The present invention can save memory resource in a large number, 8b/10b with data character is encoded to example, the present invention only needs the register of 84 bits and 32 6 bits to store data, and shared storage resources only is 4.375% of existing 8b/10b coding circuit, and resource is saved the effect highly significant.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 embodiment of the invention is based on the 8b/10b coding circuit structure chart of rd+.
Embodiment
As shown in Figure 1, be that the embodiment of the invention is based on the 8b/10b coding circuit structure chart of rd+.The embodiment of the invention based on the 8b/10b coding circuit of rd+ by merging modules (data_merge) 105 based on the 5b/6b encoder (enc_5b_to_6b) 101 of rd+, the 3b/4b encoder (enc_3b_to_4b) 102 based on rd+, 5b post-processing module (post_5b) 103,3b post-processing module (post_3b) 104, data and first 106, second XOR modules of XOR module (xor1) (xor2) 107 consist of.
Described 5b/6b encoder 101 based on rd+ is based on the 5b/6b encoder that the rd+ coding method realizes; Described 3b/4b encoder 102 based on rd+ is based on the 3b/4b encoder that the rd+ coding method realizes.
Outer input data is 8 Bit datas, this 8 Bit data is split as low 5 Bit datas and high 3 Bit datas, described low 5 Bit datas are input to described 5b/6b encoder 101 based on rd+, and described high 3 Bit datas are input to described 3b/4b encoder 102 based on rd+.Described outer input data is that described 8 Bit datas comprise two kinds of data character and control characters, described outer input data is a data character in the present embodiment, and suppose that this data character is D23.3, described 8 Bit datas that D23.3 is corresponding are 8 ' b0111_0111, corresponding described low 5 Bit data din[4:0] be 5 ' b1_0111, described high 3 Bit data din[7:5] be 3 ' b011.The polarity of supposing described outer input data is that current character polar signal crd is rd+.
One indicator signal (symbol), described 8 Bit datas that are used to refer to outside input are data character or control character, and described indicator signal is input to respectively the coding that described 5b/6b encoder 101 based on rd+ and described 3b/4b encoder 102 and being used for based on rd+ are controlled described 5b/6b encoder 101 based on rd+ and described 3b/4b encoder 102 based on rd+.If described 8 Bit datas are data characters, described 5b/6b encoder 101 based on rd+ according to the rd+ coding rule of data character carry out the 5b/6b coding, described 3b/4b encoder 102 based on rd+ carries out the 3b/4b coding according to the rd+ coding rule of data character; If described 8 Bit datas are control characters, then described 5b/6b encoder 101 based on rd+ according to the rd+ coding rule of control character carry out the 5b/6b coding, described 3b/4b encoder 102 based on rd+ carries out the 3b/4b coding according to the rd+ coding rule of control character.
Because 8 Bit datas are data characters described in the embodiment of the invention, so described 5b/6b encoder 101 based on rd+ carries out the 5b/6b coding according to the rd+ coding rule of data character in embodiments of the present invention, namely to described low 5 Bit data din[4:0] namely 5 ' b1_0111 carry out 5b/6b according to the rd+ coding rule of data character and encode, coding result is 6 ' b10_1000, namely with 6 ' b10_1000 as first coding data enc_5b[5:0] output; The described polarity of 5b/6b encoder in cataloged procedure based on rd+ changes simultaneously, and this variation represents with the first change in polarity indications signal rd_flag_5b and exports.
Described 3b/4b encoder 102 based on rd+ carries out the 3b/4b coding according to the rd+ coding rule of data character, namely to described high 3 Bit data din[7:5] namely 3 ' b011 carry out the 3b/4b coding according to the rd+ coding rule of data character, coding result is 4 ' b1100, namely with 4 ' b1100 as the second coded data enc_3b[3:0] output; The described polarity of 3b/4b encoder in cataloged procedure based on rd+ also changes simultaneously, and this variation represents with the second change in polarity indications signal rd_flag_3b and exports.
Described first coding data enc_5b[5:0] be input to described 5b post-processing module 103, described 5b post-processing module 103 under the control of the described current character polar signal crd of described the first change in polarity indications signal rd_flag_5b and outside input to described first coding data enc_5b[5:0] carry out reprocessing; The first rear coded data dpost_5b[5:0 of output one 6 bits after described 5b post-processing module 103 is processed].If described the first change in polarity indications signal rd_flag_5b represents that the described polarity of 5b/6b encoder 101 in cataloged procedure based on rd+ changes and described current character polar signal crd when employed polarity is not identical in cataloged procedure with described 5b/6b encoder 101 based on rd+, 103 couples of described first coding data enc_5b[5:0 of described 5b post-processing module] all step-by-step negates and generate the described first rear coded data dpost_5b[5:0]; Under other condition, described 5b post-processing module 103 is not to described first coding data enc_5b[5:0] process, but directly with the described first rear coded data dpost_5b[5:0] be taken as described first coding data enc_5b[5:0].
In embodiments of the present invention, described the first change in polarity indications signal rd_flag_5b represents that variation has occured the described polarity of 5b/6b encoder 101 in cataloged procedure based on rd+; But described current character polar signal crd is that rd+, described 5b/6b encoder 101 employed polarity in cataloged procedure based on rd+ also are rd+ (that is: use is based on the coding rule of rd+), therefore the two polarity is identical.So last described 5b post-processing module 103 is not to described first coding data enc_5b[5:0] process, but directly with the described first rear coded data dpost_5b[5:0] be taken as described first coding data enc_5b[5:0] i.e. 6 ' b10_1000.
Described first XOR module 106 is used for described the first change in polarity indications signal rd_flag_5b and described current character polar signal crd are carried out the XOR processing and produce described the second character polar signal enc_rd.In embodiments of the present invention, because variation has occured in the described polarity of 5b/6b encoder 101 in cataloged procedure based on rd+, therefore described the first change in polarity indications signal rd_flag_5b is 1, described the second character polar signal enc_rd is different with described current character polar signal crd, and last described the second character polar signal enc_rd is rd-.
Described second XOR module 107 is used for that described the second change in polarity indications signal rd_flag_3b and described the second character polar signal enc_rd are carried out XOR and processes and produce next character polar signal nrd and described next character polar signal nrd is externally exported.In the embodiment of the invention since the described polarity of 3b/4b encoder in cataloged procedure based on rd+ change, therefore described the second change in polarity indications signal rd_flag_3b is 1, so the polarity of the polarity of next character polar signal nrd and described the second character polar signal enc_rd is opposite, next character polar signal nrd is rd+ at last.
Described the second coded data enc_3b[3:0] be input to described 3b post-processing module 104, described 3b post-processing module 104 under the control of described the second change in polarity indications signal rd_flag_3b and the second character polar signal enc_rd to described the second coded data enc_3b[3:0] carry out reprocessing; The second rear coded data dpost_3b[3:0 of output one 4 bits after described 3b post-processing module 104 is processed].If described the second change in polarity indications signal rd_flag_3b represents that the described polarity of 3b/4b encoder 102 in cataloged procedure based on rd+ changes and described the second character polar signal enc_rd when employed polarity is not identical in cataloged procedure with described 3b/4b encoder 102 based on rd+, 104 couples of described the second coded data enc_3b[3:0 of described 3b post-processing module] all step-by-step negates and generate the described second rear coded data dpost_3b[3:0]; Under other condition, described 3b post-processing module 104 is not to described the second coded data enc_3b[3:0] process, but directly with the described second rear coded data dpost_3b[3:0] be taken as described the second coded data enc_3b[3:0].
In embodiments of the present invention, described the second change in polarity indications signal rd_flag_3b represents that variation has occured the described polarity of 3b/4b encoder 102 in cataloged procedure based on rd+; And the polarity of described the second character polar signal enc_rd is rd-, and described 3b/4b encoder 102 employed polarity in cataloged procedure based on rd+ is rd+ (that is: use is based on the coding rule of rd+), therefore the two polarity is different.So, 104 couples of described the second coded data enc_3b[3:0 of last described 3b post-processing module] all step-by-step negates and generate the described second rear coded data dpost_3b[3:0]; The the described second rear coded data dpost_3b[3:0 that obtains at last] be 4 ' b0011.
The described first rear coded data dpost_5b[5:0] and the described second rear coded data dpost_3b[3:0] all be sent to described data merge module 105 carry out data merge process and export the output data dout[9:0 of 10 bits after merging].Described data merge module 105 with the described first rear coded data dpost_5b[5:0] as hang down 6, with the described second rear coded data dpost_3b[3:0] merge as high 4, and generate the output data of one 10 bit bit wides.Merge the described output data dout[9:0 that obtains after processing in the embodiment of the invention] be 10 ' b00_1110_1000.
Abovely by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (6)

1. the 8b/10b coding circuit based on rd+ is characterized in that: by merging module and two XOR module compositions based on the 5b/6b encoder of rd+, the 3b/4b encoder based on rd+, 5b post-processing module, 3b post-processing module, data;
Outer input data is 8 Bit datas, and this 8 Bit data is split as low 5 Bit datas and high 3 Bit datas, and described low 5 Bit datas are input to described 5b/6b encoder based on rd+, and described high 3 Bit datas are input to described 3b/4b encoder based on rd+;
One indicator signal, described indicator signal are input to respectively described 5b/6b encoder based on rd+ and described 3b/4b encoder based on rd+; Described indicator signal is used for controlling the coding of described 5b/6b encoder based on rd+ and described 3b/4b encoder based on rd+; The first coding data of output the first change in polarity indications signal and one 6 bits after described 5b/6b encoder encodes based on rd+ is finished; The second coded data of output the second change in polarity indications signal and one 4 bits after described 3b/4b encoder encodes based on rd+ is finished;
Described first coding data is input to described 5b post-processing module, and described 5b post-processing module is carried out reprocessing to described first coding data under the control of the current character polar signal of described the first change in polarity indications signal and outside input; The first rear coded data of output one 6 bits after described 5b post-processing module is processed;
Described the second coded data is input to described 3b post-processing module, and described 3b post-processing module is carried out reprocessing to described the second coded data under the control of described the second change in polarity indications signal and the second character polar signal; The second rear coded data of output one 4 bits after described 3b post-processing module is processed;
The described first rear coded data and the described second rear coded data all are sent to described data and merge the output data that module is carried out 10 bits after data merge processing and export a merging;
First XOR module is used for described the first change in polarity indications signal and described current character polar signal are carried out the XOR processing and produce described the second character polar signal; Second XOR module is used for that described the second change in polarity indications signal and described the second character polar signal are carried out XOR and processes and produce next character polar signal and described next character polar signal is externally exported.
2. the 8b/10b coding circuit based on rd+ as claimed in claim 1, it is characterized in that: described 5b/6b encoder based on rd+ is based on the 5b/6b encoder that the rd+ coding method realizes; Described 8 Bit datas that described indicator signal is used to refer to outside input are data character or control character, if described 8 Bit datas are data characters, described 5b/6b encoder based on rd+ carries out the 5b/6b coding according to the rd+ coding rule of data character; If described 8 Bit datas are control characters, then described 5b/6b encoder based on rd+ carries out the 5b/6b coding according to the rd+ coding rule of control character; Described the first change in polarity indications signal is used for representing that described 5b/6b encoder based on rd+ is in the change in polarity situation of cataloged procedure.
3. the 8b/10b coding circuit based on rd+ as claimed in claim 1, it is characterized in that: described 3b/4b encoder based on rd+ is based on the 3b/4b encoder that the rd+ coding method realizes; Described 8 Bit datas that described indicator signal is used to refer to outside input are data character or control character, if described 8 Bit datas are data characters, described 3b/4b encoder based on rd+ carries out the 3b/4b coding according to the rd+ coding rule of data character; If described 8 Bit datas are control characters, then described 3b/4b encoder based on rd+ carries out the 3b/4b coding according to the rd+ coding rule of control character; Described the second change in polarity indications signal is used for representing that described 3b/4b encoder based on rd+ is in the change in polarity situation of cataloged procedure.
4. the 8b/10b coding circuit based on rd+ as claimed in claim 1, it is characterized in that: if the described polarity of 5b/6b encoder in cataloged procedure based on rd+ of described the first change in polarity indications signal indication changes and described current character polar signal when employed polarity is not identical in cataloged procedure with described 5b/6b encoder based on rd+, described 5b post-processing module is to all step-by-step negates of described first coding data and generate the described first rear coded data; Under other condition, described 5b post-processing module is not processed described first coding data, but directly the described first rear coded data is taken as described first coding data.
5. the 8b/10b coding circuit based on rd+ as claimed in claim 1, it is characterized in that: if the described polarity of 3b/4b encoder in cataloged procedure based on rd+ of described the second change in polarity indications signal indication changes and described the second character polar signal when employed polarity is not identical in cataloged procedure with described 3b/4b encoder based on rd+, described 3b post-processing module is to all step-by-step negates of described the second coded data and generate the described second rear coded data; Under other condition, described 3b post-processing module is not processed described the second coded data, but directly the described second rear coded data is taken as described the second coded data.
6. the 8b/10b coding circuit based on rd+ as claimed in claim 1 is characterized in that: described data merge module will the described first rear coded data as hanging down 6, the described second rear coded data being merged the described output data that generate 10 bit bit wides as high 4.
CN2011102390465A 2011-08-19 2011-08-19 Rd+ based 8b/10b coding circuit Pending CN102957433A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106533613A (en) * 2015-09-10 2017-03-22 安徽大学 Novel high-speed 8B/10B coding circuit technology
CN109889306A (en) * 2019-01-16 2019-06-14 中国航空工业集团公司洛阳电光设备研究所 A kind of coding polarity calculation method for high speed fibre digital transmission system

Non-Patent Citations (3)

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Title
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陈孟杰 等: "《光纤通道8B/10B编解码模块设计》", 《电子测量技术》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106533613A (en) * 2015-09-10 2017-03-22 安徽大学 Novel high-speed 8B/10B coding circuit technology
CN109889306A (en) * 2019-01-16 2019-06-14 中国航空工业集团公司洛阳电光设备研究所 A kind of coding polarity calculation method for high speed fibre digital transmission system
CN109889306B (en) * 2019-01-16 2021-12-17 中国航空工业集团公司洛阳电光设备研究所 Encoding polarity calculation method for high-speed optical fiber digital transmission system

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Application publication date: 20130306