CN104426629A

CN104426629A - Physical layer coding and decoding methods and devices

Info

Publication number: CN104426629A
Application number: CN201310390805.7A
Authority: CN
Inventors: 杨文斌; 王童童
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2013-08-30
Filing date: 2013-08-30
Publication date: 2015-03-18
Anticipated expiration: 2033-08-30
Also published as: WO2015027755A1; US9467165B2; EP3041157A1; CN104426629B; EP3041157A4; EP3041157A8; EP3041157B1; US20160182084A1

Abstract

The application discloses physical layer coding and decoding methods and devices. A physical layer coding method comprises an input MII (Media Independence Interface) control block and a first 256-bit block to be coded; determining a control block in the first 256-bit block to be coded according to the MII control block, and compressing the determined control block; determining a physical layer coding format, a sync header numerical value, a hierarchy of a block type field and a numerical value of the block type field according to the MII block; mapping the compressed block to be coded to data in a physical layer data format according to the determined physical layer coding format, adding a sync header into the data, wherein the numerical value of the added sync header is the determined sync header numerical value, and adding a block type field in a space obtained through compression according to the hierarchy of the block type field to obtain a coding result, wherein the numerical value of the added block type field is the determined numerical value of the block type field. The application can satisfy the needs of an RS-FEC (Reed-Solomon Forward Error Correction) algorithm.

Description

A kind of physical layer decoding method and device thereof

Technical field

The present invention relates to the encoding and decoding technique of the communications field, particularly relate to a kind of physical layer decoding method and device thereof.

Background technology

100G ethernet physical layer comprises PCS(Physical Coding Sublayer from top to bottom, Physical Coding Sublayer), PMA(Physical Medium Attachment, physical medium connects) sublayer and PMD(Physical Media Dependent, physical medium is correlated with) sublayer.Wherein, PCS is positioned at MAC(MediaAccess Control, medium education) the RS(Reconciliation Sublayer of layer, reconciliation sublayer) and PMA sublayer between.The interface of PCS and RS/MAC sublayer, upper strata is by XGMII(XG MediaIndependence Interface, and Media Independent Interface, wherein, for 100G Ethernet, represents 100G with " CGMII ") provide.PCS for by an ethernet mac functional mapping to coding and physical layer signal system function on go.Specify in current 100G ethernet standard 802.3ba that PCS coding adopts 64B/66B coding.

64B/66B coding is used for the coding mapping that 88 bits (8-bit) data being transmitted by XGMII and 18 bit control carry out each character, produce block payload (Block Payload), synchronization field (syncheader) and block type territory (Block Type Field), and three is generated 66 bit blocks (Block) parallel output according to certain form.Wherein, block type territory (the Block Type Field) Hamming distance be used between guarantee 64 bit block is not less than 4.

Fig. 1 is the code conversion form shfft of the 64B/66B coding provided in existing 802.3ba standard.Wherein, D _nrepresent the data block of 8 bits, C _nrepresent controll block (being 8 bits before coding, is 7 bits after coding), O ₀represent Order sequence(command sequence) instruction, T _nrepresent the position of data handbag tail Terminate.Can find out, the all data block of 64 bits (does not namely wherein comprise control code block, can datablocks be expressed as) cannot compress, the non-fully data block of 64 bits (namely wherein includes controll block, can controlblocks be expressed as) compressible be 56 bits, as Block Type Field space, 8 remaining bits ensure that control information such as Terminate(terminates), Start(starts), Order sequence(command sequence), Control(controls) etc. the Hamming distance between 64 bit code blocks be not less than 4.

Along with the proposition of 400G ethernet standard, owing to adopting the technology such as high-speed interface and high order modulation, therefore the RS-FEC(Reed-Solomon Forward Error Correction of more high-gain is adopted, in Saloman forward error correction) scheme becomes following development trend, but 64B/66B coding method can not meet the needs of RS-FEC algorithm.

Summary of the invention

Embodiments provide a kind of physical layer decoding method and device thereof, in order to meet RS-FEC algorithm needs.

First aspect, provides a kind of coding method, comprising:

The Media Independent Interface MII receiving input controls code block and the one 256 bit code block to be encoded;

Determine the control code block in described one 256 bit code block to be encoded according to described MII control code block, the control code block determined is compressed, to obtain the code block to be encoded after compressing;

Code block determination physical layer encodes form, synchronization field numerical value, the level in block type territory and the numerical value in described block type territory is controlled according to described MII;

According to the physical layer encodes form determined, code block to be encoded after described compression is mapped as the data of physical layer data form, synchronization field is added in described data, the numerical value of the synchronization field of described interpolation for described in the synchronization field numerical value determined, level according to described block type territory adds block type territory in the space obtained by compression, to obtain coding result, the numerical value in the block type territory of described interpolation for described in the numerical value in block type territory determined.

In conjunction with first aspect, in the implementation that the first is possible, described one 256 bit code block to be encoded comprises 4 tunnel 64 bit code block to be encoded, described MII controls code block and comprises 4 tunnel 8 bit MII control code blocks, and described 4 tunnel 8 bit MII control code block and described 4 tunnel 64 bit code block one_to_one corresponding to be encoded;

The described control code block determined according to described MII control code block in described one 256 bit code block to be encoded, compresses the control code block determined, comprising:

Respectively to each road code block to be encoded in 4 tunnel 64 bit code block to be encoded, perform following steps:

The 8 bit MII according to correspondence control code block, determine the control code block in 64 bit code block to be encoded;

If comprise 88 bits in 64 bit code block to be encoded to control code block, then every 8 bits are controlled code block boil down to 7 bit and control code block; And/or,

If include terminate code word, sequence code word or sfd code word in 64 bit code block to be encoded, then by the code block of 64 bit code block boil down to 56 to be encoded bit.

In conjunction with the first possible implementation of first aspect or first aspect, in the implementation that the second is possible, describedly control code block determination synchronization field numerical value according to described MII, comprising:

Control after code block determines in described one 256 bit code block to be encoded and comprise and control code block, to determine that described synchronization field numerical value is the first numerical value according to described MII;

Described method also comprises: do not comprise control code block if determine in described one 256 bit code block to be encoded according to described MII control code block, then determine that described synchronization field numerical value is second value, described second value is different from described first numerical value.

In conjunction with the implementation that the first or the second of first aspect or first aspect are possible, in the implementation that the third is possible, describedly control the level in code block determination block type territory and the numerical value in described block type territory according to described MII, comprising:

If control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising N number of 64 bits controls code blocks, described N be less than 3 positive integer, then determine to adopt one-level block type territory;

Determine the numerical value in first order block type territory in described one-level block type territory, the numerical value in the first order block type territory that the numerical value in described first order block type territory is corresponding from the 2 256 bit code block to be encoded of reception is different, described 2 256 bit code block to be encoded comprises Y 64 bits and controls code block, described Y be less than 3 positive integer, described Y 64 bits control code blocks are different from the type that described N number of 64 bits control code block, or position is different, or the position of the identical control code block of type is different.

In conjunction with the third possible implementation of first aspect, in the 4th kind of possible implementation, if control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising N number of 64 bits controls code block, then determine to adopt one-level block type territory, comprising:

If 64 bits comprising 1 termination type in described one 256 bit code block to be encoded control code block Terminate block and 3 64 Bit data code blocks, then according to the position of the Terminate code word in described Terminate block, determine the numerical value in first order block type territory in described one-level block type territory.

In conjunction with the implementation that the first or the second of first aspect or first aspect are possible, in the 5th kind of possible implementation, describedly control the level in code block determination block type territory and the numerical value in described block type territory according to described MII, comprising:

If control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising M 64 bits controls code blocks, described M be greater than 2 and be less than 5 positive integer, then determine to adopt two-stage block type territory;

Determine the numerical value in first order block type territory in described two-stage block type territory, the numerical value in the first order block type territory that the numerical value in described first order block type territory is corresponding with the 3 256 bit code block to be encoded of reception is identical, and the numerical value in the first order block type territory corresponding from the 4 256 bit code block to be encoded received is different; Described 3 256 bit code block to be encoded comprises X 64 bits and controls code blocks, described X be greater than 2 and be less than 5 positive integer, described 4 256 bit code block to be encoded comprises Z 64 bits and controls code blocks, described Z be less than 3 positive integer;

Determine the numerical value in block type territory, the second level in described two-stage block type territory, the numerical value in the block type territory, the second level that the numerical value in block type territory, the described second level is corresponding from the 5 256 bit code block to be encoded of reception is different, described 5 256 bit code block to be encoded comprises Q 64 bits and controls code block, described Q be greater than 2 and be less than 5 positive integer, described Q 64 bits control code blocks are different from the type that described M 64 bits control code block, or position is different, or the position of the control code block that type is identical is different, the numerical value in the first order block type territory that the numerical value in the first order block type territory that described 5 256 bit code block to be encoded is corresponding is corresponding with described one 256 bit code block to be encoded is identical.

In conjunction with first aspect the third, the 4th kind or the 5th kind of possible implementation, in the 6th kind of possible implementation, also comprise:

If control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising at least 2 64 bits controls code block, and one of them control code block is Terminate block, then according to the position of the Terminate code word in described Terminate block, determine instructions field numerical value, and instructions field is added in the space obtained by compression, the numerical value of the instructions field of described interpolation for described in the instructions field numerical value determined, the numerical value of the instructions field of described interpolation is for identifying the position of the Terminate code word in Terminate block.

In conjunction with the second of first party, first aspect to the one in the 5th kind of possible implementation, in the 7th kind of possible implementation, described synchronization field width is N bit, N >=1.

Second aspect, provides a kind of encoder, comprising:

Precoding module, Media Independent Interface MII for receiving input controls code block and the one 256 bit code block to be encoded, the control code block in described one 256 bit code block to be encoded is determined according to described MII control code block, the control code block determined is compressed, to obtain the code block to be encoded after compressing;

Coding module, for controlling code block determination physical layer encodes form according to described MII, synchronization field numerical value, the level in block type territory and the numerical value in described block type territory, according to the physical layer encodes form determined, code block to be encoded after the described compression described precoding module exported is mapped as the data of physical layer data form, synchronization field is added in described data, the numerical value of the synchronization field of described interpolation for described in the synchronization field numerical value determined, level according to block type territory adds block type territory in the space that described precoding module is obtained by compression, to obtain coding result, the numerical value in the block type territory of described interpolation for described in the block type territory numerical value determined.

In conjunction with second aspect, in the implementation that the first is possible, described one 256 bit code block to be encoded comprises 4 tunnel 64 bit code block to be encoded, described MII controls code block and comprises 4 tunnel 8 bit MII control code blocks, and described 4 tunnel 8 bit MII control code block and described 4 tunnel 64 bit code block one_to_one corresponding to be encoded;

Described precoding module comprises 4 precoding unit, and each described coding unit, respectively to each road code block to be encoded in 4 tunnel 64 bit code block to be encoded, performs following steps:

The 8 bit MII according to correspondence control code block, determine the control code block in 64 bit code block to be encoded; If comprise 88 bits in 64 bit code block to be encoded to control code block, then every 8 bits are controlled code block boil down to 7 bit and control code block, and/or, if include terminate code word, sequence code word or sfd code word in 64 bit code block to be encoded, then by the code block of 64 bit code block boil down to 56 to be encoded bit.

In conjunction with second aspect, in the implementation that the second is possible, described coding module specifically for, if determine in described one 256 bit code block to be encoded according to described MII control code block and comprise control code block, then determine that described synchronization field numerical value is the first numerical value, if determine in described one 256 bit code block to be encoded according to described MII control code block and do not comprise control code block, then determine that described synchronization field numerical value is second value, described second value is different from described first numerical value.

In conjunction with second aspect, in the implementation that the third is possible, described coding module specifically for, if control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising N number of 64 bits controls code block, described N be less than 3 positive integer, then determine adopt one-level block type territory; Determine the numerical value in first order block type territory in described one-level block type territory, the numerical value in the first order block type territory that the numerical value in described first order block type territory is corresponding from the 2 256 bit code block to be encoded of reception is different, described 2 256 bit code block to be encoded comprises Y 64 bits and controls code block, described Y be less than 3 positive integer, described Y 64 bits control code blocks are different from the type that described N number of 64 bits control code block, or position is different, or the position of the identical control code block of type is different.

In conjunction with second aspect, in the 4th kind of possible implementation, described coding module specifically for, if 64 bits comprising 1 termination type in described one 256 bit code block to be encoded control code block Terminate block and 3 64 Bit data code blocks, then according to the position of the Terminate code word in described Terminate block, determine the numerical value in first order block type territory in described one-level block type territory.

In conjunction with the first possible implementation of second aspect or second aspect, in the 5th kind of possible implementation, described coding module specifically for, if control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising M 64 bits controls code block, described M be greater than 2 and be less than 5 positive integer, then determine adopt two-stage block type territory, determine the numerical value in first order block type territory in described two-stage block type territory, the numerical value in the first order block type territory that the numerical value in described first order block type territory is corresponding with the 3 256 bit code block to be encoded of reception is identical, and the numerical value in the first order block type territory corresponding from the 4 256 bit code block to be encoded received is different, described 3 256 bit code block to be encoded comprises X 64 bits and controls code block, described X be greater than 2 and be less than 5 positive integer, described 4 256 bit code block to be encoded comprises Z 64 bits and controls code blocks, described Z be less than 3 positive integer, determine the numerical value in block type territory, the second level in described two-stage block type territory, the numerical value in the block type territory, the second level that the numerical value in block type territory, the described second level is corresponding from the 5 256 bit code block to be encoded of reception is different, described 5 256 bit code block to be encoded comprises Q 64 bits and controls code block, described Q be greater than 2 and be less than 5 positive integer, described Q 64 bits control code blocks are different from the type that described M 64 bits control code block, or position is different, or the position of the control code block that type is identical is different, the numerical value in the first order block type territory that the numerical value in the first order block type territory that described 5 256 bit code block to be encoded is corresponding is corresponding with described one 256 bit code block to be encoded is identical.

In conjunction with the third of second aspect to the one in the 5th kind of possible implementation, in the 6th kind of possible implementation, described coding module also for, if control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising at least 2 64 bits controls code block, and one of them control code block is Terminate block, then according to the position of the Terminate code word in Terminate block, determine instructions field numerical value, and instructions field is added in the space that described precoding module is obtained by compression, the numerical value of the instructions field of described interpolation for described in the instructions field numerical value determined, the instructions field numerical value of described interpolation is for identifying the position of the Terminate code word in Terminate block.

In conjunction with second aspect, second aspect the first to the one in the 5th kind of possible implementation, in the 7th kind of possible implementation, described synchronization field width is N bit, N >=1.

The third aspect, provides a kind of coding/decoding method, comprising:

Receive the first code block to be decoded;

According to the numerical value in the synchronization field numerical value of described first code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described first code block to be decoded;

According to the physical layer data form of described first code block to be decoded, obtain the control code block in described first code block to be decoded and data code block, and generate media have nothing to do MII control code block;

The control code block got is decompressed;

Being exported with the data code block got by control code block after decompression is 256 bit code blocks, and exports described MII control code block.

In conjunction with the third aspect, in the implementation that the first is possible, the numerical value in the described synchronization field numerical value according to described first code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described first code block to be decoded, comprising:

If the synchronization field numerical value of described first code block to be decoded is the first numerical value, then determine to comprise control code block in described first code block to be decoded;

Described method also comprises:

Receive the 3rd code block to be decoded;

According to the numerical value in the synchronization field numerical value of described 3rd code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described 3rd code block to be decoded, according to the physical layer data form of described 3rd code block to be decoded, obtain the data code block in described 3rd code block to be decoded;

The numerical value in the described synchronization field numerical value according to described 3rd code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described 3rd code block to be decoded, comprising:

If the synchronization field numerical value of described 3rd code block to be decoded is second value, then determine not comprise control code block in described 3rd code block to be decoded, described second value is different from described first numerical value.

In conjunction with the third aspect, in the implementation that the second is possible, the numerical value in the described synchronization field numerical value according to described first code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described first code block to be decoded, comprising:

If determine in described first code block to be decoded according to the synchronization field numerical value of described first code block to be decoded and comprise control code block, then determine the block type territory level of described first code block to be decoded according to the numerical value in the one-level block type territory of described first code block to be decoded;

If the level determining the block type territory of described first code block to be decoded is one-level, then determine in described first code block to be decoded comprise N number of 64 bits control code blocks, described N be less than 3 positive integer;

If determine, the level in the block type territory of described first code block to be decoded is at least two-stage, then determine in described first code block to be decoded that comprising M 64 bits controls code blocks, described M be greater than 2 and be less than 5 positive integer.

In conjunction with the implementation that the second of the third aspect is possible, in the implementation that the third is possible, the numerical value in the described synchronization field numerical value according to described first code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described first code block to be decoded, also comprise:

If the level determining the block type territory of described first code block to be decoded is one-level, and controlling to there is Terminate block in code block according to 64 bits that the numerical value in the one-level block type territory determined is determined in described first code block to be decoded, then the numerical value in the one-level block type territory determined described in basis determines the position of the Terminate code word in Terminate block.

In conjunction with the third aspect, in the 4th kind of possible implementation, if according to the physical layer data form of described first code block to be decoded determined, determine in described first code block to be decoded and also comprise instructions field, then also comprise:

According to the numerical value of described instructions field, determine that in described first code block to be decoded, Terminate block controls the position of the Terminate code word in code block.

In conjunction with the third aspect, in the 5th kind of possible implementation, described control code block in described first code block to be decoded to be decompressed, comprising:

Described first code block to be decoded is divided into 4 tunnel second code blocks to be decoded, perform following steps to described 4 tunnel second code blocks to be decoded respectively: if comprise 87 bits in the second code block to be decoded to control code block, then every 7 bits being controlled code block decompression is that 8 bits control code blocks; If include Terminate code word, sequence code word or sfd code word in the second code block to be decoded, then described second code block decompress(ion) to be decoded is condensed to 64 bit code blocks.

In conjunction with the third aspect, the third aspect the first to the one in the 5th kind of possible implementation, in the 6th kind of possible implementation, described synchronization field width is N bit, N >=1.

The third aspect, provides a kind of decoder, comprising:

Decoder module, for receiving the first code block to be decoded, according to the numerical value in the synchronization field numerical value of described first code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described first code block to be decoded, according to the physical layer data form of described first code block to be decoded, obtain the control code block in described first code block to be decoded and data code block, and generate media have nothing to do MII control code block;

Decompression module, control code block for being got by described decoder module decompresses, it is 256 bit code blocks that data code block control code block after decompression and described decoder module got exports, and the described MII exporting the generation of described decoding code block controls code block.

In conjunction with fourth aspect, in the implementation that the first is possible, described decoder module specifically for, if the synchronization field numerical value of described first code block to be decoded is the first numerical value, then determine to comprise control code block in described code block to be decoded;

Described decoder module also for, receive the 3rd code block to be decoded, according to the numerical value in the synchronization field numerical value of described 3rd code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described 3rd code block to be decoded, according to the physical layer data form of described 3rd code block to be decoded, obtain the data code block in described 3rd code block to be decoded, if the synchronization field numerical value of described 3rd code block to be decoded is second value, then determine not comprise control code block in described 3rd code block to be decoded, described second value is different from described first numerical value.

In conjunction with fourth aspect, in the implementation that the second is possible, described decoder module specifically for, if determine in described first code block to be decoded according to the synchronization field numerical value of described first code block to be decoded and comprise control code block, then determine the block type territory level of described first code block to be decoded according to the numerical value in the one-level block type territory of described first code block to be decoded; If the level determining the block type territory of described first code block to be decoded is one-level, then determine in described first code block to be decoded comprise N number of 64 bits control code blocks, described N be less than 3 positive integer; If determine, the level in the block type territory of described first code block to be decoded is at least two-stage, then determine in described first code block to be decoded that comprising M 64 bits controls code blocks, described M be greater than 2 and be less than 5 positive integer.

In conjunction with the implementation that the second of fourth aspect is possible, in the implementation that the third is possible, described decoder module also specifically for, if the level determining the block type territory of described first code block to be decoded is one-level, and controlling to there is Terminate block in code block according to 64 bits that the numerical value in the one-level block type territory determined is determined in described first code block to be decoded, then the numerical value in the one-level block type territory determined described in basis determines the position of the terminate code word in Terminate block.

In conjunction with fourth aspect, in the 4th kind of possible implementation, described decoder module specifically for, if according to the physical layer data form of described first code block to be decoded determined, determine in described first code block to be decoded and also comprise instructions field, then according to the numerical value of described instructions field, determine that in described first code block to be decoded, Terminate block controls the position of the Terminate code word in code block.

In conjunction with fourth aspect, in the 5th kind of possible implementation, described decompression module comprises 4 decompression units, described first code block to be decoded is divided into 4 tunnel second code blocks to be decoded by described decompression module, and each described decompression unit performs following steps to described 4 tunnel second code blocks to be decoded respectively:

If comprise 87 bits in the second code block to be decoded to control code block, then every 7 bits being controlled code block decompression is that 8 bits control code blocks; If include Terminate code word, sequence code word or sfd code word in the second code block to be decoded, then described second code block decompress(ion) to be decoded is condensed to 64 bit code blocks.

5th aspect, provides a kind of device, and this device can be with one of lower device:

PHY, described PHY can be realized by FPGA or ASIC.Described PHY can be the parts in network interface unit (Network Interface Card, NIC), and described NIC can be line card (LineCard) or PIC(Physical Interface Card, physical interface card).Described PHY can comprise the Media-Independent Interface(Media Independent Interface for being connected to (for interfacing to) MAC, MII);

PHY chip (PHY chip), described PHY chip can comprise multiple PHY.Described PHY chip can be realized by FPGA or ASIC;

System on Chip/SoC (system chip), described System on Chip/SoC can comprise multiple MAC and multiple PHY; Described System on Chip/SoC can be realized by FPGA or ASIC;

Multiport ethernet device (multi-port Ethernet device), described multiport ethernet device can be ethernet concentrator, ethernet router or Ethernet switch.Described multiport ethernet device comprises multiple port, and each port can comprise System on Chip/SoC, and described System on Chip/SoC can comprise MAC and PHY.Multiple MAC can also be incorporated into a MAC chip (MACchip) by described multiport ethernet device, and multiple PHY is incorporated into a PHY chip.Multiple MAC and multiple PHY also can be incorporated in a System on Chip/SoC by described multiport ethernet device;

This device can perform the method that any one the possible implementation in first aspect or first aspect provides.

6th aspect, provides a kind of device, and this device can be with one of lower device:

This device can perform the method that any one the possible implementation in the third aspect or the third aspect provides.

In the above embodiment of the present invention, when encoding, code block determination physical layer encodes form, synchronization field numerical value, the level in block type territory and the numerical value in block type territory is controlled according to MII, according to the physical layer encodes form determined, the code block to be encoded after precoding is mapped as physical layer data form, thus realizes to encode to 256 bit code blocks.Can find out, the embodiment of the present invention, by utilizing 256 bit code block compressible space, ensures that the Hamming distance between 256 bit code block to be encoded is not less than 4, and can be the School Affairs space that RS-FEC algorithm provides enough.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the code conversion form shfft of the 64B/66B coding provided in existing 802.3ba standard;

Fig. 2 A and Fig. 2 B is the schematic diagram that existing 64B/66B coding adds 256B/257B Transcoding Scheme;

The coding principle schematic diagram that Fig. 3 provides for the embodiment of the present invention;

The 256B/257B coded format table that Fig. 4 provides for the embodiment of the present invention;

The 256B/258B coded format table that Fig. 5 provides for the embodiment of the present invention;

Fig. 6 is the application architecture schematic diagram of the embodiment of the present invention;

The structural representation of the encoder that Fig. 7 provides for the embodiment of the present invention;

The coding schematic flow sheet that Fig. 8 provides for the embodiment of the present invention;

A kind of generic state redirect schematic diagram that Fig. 9 provides for the embodiment of the present invention;

One of state machine diagram of the 256B/257B encoding scheme that Figure 10 provides for the embodiment of the present invention;

The state machine diagram two of the 256B/257B encoding scheme that Figure 11 provides for the embodiment of the present invention;

The state machine diagram of the 256B/258B encoding scheme that Figure 12 provides for the embodiment of the present invention;

The MTTFPA index schematic diagram of the 256B/258B encoding scheme that Figure 13 provides for the embodiment of the present invention;

The structural representation of the decoder that Figure 14 provides for the embodiment of the present invention;

The decoding process schematic diagram that Figure 15 provides for the embodiment of the present invention.

Embodiment

In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.

Because 64B/66B no longer adapts to the FEC(Forward Error Correction of following high-gain, forward error correction) demand, therefore have a kind of evolution scheme of extension at present, namely 64B/66B coding adds the scheme of 256B/257B transcoding.In this scenario, for all data pattern of 256 bits, as shown in Figure 2 A, wherein, DB represents the Data Block(data code block of 64 bits to its Transcoding Scheme), " 01 " is synchronous head indication information, represents that the Block of 64 bits is subsequently data code block.The Transcoding Scheme of the 256B/257B of all data shown in Fig. 2 A is: out, then use 1 bit " 1 " to represent 257 bit all data code blocks dibit synchronous head indication information " 01 " compression before 4 66 bit code blocks.For the non-fully data pattern of 256 bits, as shown in Figure 2 B, wherein CB represents that the ControlBlock(of 56 bits controls code block to its Transcoding Scheme), " 10 " are synchronous head indication informations, represent that the Block of 56 bits is subsequently for controlling code block.In the Transcoding Scheme of the 256B/257B of the non-all data shown in Fig. 2 B, the front dibit synchronous head indication information of 4 66 bit code blocks is compressed equally during transcoding, the non-fully data code block (control blocks) of 257 bits is represented with 1 bit " 0 ", then before first 64 bit being controlled 8 bit space of the BlockType Field of code block, 4 bits retain, it is data or the indicating bit controlling code block that rear 4 bits are used as 4 64 bit code blocks, in such as Fig. 2 B, the code block of 4 64 bits is control code block, therefore is encoded to " 0000 ".

Above 64B/66B coding adds the scheme of 256B/257B transcoding, just a kind of format conversion, it is not actual direct coding and decoding scheme, 64B/66B encoding and decoding must be needed to realize corresponding function simultaneously, therefore this forwarding scheme can increase extra time delay, and increases extra resource occupation and power consumption.

For the demand of RS-FEC scheme adopting more high-gain, embodiments provide a kind of scheme being applied to the direct encoding and decoding of PCS in physical layer, this coding and decoding scheme can comprise 256B/257B coding and decoding scheme or 256B/258B coding and decoding scheme.Below the coding and decoding scheme that the embodiment of the present invention provides is described in detail.

256B/257B coding in the embodiment of the present invention refers to: the encoder of PCS is by MII(MediaIndependence Interface, Media Independent Interface) the 4 tunnel 64 bit code blocks to be encoded that transmit carry out the coding mapping of code word, produce block payload (Block Payload), synchronization field (sync header) and block type territory (Block Type Field), and three is generated 257 bit code block (Block) parallel outputs according to certain form; 256B/257B decoding refers to: contain what input the decoding mapping that block payload (Block Payload), synchronization field (sync header) and block type territory (Block Type Field) 257 bit code blocks carry out code word, obtain the code block (MII_TXD) of 4*64 bit, and exported by MII.Wherein, the quantity of code block is controlled according to 56 bits comprised in 257 bit code blocks after 256B/257B coding, one-level type field (Block Type Field) may be comprised in 257 bit code blocks after coding, also can comprise multiple-stage type territory (Block Type Field), be used for ensureing that the Hamming distance between each 256 bit code blocks is not less than 4.The process of 256B/258B coding/decoding is similar.

There is contradiction in the size in code efficiency and Block Type space, embodiment is in the present embodiment exactly: the Block Type spatial limitation number of code word.Such as through reckoning, namely the Block Type(finding minimum 4 bit Hamming distances in the space of 8 bits finds and can ensure that Hamming distance is not less than a group code word of 4), a lot of group code word can be found, but often only have at most 16 code words in group, in table 1, list one group that wherein has 16 code words.

Ensure that Hamming distance is not less than the combination of 4 in table 1:8 bit space

8’h1E	8’hE1	8’h4B	8’hB4
				8’h78	8’h87	8’hD2	8’h2D
8’h00	8’h33	8’h55	8’h66
				8’h99	8’hAA	8’hCC	8’hFF

Adopt 256 bits of encoded, the combined situation of all code words has exceeded 16 kinds, and therefore the BlockType space of 8 bits cannot ensure the Hamming distance between all 256 bit code blocks.

In order to solve the contradiction of current codec efficiency and Block Type code word space, in the coding and decoding scheme that the embodiment of the present invention provides, the compress technique of different code word space is carried out according to each 256 bit code block compressible space, realize classification and divide the compression of the different spaces of code block to reach encoding scheme flexibly, in cataloged procedure, ensure that the Hamming distance between 256 bits of encoded code blocks is not less than 4.

During concrete enforcement, for example, on the one hand, certain space (i.e. synchronization field) is adopted to distinguish all data code block (data blocks) of 256 bits and the non-fully data code block (control blocks) of 256 bits in 256 bit code blocks in encoded; On the other hand, in 256 bit code blocks in encoded, this Block Type Field of Block Type Field(is adopted to be called first order Block Type Field) as Block Type space, ensure the Hamming distance with other 256 bit code block.Because Block Type space is to the restriction of number of codewords, can not by all coded format of different Block Type Field unique identifications, therefore, for compressing the 256 bit code blocks obtaining more spaces, such as comprise the 256 bit code blocks that two or more 64 bits control code block, identical first order BlockType Field value can be adopted, ensure the Hamming distance between 256 code blocks that the first order Block Type Field value different from other is corresponding, 256 code blocks at these with identical first order Block Type Field value are inner, this Block Type Field of extra Block Type Field(is adopted to be called second level Block TypeField again) as Block Type space, ensure that these have the Hamming distance of 256 bit code interblocks of identical first order Block Type Field value.If necessary, the space compressing out can also be utilized further as third level Block Type Field, and even more multistage Block Type Field is to ensure the Hamming distance of 256 bit code blocks.Compress the space also to use as retaining space.

Alternatively, further, for the code block that some are more special, the T block(Terminate block of such as 64 bits, stop block), Block Type Field can be utilized or utilize extra instructions field to carry out the differentiation of the inner each code word of code block (such as, 7 bits control code word and/or 8 Bit data code words).For 64 bit T block, in T block, comprising the Terminate code word of 8 bits, also will indicate this position of Terminate code word in T block when encoding.For solving this problem, the embodiment of the present invention have employed following methods:

(1) if only comprise the T block of 1 64 bit in 256 bit code blocks, all the other are the data code block of 64 bits, then first order Block Type Field value can be utilized to identify the position of Terminate code word in this 64 bit T block.Concrete, when designing coded format table, for the 256 bit code blocks of T block and 3 64 bit data block comprising 1 64 bit, according to the diverse location of Terminate code word in T block code block, different first order Block Type Field values is set, thus utilize this Block Type Field value to ensure the Hamming distance with other 256 bit code block on the one hand, utilize this Block Type Field value to identify the position of Terminate code word in T block on the other hand;

(2) if comprise the T block of 1 64 bit and the control code block of other 64 bit one or more in 256 bit code blocks, then the space that these control code blocks can be utilized to compress indicates the position of Terminate code word in this 64 bit T block as extra instructions field.

Based on the principle of above coding, as shown in Figure 3, in coded format table, syna and synb is two kinds of values of synchronization field, for distinguishing all data code block (data blocks) and non-fully data code block (controlblocks).Wherein, syna is used for identifying all data code block (data blocks), and synb is used for identifying non-fully data code block (control blocks).Synchronization field can be 1 bit or more bit, and the amount of bits of synchronization field can carry out arranging and adjusting according to concrete framework, algorithm and performance requirement, and the embodiment of the present invention is not restricted this.

Type0 ~ typea in Fig. 3 is the value of first order Block Type Field, and typeA ~ typeD is the value of second level Block Type Field.Wherein, because Block Type space is to the restriction of number of codewords, cannot by a kind of coded format of different Block Type Field value unique identifications, therefore, for the 256 bit code blocks comprising 3 or 4 64 bits control code block (Control block), adopt identical first order Block Type Field value (typea as in figure), the space obtained by 256 bit code block internal compression is again as second level Block Type Field, by the different values of second level Block Type Field (as the typeA in figure, typeB, typeC, typeD) 256 code blocks that these have identical first order Block Type Field are distinguished.The code word space (i.e. the amount of bits of first order Block TypeField) of type0 ~ typea or the code word space (i.e. the amount of bits of second level Block Type Field) of typeA ~ typeD, be preferably 8 bits, bit number can certainly be set as the case may be, such as can be less than or more than 8 bits.

The control code block that Fig. 3 bend is filled represents special code block, such as T block, needs extra instructions field (typeT in figure) to indicate the position of Terminate code word in T block of 8 bits.TypeT value corresponding to the diverse location of Terminate code word is different, such as typeT=0x00, represent and Terminate code word be in the first character joint of T block (64 bit T block are according to 8 bit one group, be divided into 8 byte groups), typeT=0x11, represents that Terminate code word is in last byte of T block.The bit number of this instructions field is preferably 8 bits, can certainly arrange the amount of bits of this instructions field according to actual needs.

The space of all type of codings (comprises first order Block Type Field, second level Block TypeField, and instructions field) be all from the control code block of 64 bits, as S block(start block, begin block), T block or C block(Control block, controll block), compress out.For the bit compressing out from control code block, except for except above-mentioned first order Block Type Field, second level Block TypeField, instructions field, if there is remaining bits, then this remaining bits can be used as reserved bit territory (Res territory as shown in Figure 3).Further, as required, Res territory also can use as the Block Type Field of the third level or the fourth stage.

The value (type0 ~ typea as in figure) of the first order Block Type Field in Fig. 3, the value (typeA ~ typeD as in figure) of second level Block Type Field are only signal, in actual applications, can choose the numerical value shown in table 1.

It should be noted that, the coded format shown in above-mentioned Fig. 3 is only a kind of example, and the coded format table obtained according to above-mentioned coding principle, all should within protection scope of the present invention.

Based on above-mentioned coding principle, Fig. 4 shows the 256B/257B coded format table that the embodiment of the present invention provides.Wherein, the bit number of synchronization field is 1 bit, the bit number in Block Type Field territory is 8 bits, the bit number of instructions field is 8 bits.

As shown in Figure 4, for time " 0 ", synchronization field value represents that 256 bit code blocks are all data code block (datablocks), for time " 1 ", value represents that 256 bit code blocks are non-fully data code block (control blocks).

For including 1 64 bit T block and 3 64 bit DATA block(data code block) 256 bit code blocks, distinguish with different first order Block Type Field value (type0 ~ type7), this first order Block Type Field value, can also identify the position of 8 bit Terminate code words in T block simultaneously.As shown in Figure 4, first order Block Type Field value represents when being type0 that Terminate code word is arranged in the first character joint of T block, first order Block Type Field value represents that Terminate code word is positioned at second byte when being type1, by that analogy.

For including 1 64 bit T block, and other of more than 2 or 2 64 bits controls 256 bit code blocks of code block (as S block, C block), adopt identical first order Block TypeField value (typed), and different from the value of above-mentioned type0 ~ type7.In the inside of these 256 bit code blocks, recycling controls code block and compresses the Block Type Field territory, the spatial placement second level, and is distinguished by the value (typeA ~ typeE as in figure) of different second level Block Type Field.In like manner, for including 4 64 bit C block or including the 256 bit code blocks of 4 64 bit O block, also first order Block Type Field value can be set to typed, inner at this 256 bit code block again, control code block is utilized to compress the spatial placement second level Block Type Field, by the value (typeF, typeG as in figure) of different second level Block Type Field.

In addition, for including 1 64 bit T block, and other of more than 1 or 1 64 bits controls 256 bit code blocks of code block (as S block, C block), also will according to the position of 8 bit Terminate code words in T block, instructions field is set in this 256 bit code block, identifies the position of Terminate code word by different instructions field values (typeT as in figure).

Type0 ~ type7 in Fig. 4, typeA ~ typeE can choose from table 1, to ensure that Hamming distance is not less than 4.

In order to simplify the state number of Order sequence in Fig. 4, ensure that Order sequence is according to 256 bit aligned, realizability (the such as AM(Alignment Marker of global design can not be affected, alignment mark) the problem such as insertion), the mode of certain simplified design is not limited to aforesaid way.

Can be found out by the 256B/257B coded format table shown in Fig. 4, can ensure that Hamming distance is not less than 4 between 13 kind of 256 bit code block corresponding to first order Block Type Field value (type0 ~ type9, typea ~ typec), between 7 kind of 256 bit code block that first order Block Type Field value typed is corresponding and above-mentioned 13 kind of 256 bit code block, can ensure that Hamming distance is not less than 4; Between 7 kind of 256 bit code block that first order Block TypeField value typed is corresponding, minimum 4 bit Hamming distances can be kept by different second level Block Type Field value (typeA ~ typeG); By instructions field, the different Terminate positions in 64 bit T block ensure that Hamming distance is not less than 4.Such embodiment of the present invention just can ensure that the Hamming distance between each 256 bit code blocks is not less than 4.

In Fig. 4, the value of Block Type Field and instructions field can reference table 1.Table 2 shows the value table of a kind of Block Type Field and instructions field, and table 2 is only a kind of example, is not construed as limiting the invention.

The value of table 2:Block Type Field and instructions field

Based on above coding principle, Fig. 5 shows the 256B/258B coded format table that the embodiment of the present invention provides.Wherein, the bit number of Block Type Field territory and instructions field is 8 bits, identical with the 256B/257B coded format table shown in Fig. 4, and the bit number of synchronization field is 2 bits, than the many bits in the 256B/257B coded format table shown in Fig. 4.256B/258B coded format table shown in Fig. 5, basic identical with the 256B/257B coded format table shown in Fig. 4, in Fig. 5, the value of Block Type Field and instructions field also can reference table 1 value, is not described in detail in this.

According to above-mentioned coding principle, when arranging coded format table, the value of BlockType Field can be set according to following rule.

For the 256 bit code blocks including 1 or 2 64 bits control code blocks, can with the Block Type Field(of a level and first order Block Type Field) ensure the Hamming distance of these 256 bit code interblocks, the value that first order Block Type Field be determined in the type of code blocks or position can be controlled according to 64 comprised bits.All comprise 1 or 2 64 bits control code blocks for the one 256 bit code block and the 2 256 bit code block, in following several situation, the one 256 bit code block is different with the value in the first order block type territory of the 2 256 bit code block:

64 bits in situation 1: the one 256 bit code block control the type of code block, different from the type of the control code block in the 2 256 bit code block.In the 11st row in such as Fig. 4 and 257 bit code blocks shown in the 12nd row, DATA Block and 2 that all comprises 2 64 bits controls code block, but because the type controlling code block is incomplete same, (2 in the 11st row control code block is T block and S block, 2 in 12nd row control code block is T block and C block), therefore the value of first order Block Type Field is different, is namely respectively type9 and typea.

64 bits in situation 2: the one 256 bit code block control the position of code block, different from the position of the control code block in the 2 256 bit code block.In the 11st row in such as Fig. 4 and 257 bit code blocks shown in the 13rd row, all comprise the control code block that the DATA Block of 2 64 bits is identical with 2 types, but because DATA Block is different with the arrangement position controlling code block, therefore the value of first order Block Type Field is different, is namely respectively type9 and typeb.

64 bits in situation 3: the one 256 bit code block control the type of code blocks, identical from the type of the control code block in the 2 256 bit code block but position is different.Such as, 2 64 bit DATA Block, 1 S block, 1 C block is comprised successively in one 256 bit code block, comprise 2 64 bit DATA Block, 1 C block, 1 S block in 2 256 bit code block successively, then the one 256 bit code block is different with the value of the first order level Block Type Field of the 2 256 bit code block.

For including 3 or 4 64 bits control 256 bit code blocks of code blocks, can with the Block Type Field(of two levels and first order Block Type Field and second level Block Type Field).When determining the value of the first order Block Type Field in two-stage Block Type Field, the value of first order Block Type Field that 3 or 4 64 bits control 256 bit code blocks of code blocks can be comprised be set to all identical value, but different from comprising the value that 1 or 2 64 bits control the first order Block Type Field of 256 bit code blocks of code block.The value of the first order Block Type Field in 257 bit code blocks in such as Fig. 4 shown in 15th ~ 21 row is identical, but different from the value of the first order Block Type Field of any 257 bit code blocks shown in 2nd ~ 14 row.

When determining the value of the second level Block Type Field in two-stage Block Type Field, the value of second level Block Type Field can be determined according to the type of 64 comprised bits control code blocks or position.All comprise 3 or 4 64 bits control code blocks for the 3 256 bit code block and the 4 256 bit code block, in following several situation, the 3 256 bit code block is different with the value in the first order block type territory of the 4 256 bit code block:

64 bits in situation 1: the 3 256 bit code block control the type of code block, different from the type of the control code block in the 4 256 bit code block.In the 15th row in such as Fig. 4 and 257 bit code blocks shown in the 16th row, DATA Block and 3 that all comprises 1 64 bit controls code block, but because the type controlling code block is incomplete same, therefore the value of second level Block Type Field is different, is namely respectively typeA and typeB.

64 bits in situation 2: the 3 256 bit code block control the position of code block, different from the position of the control code block in the 4 256 bit code block.In the 16th row in such as Fig. 4 and 257 bit code blocks shown in the 17th row, DATA Block and 3 that all comprises 1 64 bit controls code block, but because DATABlock is different with the arrangement position controlling code block, therefore the value of second level Block Type Field is different, is namely respectively typeB and typeC.

64 bits in situation 3: the 3 256 bit code block control the type of code blocks, identical from the type of the control code block in the 4 256 bit code block but position is different.Such as, 1 64 bit DATA Block, 2 C block, 1 S block are comprised successively in 3 256 bit code block, comprise 1 64 bit DATA Block, 1 C block, 1 S block, 1 C Block in 4 256 bit code block successively, then the 3 256 bit code block is different with the value of the second level Block Type Field of the 4 256 bit code block.

The encoding scheme (as 256B/257B coding and decoding scheme and 256B/258B coding and decoding scheme) that the embodiment of the present invention provides, can be applied to Fast Ethernet, such as 400G Ethernet of future generation.Fig. 6 shows the framework of the 400G Ethernet of future generation of the coding and decoding scheme adopting the embodiment of the present invention to provide.

As shown in Figure 6, after encoder in PCS receives data by MII, the coded system (as 256B/257B coding or 256B/258B coding) provided according to the embodiment of the present invention is encoded, data after coding are exported to FEC module by encoder, FEC module inserts FEC verification sequence, and data are exported to scrambling module, scrambling module carries out scrambling process to data, and data are exported to Data dissemination module; Data dissemination module carries out distribution processor to data; Afterwards, periodically insert AM, and it is multiplexing to carry out FEC-Symbol.

Below in conjunction with Fig. 7 and Fig. 8, the embodiment of the present invention encoder provided and flow process of encoding are described, composition graphs 9 and Figure 10, the decoder that the description embodiment of the present invention provides and decoding process.

See Fig. 7, be the structural representation of the encoder that the embodiment of the present invention provides, this encoder can be realized by logical circuit, for performing the direct coding function that the above embodiment of the present invention provides.

As shown in Figure 7, this encoder 700 can comprise: precoding module 71, coding module 72, further also can comprise encoder state machine module 73.

Precoding module 71 can control 256 bit to be encoded code block (hereinafter referred to as MII_TXD) of code block (hereinafter referred to as MII_TXC) to input according to the MII of input and carry out precoding, and the code block to be encoded after precoding and MII_TXC are exported to coding module 72; Wherein, if comprise control code block in 256 bit MII_TXD, then comprised control code block is compressed;

The MII_TXC(MII_TXC that coding module 72 can export to coding module 72 according to precoding module 71 also can be directly inputted to coding module 72) and the coded format table that provides of the embodiment of the present invention (as Fig. 3, Fig. 4 or Fig. 5), determine physical layer encodes form, synchronization field numerical value, Block Type Field(block type territory) level and the numerical value of Block Type Field, the data of physical layer data form are mapped as according to the MII_TXD of (after namely decompressing) after the precoding that precoding module 71 exports by the physical layer encodes form determined, add synchronization field, the synchronization field numerical value that the numerical value of the synchronization field added is determined before being, to compress in the space that in precoding module 71 according to the level of Block Type Field and add Block Type Field, the Block TypeField numerical value that the numerical value of the Block Type Field added is determined before being, and output encoder result is to encoder state machine module 73,

Encoder state machine module 73, the coding result for being exported by coding module 72 is encoded to Ethernet data bag and exports.

The MII_TXC being input to precoding module 71 from MII is the MII_TXC of 4 tunnel 8 bits, the MII_TXD being input to precoding module 71 from MII is the MII_TXD of 4 tunnel 64 bits, and 8 bit MII_TXC and 64 bit MII_TXD one_to_one corresponding, 8 bit MII_TXC are used to indicate in 64 corresponding bit MII_TXD and often organize 8 bit code code blocks is data code block or control code block.Accordingly, 4 precoding unit 701 in precoding module 71, can be comprised, to carry out precoding processing to this 4 tunnel 8 bit MII_TXC and 64 bit MII_TXD respectively.

Below in conjunction with Fig. 8, the cataloged procedure of above-mentioned encoder 700 is described in detail.

See Fig. 8, be the schematic flow sheet of the coding method that the embodiment of the present invention provides, as shown in the figure, the method can comprise:

Step 801: the precoding module 71 in encoder 700 carries out precoding according to the 256 bit MII_TXD of the MII_TXC of input to input.Wherein, if comprise control code block in 256 bit MII_TXD, then wherein comprised control code block is compressed.

During concrete enforcement, each precoding unit 701 in precoding module 71, according to 4 bit MII_TXC Zhong mono-tunnel 8, tunnel 8 bit MII_TXC, can carry out precoding processing to corresponding 64 bit MII_TXD.Precoding processing can comprise: if comprise 8 bits in 64 bit MII_TXD to control code block, then this 8 bit is controlled code block boil down to 7 bit and control code block, namely, every 8 bits can compress 1 bit, 64 bit code blocks are compressible is the space of additional 8 bits of 56 bit code block, and this 8 bit space maps accordingly or retains in next code code block.All data code block (datablocks) for 64 bits then keeps this 64 bit code block constant.During concrete enforcement, can refer to the compression that table 3 carries out controlling code block.

The conversion table of 56 bit codewords after controlling code word in table 364 bit and compressing

Control code type	Input control information form	Form after precoding processing
			error	8’hfe	7’h1e
idle	8’h00	7’h07
			terminate	8’hfd	Compress 8bit space completely
sequence	8’h9c	Compress 8bit space completely
			sfd	8’hfb	Compress 8bit space completely

According to table 3, control code block by by control information boil down to 7 bit information of 8 bits, compress 1 bit space.If have terminate, sequence or sfd etc. to control code word in 64 bit code blocks, then directly can compress 8bit space.

Step 802: the coding module 72 in encoder 700, physical layer encodes form is determined according to MII_TXC, synchronization field numerical value, the level of Block Type Field and the numerical value of each level Block Type Field, according to the physical layer encodes form determined, the code block to be encoded after precoding is mapped as the data of physical layer data form, add synchronization field, the numerical value of this synchronization field is the synchronization field numerical value determined, to compress in the space that in precoding module 71 according to the level of BlockType Field and add Block Type Field, the numerical value of this Block Type Field is the Block Type Field numerical value determined, obtain coding result.

During concrete enforcement, when coding module 72 determines synchronization field numerical value, if determine that the MII_TXD of 256 bits comprises control code block according to the MII_TXC of 32 bits, then determine that synchronization field numerical value is the first numerical value, if determine that the MII_TXD of 256 bits is all data code block (datablocks) according to the MII_TXC of 32 bits, then determine that synchronization field numerical value is second value, such as, corresponding to aforesaid 256B/257B coded system, synchronization field is 1 bit, when the MII_TXD of 256 bits is all data code block (data blocks), synchronization field numerical value is defined as " 0 ", otherwise synchronization field numerical value is defined as " 1 ", corresponding to aforesaid 256B/258B coded system, synchronization field is 2 bits, when the MII_TXD of 256 bits is all data code block (data blocks), is defined as " 01 " by synchronization field numerical value, otherwise is defined as " 10 " by synchronization field numerical value.

For example, coding module 72 is when determining Block Type Field level and Block Type Field numerical value, if determine in 256 bit MII_TXD that 64 bits comprising more than 3 or 3 control code block according to 32 bit MII_TXC, then determine to adopt two-stage Block Type Field, wherein, it is all that to comprise the first order Block Type Field numerical value of MII_TXD that more than 3 or 3 64 bits control code blocks identical, second level Block Type Field numerical value can be arranged according to the type and/or position controlling code block and data code block (carrying when comprising data code block), described in concrete the same.Again for example, coding module 72 is when determining Block Type Field level and Block Type Field numerical value, if determine in 256 bit MII_TXD that comprising less than 2 or 2 64 bits controls code block according to 32 bit MII_TXC, then determine to adopt one-level Block Type Field, the numerical value of this Block Type Field can be arranged according to the type and/or position controlling code block and data code block (carrying when comprising data code block), concrete the same described in.Wherein, if comprise 1 64 bit Terminate block and 3, a 64 Bit data code block in 256 bit MII_TXD, then according to the position of the Terminate code word in Terminate block, first order block type territory numerical value is determined.

Alternatively, further, if according to MII_TXC, coding module 72 determines in MII_TXC that comprising at least 2 64 bits controls code block, and one of them control code block is Terminate block, then according to the position of the Terminate code word in Terminate block, determine instructions field numerical value, and compress in the space that in precoding module 71 and add instructions field and in this instructions field, add the instructions field numerical value determined; Wherein, this instructions field numerical value is for identifying the position of the Terminate code word in Terminate block.

Further, in order to obtain Ethernet data bag, after above-mentioned steps 802, the method shown in Fig. 8 can also comprise the following steps:

Step 803: the coding result that coding module 72 exports is encoded to Ethernet data bag and exports by the encoder state machine module 73 of encoder 700.

In order to ensure the data boundary correctness that has after the data encoding of a definite sequence, the embodiment of the present invention have employed certain sequence(order) state machine, carries out the coded treatment of state machine to the encoding block of alphabetic data.During concrete enforcement, the coding result that coding module 72 can export by encoder state machine module 73, the redirect order through state machine is encoded, further to be encoded to Ethernet data bag.

The structure of the packet in Ethernet is generally: the packet header s...... of packet header s/ bag data dddddd/ bag tail t/ frame gap ccccc/ next one bag.Code block not in accordance with correct bag order all can by the code word compiled as mistake, and coding just can reach certain error detecing capability like this, and the code block especially for packet boundary place code block type frequent variations has stronger error detection ability.According to above-mentioned Ethernet data pack arrangement, for example, Fig. 9 shows a kind of general encoder state machine state transition schematic diagram.

The Ethernet data bag meeting call format can be exported by the state transition shown in Fig. 9, such as:

Time under Data state, if input Data code word, then export this Data code word, thus the bag data field in Ethernet data bag is sequentially written in Data code word, and keeps current Data state; If input Terminate code word, then show to reach bag tail, then export this Terminate code word, thus be sequentially written in Terminate code word in Ethernet data bag, and jump to Control state;

Subsequently, under Control state, if input control code word, then export this control code word, thus be sequentially written in this control code word as number of frame gaps certificate after a upper bag tail; If again input control code word, then export this control code word, thus continue to be sequentially written in control code word at location between frames; If input sop code word, then export the packet header of this control code word as next packet, thus after interframe data, start a new packet.

In addition, under Data state, if input error code word or sop code word or control code word, then do not meet the call format (can not directly follow next packet header or frame gap after Data) of Ethernet data bag, thus jump to Error state; In like manner, under Control state, if input error code word or data code word or terminate code word, then do not meet the requirement of Ethernet data packet format, thus jump to Error state.

According to above state transition principle, for aforesaid 256B/257B encoding scheme, its coded state machines can be as shown in Figure 10.All conditions is selected to choose from the 1st 64 bit code blocks and the 4th 64 bit blocks, so just there is following redirect condition: D, D/T, S/D, D/S, D/C, D/E, T/D, T/S, T/E, T/C, C, E, C/E, E/C, wherein D represents Data, T represents Terminate code word, S represents Sop code word, C represents Control code word, E code Error code word.In addition, the state of all Errors of comprising can think Error.

Only comprise 256 bit code blocks of one of T0 ~ T7 code word corresponding be same state: D/T.Default redirect condition in Figure 10 representated by dotted arrow refer to other all be not the redirect condition shown in solid arrow, state machine will jump to E state (i.e. Error state) automatically.

Further, merging and the simplification of state can be carried out on the basis of Figure 10.As shown in figure 11, in figure state C represent jump to this state after can be control word according to conditional compilation, S represents that jumping to this state can be packet header Sop according to conditional compilation, D represents that jumping to this state can be data according to conditional compilation, T represents that jumping to this state can be that bag tail Terminate, E represent that jumping to this state can be encoded to erroneous words according to conditional compilation.S state and D state can according to circumstances merge further, and the state machine of this simplification simultaneously can add initial state Init according to the actual requirements.

According to above state transition principle, for aforesaid 256B/257B encoding scheme, its coded state machines can be as shown in figure 12.256B/258B encoding scheme is distinguished, so can find out that the Hamming distance between each coding codeword is not less than 2 in state machine redirect Figure 12 due to the synchronization field that have employed 2 bits between data and control information.

By describing above and can finding out, the 256B/257B encoding scheme that the embodiment of the present invention provides or 256B/258B encoding scheme, effectively can reduce time delay.The compressed encoding space of the encoding scheme that the embodiment of the present invention provides can well adapt to the structure of current main flow RS-FEC algorithm, by ensureing the Hamming distance that 256B/257B coding or 256B/258B encode between all control code words, ensure the error detecing capability of CRC32, meet network MTTFPA(Mean Time To False Packet Acceptance, the bag that lost efficacy receives average time) index.In addition, the coded state machines design optimization that provides of the embodiment of the present invention.

The 256B/257B encoding scheme that the embodiment of the present invention provides, when the error rate is 10^-12, MTTFPA can reach 1000.According to formula to calculating, the MTTFPA index of the 256B/258B encoding scheme that the embodiment of the present invention provides can reach the requirement of present Ethernet, and when the error rate is 10^-12, the network MTTFPA time reaches 10^17.Figure 13 shows the MTTFPA index schematic diagram of 256B/257B encoding scheme.

See Figure 14, be the structural representation of the decoder that the embodiment of the present invention provides, this decoder can be realized by logical circuit, for performing the decoding function of PCS in Fig. 5.

As shown in figure 14, this decoder 1400 can comprise: decoder module 141 and decompression module 142.

After decoder module 141 receives code block to be decoded, synchronization field numerical value, BlockType Field(block type territory according to this code block to be decoded) level and Block Type Field numerical value, determine the physical layer data form of this code block to be decoded, according to the physical layer data form of this code block to be decoded, obtain the control code block in this code block to be decoded and data code block (when comprising control code block and data code block), and generate MII control code block (hereinafter referred to as MII_TXC);

The control code block that decompression module 142 can get according to decoder module 141, this control code block is decompressed, it is 256 bit code blocks (hereinafter referred to as MII_TXD) that data code block in this code block to be decoded get the control code block after decompression and decoding module exports, and exports the MII_TXC of this MII_TXD and decoder module 141 generation.

From the MII_TXC that the MII_TXC of MII output is 4 tunnel 8 bits, be the MII_TXD of 4 tunnel 64 bits from the MII_TXD of MII output, and 8 bit MII_TXC and 64 bit MII_TXD one_to_one corresponding.When therefore exporting the data after decompressing after decompressing, can be decompressed and output processing to each circuit-switched data wherein by the decompression unit of 4 in decompression module 142 1421.

Below in conjunction with Figure 15, the cataloged procedure of above-mentioned encoder 1400 is described in detail.

See Figure 15, be the decoding process schematic diagram that the embodiment of the present invention provides, as shown in the figure, this flow process can comprise:

Step 1501: the decoder module 141 of decoder 1400 receives code block to be decoded, according to the synchronization field numerical value of this code block to be decoded, Block Type Field level and Block Type Field numerical value, determine the physical layer data form of this code block to be decoded, according to the physical layer data form of described code block to be decoded, obtain the control code block in this code block to be decoded and data code block (when comprising control code block and data code block), and generate MII_TXC.

For example, during specific embodiment, if determine, the synchronization field numerical value of this code block to be decoded is the first numerical value, then determine to comprise control code block in this code block to be decoded, if decoder module 141 determines that the synchronization field numerical value of this code block to be decoded is second value, then determine that this code block to be decoded is all data code block.Such as, for aforesaid 256B/257B coding and decoding scheme, when synchronization field numerical value is 0, represent in 257 bit code blocks of correspondence and comprise 4 64 Bit data code blocks, be all data code block (data blocks), when synchronization field numerical value is 1, represent in 257 bit code blocks of correspondence to there is control code block; For aforesaid 256B/258B coding and decoding scheme, when synchronization field numerical value is 01, represents in 257 bit code blocks of correspondence and comprise 4 64 Bit data code blocks, be all data code block (data blocks), when synchronization field numerical value is 10, represent in 257 bit code blocks of correspondence to there is control code block.Wherein, ditto, the bit number of the embodiment of the present invention to synchronization field is not restricted.

Alternatively, further, after determining that in 257 bit code blocks, existence controls code block, decoder module 141 can determine the Block Type Field level of this code block to be decoded according to the first order Block Type Field numerical value of this code block to be decoded, such as after obtaining the first order block type territory numerical value in this code block to be decoded, by comparing with the Block Type Field numerical value in the coded format table shown in Fig. 3, Fig. 4 or Fig. 5, the physical layer data form of this code block to be encoded can be determined.If determined in this code block to be decoded by above-mentioned steps and comprise one-level Block Type Field, then determine that comprising less than 2 or 2 in this code block to be decoded controls code block; If determine in this code block to be decoded and comprise at least two-stage Block Type Field, then determine that comprising more than 3 or 3 in this code block to be decoded controls code block.

Alternatively, further, if determine in this code block to be decoded and comprise one-level Block Type Field, and determine in the control code block in this code block to be decoded to there is Terminate block according to this Block Type Field numerical value, then decoder module 141 can determine the position of the terminate code word in Terminate block according to this block type numerical value.

Further, if decoder module 141 is according to the physical layer data form of this code block to be decoded, determine in this code block to be decoded and also comprise instructions field, then also according to the numerical value of this instructions field, can determine that in this code block to be decoded, Terminate block controls the position of the Terminate code word in code block.

Step 1502: the control code block in this code block to be decoded decompresses by the decompression module 142 of decoder 1400, control code block after decompression and the data code block in this code block to be decoded being exported is 256 bit code blocks (MII_TXD), and exports from MII the MII_TXC determined this MII_TXD and step 1501.

During concrete enforcement, this code block to be decoded is divided into 4 road code blocks to be decoded by decompression module 142, each decompression unit 1421 in decompression module 142, decompresses to each road in 4 road code blocks to be decoded in code block to be decoded; Wherein, if comprise 87 bits in code block to be decoded to control code block, then every 7 bits being controlled code block decompression is that 8 bits control code blocks; If include terminate code word, sequence code word or sfd code word in code block to be decoded, then decompress out 8 bit space.

It should be noted that; although mainly describe for the direct encoding and decoding of 256B/257B and the direct encoding and decoding of 256B/258B in the above embodiment of the present invention; but protection scope of the present invention is not restricted to this; such as; based on the above-mentioned encoding and decoding principle of the embodiment of the present invention; when use 4 bit is as synchronization field, its coding and decoding scheme can be described as 256B/260B coding and decoding scheme.

Based on identical technical conceive, the embodiment of the present invention additionally provides the device that can realize above-mentioned coding method, and this device can be with the one in lower device:

Multiport ethernet device (multi-port Ethernet device), described multiport ethernet device can be ethernet concentrator, ethernet router or Ethernet switch.Described multiport ethernet device comprises multiple port, and each port can comprise System on Chip/SoC, and described System on Chip/SoC can comprise MAC and PHY.Multiple MAC can also be incorporated into a MAC chip (MACchip) by described multiport ethernet device, and multiple PHY is incorporated into a PHY chip.Multiple MAC and multiple PHY also can be incorporated in a System on Chip/SoC by described multiport ethernet device.

This device can perform the coding method that the above embodiment of the present invention provides, and specific implementation does not repeat them here.

Based on identical technical conceive, the embodiment of the present invention additionally provides the device that can realize above-mentioned coding/decoding method, and this device can be with the one in lower device::

This device can perform the coding/decoding method that the above embodiment of the present invention provides, and specific implementation does not repeat them here.。

In sum, the above embodiment of the present invention is when physical layer encodes, code block determination physical layer encodes form, synchronization field numerical value, the level in block type territory and the numerical value in each level block type territory is controlled according to MII, according to the physical layer encodes form determined, the code block to be encoded after precoding is mapped as physical layer data form, thus realizes to encode to 256 bit code blocks.Due to according to 256 bit code block compressible space, the block type carrying out multi-layer divides, thus ensure that the Hamming distance between each 256 bit code block to be encoded is not less than 4 in an encoding process, and can be the School Affairs space that RS-FEC forward error correction algorithm provides enough.

The present invention describes with reference to according to the flow chart of the method for the embodiment of the present invention, equipment (system) and computer program and/or block diagram.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can be provided to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing device, make the function that the instruction that performed by the processor of this computer or other programmable data processing device can be specified in a flow process in realization flow figure or multiple flow process and/or block diagram square frame or multiple square frame.

These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing device, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.

These computer program instructions also can be loaded in computer or other programmable data processing device, make on computer or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computer or other programmable devices is provided for the step realizing the function of specifying in a flow process of flow chart or a square frame of multiple flow process and/or block diagram or multiple square frame.

Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.

Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.

Claims

1. a coding method, is characterized in that, comprising:

2. the method for claim 1, it is characterized in that, described one 256 bit code block to be encoded comprises 4 tunnel 64 bit code block to be encoded, described MII controls code block and comprises 4 tunnel 8 bit MII control code blocks, and described 4 tunnel 8 bit MII control code block and described 4 tunnel 64 bit code block one_to_one corresponding to be encoded;

3. method as claimed in claim 1 or 2, is characterized in that, described according to described MII control code block determination synchronization field numerical value, comprising:

4. the method according to any one of claim 1-3, is characterized in that, described according to the described MII control level in code block determination block type territory and the numerical value in described block type territory, comprising:

5. method as claimed in claim 4, is characterized in that, if control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising N number of 64 bits controls code block, then determine to adopt one-level block type territory, comprising:

6. the method according to any one of claim 1-3, is characterized in that, described according to the described MII control level in code block determination block type territory and the numerical value in described block type territory, comprising:

7. the method according to any one of claim 4-6, is characterized in that, also comprises:

8. the method according to any one of claim 1-6, is characterized in that, described synchronization field width is N bit, N >=1.

9. an encoder, is characterized in that, comprising:

10. encoder as claimed in claim 9, it is characterized in that, described one 256 bit code block to be encoded comprises 4 tunnel 64 bit code block to be encoded, described MII controls code block and comprises 4 tunnel 8 bit MII control code blocks, and described 4 tunnel 8 bit MII control code block and described 4 tunnel 64 bit code block one_to_one corresponding to be encoded;

11. encoders as claimed in claim 9, it is characterized in that, described coding module specifically for, if determine in described one 256 bit code block to be encoded according to described MII control code block and comprise control code block, then determine that described synchronization field numerical value is the first numerical value, if determine in described one 256 bit code block to be encoded according to described MII control code block and do not comprise control code block, then determine that described synchronization field numerical value is second value, described second value is different from described first numerical value.

12. encoders as claimed in claim 9, it is characterized in that, described coding module specifically for, if control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising N number of 64 bits controls code block, described N be less than 3 positive integer, then determine adopt one-level block type territory; Determine the numerical value in first order block type territory in described one-level block type territory, the numerical value in the first order block type territory that the numerical value in described first order block type territory is corresponding from the 2 256 bit code block to be encoded of reception is different, described 2 256 bit code block to be encoded comprises Y 64 bits and controls code block, described Y be less than 3 positive integer, described Y 64 bits control code blocks are different from the type that described N number of 64 bits control code block, or position is different, or the position of the identical control code block of type is different.

13. encoders as claimed in claim 9, it is characterized in that, described coding module specifically for, if 64 bits comprising 1 termination type in described one 256 bit code block to be encoded control code block Terminate block and 3 64 Bit data code blocks, then according to the position of the Terminate code word in described Terminate block, determine the numerical value in first order block type territory in described one-level block type territory.

14. encoders as described in claim 9 or 10, it is characterized in that, described coding module specifically for, if control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising M 64 bits controls code block, described M be greater than 2 and be less than 5 positive integer, then determine adopt two-stage block type territory, determine the numerical value in first order block type territory in described two-stage block type territory, the numerical value in the first order block type territory that the numerical value in described first order block type territory is corresponding with the 3 256 bit code block to be encoded of reception is identical, and the numerical value in the first order block type territory corresponding from the 4 256 bit code block to be encoded received is different, described 3 256 bit code block to be encoded comprises X 64 bits and controls code block, described X be greater than 2 and be less than 5 positive integer, described 4 256 bit code block to be encoded comprises Z 64 bits and controls code blocks, described Z be less than 3 positive integer, determine the numerical value in block type territory, the second level in described two-stage block type territory, the numerical value in the block type territory, the second level that the numerical value in block type territory, the described second level is corresponding from the 5 256 bit code block to be encoded of reception is different, described 5 256 bit code block to be encoded comprises Q 64 bits and controls code block, described Q be greater than 2 and be less than 5 positive integer, described Q 64 bits control code blocks are different from the type that described M 64 bits control code block, or position is different, or the position of the control code block that type is identical is different, the numerical value in the first order block type territory that the numerical value in the first order block type territory that described 5 256 bit code block to be encoded is corresponding is corresponding with described one 256 bit code block to be encoded is identical.

15. encoders according to any one of claim 12-14, it is characterized in that, described coding module also for, if control code block according to described MII to determine in described one 256 bit code block to be encoded that comprising at least 2 64 bits controls code block, and one of them control code block is Terminate block, then according to the position of the Terminate code word in Terminate block, determine instructions field numerical value, and instructions field is added in the space that described precoding module is obtained by compression, the numerical value of the instructions field of described interpolation for described in the instructions field numerical value determined, the instructions field numerical value of described interpolation is for identifying the position of the Terminate code word in Terminate block.

16. encoders according to any one of claim 9-14, it is characterized in that, described synchronization field width is N bit, N >=1.

17. 1 kinds of coding/decoding methods, is characterized in that, comprising:

Receive the first code block to be decoded;

The control code block got is decompressed;

18. methods as claimed in claim 17, is characterized in that, the numerical value in the described synchronization field numerical value according to described first code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described first code block to be decoded, comprising:

Described method also comprises:

Receive the 3rd code block to be decoded;

19. methods as claimed in claim 17, is characterized in that, the numerical value in the described synchronization field numerical value according to described first code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described first code block to be decoded, comprising:

20. methods as claimed in claim 19, is characterized in that, the numerical value in the described synchronization field numerical value according to described first code block to be decoded, block type territory level and described block type territory, determine the physical layer data form of described first code block to be decoded, also comprise:

21. methods as claimed in claim 17, is characterized in that, if according to the physical layer data form of described first code block to be decoded determined, determine in described first code block to be decoded and also comprise instructions field, then also comprise:

22. methods as claimed in claim 17, is characterized in that, are describedly decompressed by control code block in described first code block to be decoded, comprising:

23. methods according to any one of claim 17-22, it is characterized in that, described synchronization field width is N bit, N >=1.

24. 1 kinds of decoders, is characterized in that, comprising:

25. decoders as claimed in claim 24, is characterized in that, described decoder module specifically for, if the synchronization field numerical value of described first code block to be decoded is the first numerical value, then determine to comprise control code block in described code block to be decoded;

26. decoders as claimed in claim 24, it is characterized in that, described decoder module specifically for, if determine in described first code block to be decoded according to the synchronization field numerical value of described first code block to be decoded and comprise control code block, then determine the block type territory level of described first code block to be decoded according to the numerical value in the one-level block type territory of described first code block to be decoded; If the level determining the block type territory of described first code block to be decoded is one-level, then determine in described first code block to be decoded comprise N number of 64 bits control code blocks, described N be less than 3 positive integer; If determine, the level in the block type territory of described first code block to be decoded is at least two-stage, then determine in described first code block to be decoded that comprising M 64 bits controls code blocks, described M be greater than 2 and be less than 5 positive integer.

27. decoders as claimed in claim 26, it is characterized in that, described decoder module also specifically for, if the level determining the block type territory of described first code block to be decoded is one-level, and controlling to there is Terminate block in code block according to 64 bits that the numerical value in the one-level block type territory determined is determined in described first code block to be decoded, then the numerical value in the one-level block type territory determined described in basis determines the position of the terminate code word in Terminate block.

28. decoders as claimed in claim 24, it is characterized in that, described decoder module specifically for, if according to the physical layer data form of described first code block to be decoded determined, determine in described first code block to be decoded and also comprise instructions field, then according to the numerical value of described instructions field, determine that in described first code block to be decoded, Terminate block controls the position of the Terminate code word in code block.

29. decoders as claimed in claim 24, it is characterized in that, described decompression module comprises 4 decompression units, described first code block to be decoded is divided into 4 tunnel second code blocks to be decoded by described decompression module, and each described decompression unit performs following steps to described 4 tunnel second code blocks to be decoded respectively: