CN111385058A

CN111385058A - Data transmission method and device

Info

Publication number: CN111385058A
Application number: CN201811610664.4A
Authority: CN
Inventors: 汪伊明; 罗勇
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-12-27
Filing date: 2018-12-27
Publication date: 2020-07-07

Abstract

The embodiment of the application provides a method and a device for data transmission, wherein the method comprises the following steps: FEC encoding is carried out on a data code block sequence output by a physical encoding sublayer on a Forward Error Correction (FEC) encoding processing sublayer, wherein m data code blocks are used as a group to generate n FEC check code blocks, and m and n are both positive integers; distributing the m data code blocks to a first physical channel group; distributing the n FEC check-code blocks to a second physical channel group. In other words, after the data code block is sent to the first physical channel group, the FEC check code block of the data code block can only be distributed to the physical channel group other than the first physical channel group, the FEC check code block uses an additional transmission channel separated from the space, and is isolated and independently transmitted from the data code block.

Description

Data transmission method and device

Technical Field

The embodiment of the application relates to the field of communication, in particular to a method and a device for data transmission.

Background

Forward Error Correction (FEC) coding and decoding is a technique used in a communication system to improve the performance of a transmission system. The FEC coding and decoding algorithm and processing device are introduced to the source end and the destination end of the transmission system, and the transmission source end needs to additionally transmit check overhead data generated by FEC coding in the transmission system. In a typical single-channel communication transmission system, transmission of original information data and FEC check overhead data is mainly achieved by increasing the line transmission rate. For example, a typical Reed-solomon (Reed-solomon) RS (255,239) codec, the original 239 bytes of information are FEC encoded to 255 bytes, and the transmission system transmits the encoded data at a rate that is higher than the rate required without encoding.

With the development of network technology, the bandwidth rate of the information transmission interface of the optical communication system is developing from 10Gbps and 40Gbps to 100Gbps, 400Gbps, even 1Tbps and 1.6 TGbps. Transmitting such a huge amount of information per unit time requires increasing the transmission capacity of the system in several feasible dimensions: firstly, the symbol transmission rate in a single-channel transmission system is improved, secondly, a larger information amount is carried in one symbol transmission, and finally, a multi-channel transmission system is adopted.

Currently, the Institute of Electrical and Electronics Engineers (IEEE) considers and gradually adopts high-order code modulation techniques such as Pulse Amplitude Modulation (PAM) 4, PAM8, PAM16, Carrierless Amplitude phase modulation (CAP) 16, which can directly detect and receive, to increase the information carrying capacity on symbols, for example, designing compact interface transmission modules such as 100 Gigabit Ethernet (GE) and 400 GE. For future 400GE and higher information rate interfaces, a mode of independently improving single-channel symbol transmission capability gradually faces a bottleneck, and multi-channel and high-order level coding modulation technologies become another two main dimensions of subsequent development and need to be reasonably compromised in terms of the three dimensions. The high-order coded modulation introduces larger information quantity into one transmission symbol, which causes the deterioration of the signal-to-noise ratio of the system, greatly reduces the transmission error code performance of the system, and the system is more easily influenced by the transmission error code. Under such a background, the introduction of FEC coding is an inevitable consideration, and how to reasonably combine FEC coding and decoding technology with the current transmission system becomes an important research topic for transmitting FEC check overhead data.

In the transmission method of FEC check overhead data in the prior art, original information data and FEC check overhead data are transmitted through one channel between two communicating entities, only a traditional Non Return to Zero (NRZ) to Zero code line transmission pattern is used, which increases the NRZ line transmission rate after FEC to 10.3125 Baud (Baud), compared with the transmission rate of the same NRZ line without FEC, because no high-order coding modulation is used, the data flow rate that can be actually transmitted is reduced, and the available bandwidth that can actually transmit the original information data is reduced by transmitting FEC check overhead data through occupying the bandwidth that transmits the original information data.

Another transmission method for FEC check overhead data in the prior art is to compress the synchronization header redundancy overhead of a coding block based on 64/66b coding, and after compressing a 64/66b coding block, the coding block becomes a 64/65b coding block, so that 1-bit redundancy information is removed. And then, the Fire Code FEC (2112, 2080) is adopted to generate 2080 bit original information data and 32 bit FEC check overhead data together, and because the added FEC check overhead data is offset with the compression of redundancy overhead of a synchronous head in the process of Code conversion from an 64/66b coding block to a 64/65b, the transmission rate of the NRZ line is not actually improved. The FEC overhead carrying capacity provided by the method is limited, the selected FEC error correction capacity is limited, and the method is not suitable for the situation of higher actual line error rate, in particular to a system introduced with a high-order modulation code pattern. In addition, the implementation method needs to perform compression on each channel independently, if the compression is distributed to 4 channels, 4 times of coding and decoding delay is introduced, and relatively high FEC coding and decoding delay is introduced to a multi-channel system, so that the method is not suitable for occasions with low delay requirements. Especially, for two entities communicating through a Wireless Fidelity (WiFi) link, how to transmit FEC check overhead data is a problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a method and a related device for transmitting data, wherein a data code block is transmitted through a first physical channel group, an FEC check code block is transmitted through a second physical channel group, the FEC check code block uses an additional transmission channel with spatial separation, and the data code block and the FEC check code block are isolated and independently transmitted. By the design, the FEC check overhead data of the data code block does not occupy the bandwidth of a channel for transmitting the data code block, and the normal transmission of the data code block is powerfully guaranteed.

In a first aspect, an embodiment of the present application provides a method for sending data, where the method is used for a first device, where at least a first physical channel group and a second physical channel group are established between the first device and a second device, and the method includes: the first step is to perform FEC encoding on a data code block sequence output by a physical encoding sublayer on a Forward Error Correction (FEC) encoding processing sublayer, wherein m data code blocks are taken as a group, and n FEC check code blocks are generated, wherein m and n are positive integers. Then, the m data code blocks are distributed to a first physical channel group and the n FEC check code blocks are distributed to a second physical channel group, without being divided into front and back.

In one design, the method further includes: the first device distributes the M data code blocks to M virtual lanes of a first virtual lane group and distributes the N FEC check code blocks to N virtual lanes of a second virtual lane group, wherein M and N are positive integers; multiplexing the data distributed onto the first virtual channel group and the data distributed onto the second virtual channel group to the first physical channel group and the second physical channel group, respectively.

In one design, the distributing the M data code blocks to M virtual lanes of a first virtual lane group and the distributing the N FEC check code blocks to N virtual lanes of a second virtual lane group further includes: and periodically inserting alignment mark code blocks into code block streams borne on the M + N virtual channels of the first virtual channel group and the second virtual channel group, wherein each alignment mark code block also marks the serial number of the virtual channel where the alignment mark code block is located, and the alignment mark code blocks are used for aligning, recombining and restoring the code block streams after a receiving end acquires the code block streams.

In one design, the FEC encoding, at the FEC encoding processing sublayer, a data code block sequence output by the physical encoding sublayer is FEC encoded by taking m data code blocks as a group to generate n FEC check code blocks, and then the method further includes: generating i idle code blocks, the idle code blocks including idle information bits; distributing the i idle code blocks over N virtual lanes of the first virtual lane group, the data distributed over the first virtual lane group including the N FEC check code blocks and the i idle code blocks.

In one design, the multiplexing the data distributed to the first virtual channel group to a first physical channel group, and multiplexing the data distributed to the second virtual channel group to a second physical channel group, and then further includes: and transmitting all the data multiplexed on the first physical channel group and all the data multiplexed on the second physical channel group to a receiving end, namely a second device through a physical transmission medium.

In one design, the multiplexing the data distributed to the first virtual channel group to the first physical channel group and the multiplexing the data distributed to the second virtual channel group to the second physical channel group further includes: and discarding i idle code blocks in all data multiplexed on the second physical channel group, and transmitting all data multiplexed on the first physical channel group and n FEC check code blocks in all data multiplexed on the second physical channel group to a receiving end through a physical transmission medium.

In one design, the m data code blocks and the n FEC check code blocks are distinguished by different synchronization headers.

In a second aspect, an embodiment of the present application provides a method for receiving data, where at least a first physical channel group and a second physical channel group are established between a second device and a first device, and the method includes the following steps: the second equipment receives first data from a first physical channel group and separates m data code blocks from the first data, wherein m is a positive integer; receiving second data from a second physical channel group, and separating n FEC check code blocks from the second data stream, wherein n is a positive integer; then, the n FEC check code blocks are used for correcting the error codes in the m data code blocks on the FEC coding processing sublayer, and the m data code blocks after error code correction are input into the physical coding sublayer.

In one design, the method further includes: searching for alignment mark code blocks inserted in M + N code block streams consisting of data code block streams on M virtual channels and FEC check code blocks on N virtual channels; and code block sequences for code block distribution on the M + N virtual channels are aligned and recombined according to the alignment mark code blocks to obtain M data code blocks and N FEC check code blocks.

In one design, the method further includes: searching for an alignment mark code block inserted in a code block stream consisting of the data code block stream on the M virtual channels and the FEC check code blocks on the N virtual channels; and aligning and recombining the code block streams on the M + N virtual channels according to the alignment mark code blocks to obtain M data code blocks, N FEC check code blocks and i idle code blocks.

In a third aspect, an embodiment of the present application further discloses a first device, where the first device includes: an FEC encoding unit, configured to perform FEC encoding on a data code block sequence output by a physical coding sublayer on a forward error correction FEC encoding processing sublayer, with m data code blocks as a group, and generate n FEC check code blocks, where m and n are positive integers; a distribution unit configured to distribute the m data code blocks to a first physical channel group; distributing the n FEC check-code blocks to a second physical channel group.

In one design, the distribution unit is further configured to: distributing the M data code blocks to M virtual channels of a first virtual channel group, and distributing the N FEC check code blocks to N virtual channels of a second virtual channel group, wherein M and N are positive integers; the device further comprises: a multiplexing unit, configured to multiplex the data distributed to the first virtual channel group and the data distributed to the second virtual channel group to the first physical channel group and the second physical channel group, respectively.

In one design, the apparatus further comprises: and the alignment unit is used for periodically inserting alignment mark code blocks into code block streams borne on the M + N virtual channels of the first virtual channel group and the second virtual channel group, wherein each alignment mark code block also marks the serial number of the virtual channel where the alignment mark code block is located, and the alignment mark code blocks are used for alignment recombination recovery after a receiving end acquires the code block streams.

In one design, the apparatus further comprises: a generating unit configured to generate i idle code blocks, where the idle code blocks include idle information bits; the distribution unit is further configured to distribute the i idle code blocks to N virtual lanes of the first virtual lane group, where the data distributed to the first virtual lane group includes the N FEC check code blocks and the i idle code blocks.

In a fourth aspect, an embodiment of the present application further discloses a second device, including: a first receiving unit, configured to receive data from a first physical channel group, and separate m data code blocks from the data, where m is a positive integer; a second receiving unit, configured to receive data from a second physical channel group, and separate n FEC check code blocks from the data stream, where n is a positive integer; an FEC decoding unit, configured to correct, at an FEC encoding processing sublayer, errors in the m data code blocks using the n FEC check code blocks; and the sending unit is used for inputting the m data code blocks with corrected bit errors into the physical coding sublayer.

In one design, the second device further comprises: a first search searching unit, configured to search for an alignment marker code block inserted in M + N code block streams composed of data code block streams on M virtual channels and FEC check code blocks on N virtual channels, where data on the first virtual channel group and data distributed to the second virtual channel group are multiplexed to the first physical channel group and the second physical channel group, respectively; and the recombination unit is used for carrying out alignment recombination on code block sequences for code block distribution on the M + N virtual channels according to the alignment mark code blocks to obtain M data code blocks and N FEC check code blocks.

In one design, the second device further comprises: a second searching unit, configured to search for an alignment mark code block inserted in a code block stream composed of the data code block streams on the M virtual channels and the FEC check code blocks on the N virtual channels; and the recombination unit is used for aligning and recombining the code block streams on the M + N virtual channels according to the alignment mark code blocks to obtain M data code blocks, N FEC check code blocks and i idle code blocks.

In a fifth aspect, an embodiment of the present application further discloses a first device, including: an input device, an output device, a memory, and a processor; wherein the processor performs the method of any one of the first aspect.

In a sixth aspect, an embodiment of the present application further discloses a second device, which is characterized by including: an input device, an output device, a memory, and a processor; wherein the processor performs the method of any one of the second aspects.

In a seventh aspect, this application further discloses a computer-readable storage medium, which includes instructions that, when executed on a device, cause the device to perform the method according to any one of the foregoing first aspect or second aspect.

In an eighth aspect, this application further discloses a computer program product containing instructions, which when run on a device, causes the device to perform the method according to any one of the first or second aspects.

According to the technical scheme, the embodiment of the application has the following advantages:

because the data code block and the FEC check code block are separately transmitted to the first physical channel group and the second physical channel group, the FEC check code block uses additional transmission channels which are separated from each other in space, and is isolated and independently transmitted from the data code block, the design ensures that FEC check overhead data of the data code block does not occupy the bandwidth of the channel for transmitting the data code block, and the normal transmission of the data code block is powerfully ensured.

Drawings

FIG. 1 is a schematic diagram of an application scenario of an embodiment of the present application;

fig. 2 is a schematic flow chart diagram of a data processing method according to an embodiment of the present application;

fig. 3 is a schematic flow chart diagram of another data processing method according to an embodiment of the present application;

fig. 4 is a schematic flow chart diagram of another data processing method according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of another data processing apparatus according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of another data processing apparatus according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of another data processing apparatus according to an embodiment of the present application.

Detailed Description

In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one skilled in the art from the embodiments given herein are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a typical scenario in which the embodiment of the present application may be applied, and the embodiment of the present application may be applied to a Wireless Local Area Network (WLAN), where a standard adopted by the WLAN at present is IEEE802.11 series. A WLAN may include multiple Access Points (APs) or Stations (STAs).

An AP is also referred to as a wireless access point or hotspot, etc. The AP is an access point for a mobile subscriber to enter a wired network, and is mainly deployed in a home, a building, and a campus, and typically has a coverage radius of several tens of meters to hundreds of meters, and may be deployed outdoors. The AP acts as a bridge connecting the network and the wireless network, and mainly functions to connect the wireless network clients together and then to access the wireless network to the ethernet. Specifically, the AP may be a terminal device or a network device with a wireless fidelity (WiFi) chip. Optionally, the AP may be a device supporting 802.11ax standard, and further optionally, the AP may be a device supporting multiple WLAN standards such as 802.11ac, 802.11n, 802.11g, 802.11b, and 802.11 a.

The STA may be a wireless communication chip, a wireless sensor, or a wireless communication terminal. For example: the mobile phone supporting the WiFi communication function, the tablet computer supporting the WiFi communication function, the set top box supporting the WiFi communication function, the smart television supporting the WiFi communication function, the smart wearable device supporting the WiFi communication function, the vehicle-mounted communication device supporting the WiFi communication function and the computer supporting the WiFi communication function. Optionally, the station may support an 802.11ax system, and further optionally, the station supports multiple WLAN systems such as 802.11ac, 802.11n, 802.11g, 802.11b, and 802.11 a.

One component is the FEC module for an AP or STA. The FEC module is a transmission error control system that may include hardware and software subcomponents. The FEC module may have a transmitter section and a receiver section and these two sections may work together to correct errors. The transmitter component may employ an FEC algorithm to generate redundant data from the original data block and may transmit the redundant data and the original data block to an intended recipient. The receiver component may employ the same or similar algorithms to generate its redundant data version. The difference between the two versions of the redundant data is indicative of a transmission error. In this case, the receiver component of the FEC module may use the redundant data to correct errors and recover the original data block. The FEC module may be implemented using a hardware module, a software module, or a combination thereof.

The above is only an example, and is not limited to a local area network, and the embodiment of the present application is applicable to any transmitting end and receiving end that start an FEC function.

As shown in fig. 2, an embodiment of the data processing method provided by the present invention may specifically include the following steps:

201. and FEC encoding the data code block sequence output by the physical coding sublayer on a forward error correction FEC encoding processing sublayer by taking m data code blocks as a group to generate n FEC check code blocks, wherein m and n are positive integers.

In the embodiment of the application, after a Physical Coding Sub-layer (PCS) is subjected to block Coding, a data code block sequence is output, where the data code block sequence includes a plurality of data code blocks, where a data code block refers to a code block carrying raw information data and having a certain format, where the carried raw information is payload data subjected to FEC Coding, and the data code block sequence is input to an FEC Coding processing Sub-layer, where the block Coding performed on the PCS may specifically be 64/66b Coding, or 256/(257+ P) b or 512/(513+ P) b with lower overhead, where P is a natural number, which is not limited in the present invention.

In the embodiment of the application, the data code blocks output on the PCS physical coding processing sublayer have strict and definite precedence order, which is called a data code block sequence. Selecting continuous m data code blocks in a data code block sequence as a group for FEC coding, and performing FEC calculation on data carried in the m data code blocks to generate FEC check overhead data, wherein the FEC check overhead data are encapsulated into n FEC check code blocks by being covered with specific type indication and (or) synchronization header information, wherein m and n are positive integers, the value of the positive integers is related to the FEC coding mode selected by the FEC coding processing sub-layer, the value of the positive integers is not limited here, and in addition, the process of FEC coding is described in the prior art, and is not described herein again.

It should be noted that, in the embodiment of the present application, specifically, a plurality of data code blocks covered by the FEC coding sub-layer FEC coding frame may be provided, and values of the data code blocks are not limited, which is denoted by m in the embodiment of the present application, and all the plurality of data code blocks are sent to the FEC coding processing sub-layer for FEC coding, so as to generate a plurality of FEC check code blocks, which is denoted by n in the embodiment of the present application.

It should be noted that, in this embodiment of the present application, the FEC coding processing sublayer is responsible for performing FEC calculation on m coding blocks to generate n FEC check code blocks, where the data code block and the FEC check code block are clearly distinguished from each other by a known value on the FEC coding processing sublayer, and the FEC coding processing sublayer may specifically perform data transmission with other modules in a parallel or time-separated serial transmission manner with spatially separated, according to the known distinction between the two coding blocks, which is not limited in this embodiment of the present application. When the FEC coding processing sublayer and other modules perform data transmission with each other, the target module needs to be informed of different indications of the block types. The FEC codec sublayer is relatively independent of the Physical Medium Attachment sublayer (PMA), and requires explicit indication to distinguish between data codeblocks and FEC check codeblocks at the interface. The PMA distributes the data blocks and the check blocks to different virtual channels, respectively, according to the differentiation indication, as will be described later. In the case of the spatially separated mode, this is actually distinguished by different separate interfaces, and in the case of the temporally separated serial mode, this is distinguished by different time slices. Whether in a spatially separated parallel or a temporally separated serial manner, an additional indication signal may be added to distinguish the indication, for example, by encoding the block header information differently for the FEC check block.

For example, the data code block uses synchronization headers "0 b 10" and "0 b 01", specifically, the synchronization header "0 b 10" indicates that the data code block includes control characters, the synchronization header "0 b 01" indicates that the data code block does not include control characters, all the data code blocks are data characters at this time, the FEC check code block uses synchronization headers "0 b 00" and "0 b 11" alternately, specifically, the synchronization header "0 b 00" indicates an odd FEC check code block, FEC check overhead data is in the block, the synchronization header "0 b 11" indicates an even FEC check code block, and FEC check overhead data is in the block. In this operation mode, the synchronization header of the data code block and the FEC check code block arranged on the FEC encoding processing sublayer has FEC frame period regularity, and can be used to mark the data code block and the FEC check code block, and the synchronization header can be distributed to the downward direction block and upward direct to identify the data code block and the FEC check code block.

202. Distributing the m data code blocks to a first physical channel group, and distributing the n FEC check code blocks to a second physical channel group.

In this embodiment, the FEC check code block belonging to a certain data code block cannot go through the same channel as the data code block, for example, after the data code block is sent to the first physical channel group, the FEC check code block of the data code block can only be sent to a physical channel group other than the first physical channel group. After the data code block is distributed to the second physical channel group, the FEC check code block of the data code block can be distributed to only the physical channel groups other than the second physical channel group. Specifically, it is not limited to which channel the data code block or the FEC check code block is distributed first.

It can be seen that, in the embodiment of the present application, the data code block and the FEC check code block are separately transmitted to the first physical channel group and the second physical channel group, the FEC check code block uses an additional transmission channel separated from the data code block, and is isolated and independently transmitted from the data code block.

In one implementation, the data code block and the FEC check code may also not be distributed to the first physical channel group and the second physical channel group immediately after step 201, but are sent to the virtual channel group and then multiplexed to the physical channel group, specifically as follows:

203: distributing the M data code blocks to M virtual lanes of a first virtual lane group, and distributing the N FEC check code blocks to N virtual lanes of a second virtual lane group, wherein M and N are positive integers.

In this embodiment of the present application, a plurality of virtual channel groups are divided into a first virtual channel group and a second virtual channel group, and a data code block and an FEC check code block are respectively distributed to different virtual channel groups.

The first virtual channel group comprises M virtual channels, the second virtual channel group comprises N virtual channels, wherein M is equal to M × t 1M _ max, M _ max is equal to M × t2, t1 and t2 are positive integers, i.e. the positive integer multiple of M is equal to or greater than M, the physical meaning is that the number of virtual channels of the first virtual channel group provides a transmission bearer capability greater than or equal to the transmission bearer requirement of the data code block, N is equal to the physical meaning that N × t1 is equal to N _ max, N _ max is equal to or greater than N × t2, t1 and t2 are positive integers, i.e. the positive integer multiple of N is equal to or greater than N, the physical meaning that the number of virtual channels of the second virtual channel group provides a transmission bearer capability greater than or equal to the transmission bearer requirement of the check code block N _ M _ × N > N × t ×, M × t × is equal to N × M _ max, the above- × M × N is used to describe the above- × N, and the above- × N is used as an empty code block.

In the embodiment of the present application, step 203 can also be understood as the following two steps:

a1, distributing M data code blocks to M virtual channels of a first virtual channel group;

and A2, distributing the N FEC check code blocks to the N virtual channels of the second virtual channel group.

When the step a1 and the step a2 are executed, there is no chronological order, the step a1 may be executed first and then the step a2 is executed, the step a2 may be executed first and then the step a1 is executed, and the steps a1 and a2 may be executed at the same time, which is not limited in the embodiment of the present application.

In this embodiment of the present application, distributing the data code block to the first virtual channel group and distributing the FEC check code block to the second virtual channel group may be specifically performed on a PMA sublayer, and the data distributed to the first virtual channel group and the data distributed to the second virtual channel group are processed according to the following step 203, which is described in detail below.

204. Multiplexing the data distributed to the first virtual channel group and the data distributed to the second virtual channel group to a first physical channel group and a second physical channel group, respectively.

It should be noted that, after step 202 is completed in the embodiment of the present application, the following steps may also be included: the method comprises the steps that alignment mark code blocks are periodically inserted into code block streams carried on a first physical channel and a second physical channel, wherein each alignment mark code block also marks the serial number of the physical channel where the alignment mark code block is located, and the alignment mark code blocks are used for aligning, recombining and restoring the code block streams after the code block streams of the first physical channel and the second physical channel are obtained by a receiving end. The code block streams carried on the first physical channel and the second physical channel include m data code blocks and n FEC check code blocks in each FEC frame, and after the code block stream is periodically inserted with Alignment mark code blocks (Alignment Marker), the receiving end can perform Alignment recombination recovery according to the Alignment mark code blocks. In addition, the alignment mark code block may also be used to mark the number information of the first physical channel where the alignment mark code block is located and the number information of the second physical channel where the alignment mark code block is located.

Specifically, one design is to multiplex data distributed to the first virtual channel group and data distributed to the second virtual channel group to at most H interfaces of the first physical channel group and at most K interfaces of the second physical channel group, respectively. Where M is an integer multiple of H and N is an integer multiple of K.

The data distributed to the first physical channel group in step 203 described herein refers to m data code blocks, and may further include necessary spare code blocks in some embodiments of the present invention, and the data distributed to the second physical channel group refers to n FEC check code blocks, and may further include necessary spare code blocks in some embodiments of the present invention.

In the embodiment of the present application, step 202 can also be understood as the following two steps:

b1, multiplexing M data bit streams distributed to the first physical channel group onto at most H interfaces of the first physical channel group;

and B2, multiplexing the N data bit streams distributed to the second virtual channel group to at most K interfaces of the second physical channel group respectively.

When the step B1 and the step B2 are executed, there is no chronological order, the step B1 may be executed first and then the step B2 is executed, the step B2 may be executed first and then the step B1 is executed, and the steps B1 and B2 may be executed at the same time, which is not limited in the embodiment of the present application.

It should be noted that, for steps B1 and B2, taking step B1 as an example, M data bit streams are multiplexed from the first virtual channel group to at most H interfaces of the first physical channel group, specifically, the multiplexing of M data bit streams may be simultaneously multiplexed to at most H interfaces, and M is an integer multiple of H, and the multiplexing of M data bit streams may be multiplexed to H interfaces of the first physical channel group, or may be multiplexed to H1 and H2 specific interfaces of the first physical channel group that are less than H. For the case of less than H, specific H1 electrical interfaces and H2 optical interface are taken as an example for explanation. In the embodiment of the present application, multiplexing may be bit-rate-variable multiplexing, where bit-rate-variable multiplexing refers to a multiplexing method of multiplexing input data bit streams and then outputting the multiplexed data bit streams, for example, 4 input data bit streams may be input, and if the rate-variable ratio is 4:3, 3 data bit streams may be output.

In the embodiment of the present application, the specific interface form of the physical channel group may be an electrical interface and an optical interface, an optical module is connected between the electrical interface and the optical interface, and the optical module is used for implementing photoelectric conversion and electro-optical conversion. Specifically, the specific form of at most H interfaces of the first physical channel group may be H1 electrical interfaces and H2 optical interfaces, and the specific form of at most K interfaces of the second physical channel group may be K1 electrical interfaces and K2 optical interfaces, that is, the first physical channel group includes H1 electrical interfaces and H2 optical interfaces, and the second physical channel group includes K1 electrical interfaces and K2 optical interfaces. Here, H is the (smallest) common multiple of H1, H2, and K is the (smallest) common multiple of K1, K2.

Specifically, in this embodiment of the present application, multiplexing the data distributed to the first virtual channel group and the data distributed to the second virtual channel group to at most H interfaces of the first physical channel group and at most K interfaces of the second physical channel group, respectively, may include the following steps:

c1, multiplexing the data distributed to the first virtual channel group and the data distributed to the second virtual channel group to H1 electrical interfaces of the first physical channel group and K1 electrical interfaces of the second physical channel group respectively, wherein M is an integral multiple of H1, and N is an integral multiple of K1;

and C2, respectively multiplexing and mapping and modulating all data multiplexed on H1 electrical interfaces and all data multiplexed on K1 electrical interfaces, and then sending the data to H2 optical interfaces and K2 optical interfaces, wherein M is an integral multiple of H2, and N is an integral multiple of K2.

The data code block and the FEC check code block are first multiplexed onto the electrical interface of the first physical channel group and the electrical interface of the second physical channel group in step C1, and then all the data on the electrical interface of the first physical channel group are multiplexed and mapped and modulated in step C2, and then sent to the optical interface of the first physical channel group, and all the data on the electrical interface of the second physical channel group are multiplexed and mapped and modulated, and then sent to the optical interface of the second physical channel group. Specifically, in step C2, the electrical-to-optical conversion may be implemented by an optical module connected between the electrical interface and the optical interface, and the process of the electrical-to-optical conversion is not described herein again.

It should be noted that, in the embodiment of the present application, the first virtual channel group and the second virtual channel group described in step 202 both refer to a plurality of virtual channels divided into two different groups, and only the nomenclature adopted for distinguishing the first virtual channel group and the second virtual channel group is to divide the plurality of virtual channels into the different groups respectively, where "first" and "second" do not have any relation in time sequence or logic, and only the explanation here is made, and the distinction between the first physical channel group and the second physical channel group is also applicable to the explanation here regarding "first" and "second". In the embodiment of the application, the interfaces of the physical channel groups used by the data code block and the FEC check code block respectively are divided into two interface subgroups, so that when the sending end device transmits the data code block and the FEC check code block, the first physical channel group is used for transmitting the data code block, and the second physical channel group is used for transmitting the FEC check code block. That is, all data multiplexed onto at most H interfaces and all data multiplexed onto at most K interfaces are transmitted to a receiving end through a physical transmission medium. In the embodiment described herein, space division and shunting are performed on the FEC check code block and the data code block, the data code block and the FEC check code block are multiplexed onto interfaces of different physical channel groups, and then the data code block and the FEC check code block are simultaneously transmitted in a target distance through a physical transmission medium.

In addition to generating FEC check code blocks, the method may further include generating i idle code blocks, where the idle code blocks include certain idle information bit patterns known by both the transmitting end and the receiving end, N × t 1N _ max, N _ max ≧ N × t2, t1, t2 are positive integers and are determined by M, H, i equals N _ max minus N × t2, the idle code blocks and the FEC check code blocks are distributed to N virtual channels of a second virtual channel group, then the data bit streams distributed to the second virtual channel group and corresponding to N virtual channels described in step 103 include N idle data bit streams and N idle data bit streams, and the data bit streams are multiplexed to a second physical channel group, N — N ×.

It should be noted that the FEC check code blocks and the idle code blocks may be indicated by using different sync headers, for example, a sync header "0 b 01" used for the FEC check code blocks, a sync header "0 b 10" used for the idle code blocks, a sync header "0 b 01" for the FEC check code blocks, FEC check overhead data in the blocks, a sync header "0 b 10" for the idle code blocks, and idle information bits in the blocks.

When the data distributed to the second virtual channel group includes the FEC check code block and the idle code block, the data distributed to the second virtual channel group is multiplexed onto the interface of the second physical channel, which may specifically include the following steps:

for example, a first virtual channel group has M-80 virtual channels, a first physical channel group has 16 physical interfaces, a second virtual channel group has 10 virtual channels, and a second physical channel group has 2 physical interfaces, which means that, within one FEC frame period, 160 data code blocks need to be distributed to M-80 virtual channels, 10 data code blocks need to be distributed to N-10 virtual channels, 10 idle code blocks need to be inserted according to the equal rate of the physical channels, M _ max-M × t1, t 1-2, N _ 10 × t 1-20, i-N-M-10-max-M-10 t1, t 1-2, N-max-10 t 1-20, and the idle code blocks are inserted into the second physical channel group, wherein, the idle code blocks are inserted into the second physical channel group, and the idle code blocks are used for transmission of the FEC frame 1.

In the embodiment of the application, FEC encoding is performed on m data code blocks on an FEC encoding processing sublayer to generate n FEC check code blocks, then the data code blocks and the FEC check code blocks are respectively distributed to a first virtual channel group and a second virtual channel group, next, data distributed to the first virtual channel group and data distributed to the second virtual channel group are respectively multiplexed on an interface of the first physical channel group and an interface of the second physical channel group, the first physical channel group is used for transmitting the data code blocks, the second physical channel group is used for transmitting the FEC check code blocks, an additional transmission channel separated from space is used, and isolation and independent transmission are achieved with the data.

In this embodiment of the present application, FEC encoding is performed on a data code block on an FEC encoding processing sublayer to generate an FEC check code block, then the data code block and the FEC check code block are respectively distributed to a first virtual channel group and a second virtual channel group, and then data distributed to the first virtual channel group and data distributed to the second virtual channel group are respectively multiplexed on an interface of a first physical channel group and an interface of a second physical channel group. The FEC check code blocks are distributed to the N virtual channels of the second virtual channel group firstly and then are output to the K interfaces of the additional second physical channel group different from the data transmission channel through the N virtual channels through bit variable speed multiplexing, so that the FEC check code blocks do not occupy the transmission bandwidth of original data, and the method can be suitable for occasions with low delay requirements. Since the data code block and the FEC check code block are separately transmitted to the first physical channel group and the second physical channel group, the FEC check code block uses additional spatially separated transmission channels, enabling isolated and independent transmission from the data. The FEC check code block does not occupy the bandwidth of a data code block forwarding link, the FEC coding density is determined according to a network link, packet loss recovery is guaranteed to be completed at one time to the maximum extent, and air interface waste and time delay caused by retransmission of the data forwarding link are reduced.

The above embodiments describe a method for transmitting data on a transmitting end, and next describe a method for receiving data on a receiving end, please refer to fig. 4, which may specifically include the following steps:

301. first data is received from a first physical channel group, and m data code blocks are separated from the first data, wherein m is a positive integer.

In one embodiment, the M data bit streams distributed to the first physical channel group are multiplexed onto at most H interfaces of the first physical channel group, and the N data bit streams distributed to the second virtual channel group are multiplexed onto at most K interfaces of the second physical channel group, respectively.

The multiplexing of the M data bit streams may be simultaneously multiplexing to at most H interfaces, where M is an integer multiple of H, and the M data bit streams may be multiplexed to H interfaces of the first physical channel group, or may be multiplexed to H1 and H2 specific interfaces of the first physical channel group that are less than H. For the case of less than H, specific H1 electrical interfaces and H2 optical interface are taken as an example for explanation. In the embodiment of the present application, multiplexing may be bit-rate-variable multiplexing, where bit-rate-variable multiplexing refers to a multiplexing method of multiplexing input data bit streams and then outputting the multiplexed data bit streams, for example, 4 input data bit streams may be input, and if the rate-variable ratio is 4:3, 3 data bit streams may be output.

302. And receiving second data from a second physical channel group, and separating n FEC check code blocks from the second data stream, wherein n is a positive integer.

In this embodiment, the sending end and the receiving end divide the physical channels into two groups, namely a first physical channel group and a second physical channel group, and the receiving end can receive data from the first physical channel group and the second physical channel group respectively through different divisions of the physical channels. The first physical channel group and the second physical channel group can be a combination of 5G and 2.4G, and can also be a double 5G combination.

303. And correcting the error codes in the m data code blocks by using the n FEC check code blocks on the FEC coding processing sublayer, and inputting the m data code blocks after error code correction into the physical coding sublayer.

For the receiving end, the data sent through the H interfaces of the first physical channel group and the data sent through the K interfaces of the second physical channel group are received, the embodiment of the present application may further include the following steps:

d1, separating M data code block streams from data sent by at most H interfaces, and separating N FEC check code block streams from data sent by at most K interfaces, where M is an integer multiple of H, M data code block streams correspond to M virtual channels of a first virtual channel group, N is an integer multiple of K, and N data code block streams correspond to N virtual channels of a second virtual channel group.

D2, searching for the alignment mark code block inserted in the (M + N) code block streams composed of the data code block stream on the M virtual channels and the FEC check code block on the N virtual channels.

D3, code block sequences for code block distribution on (M + N) virtual channels are aligned and recombined according to the alignment mark code blocks to obtain M × t2 data code blocks and N × t2 FEC check code blocks, wherein M × t2 is less than or equal to M _ max, M _ max is t1 times of M, N × t2 is less than or equal to N _ max — N × t1, N _ max is t1 times of N, and t1 and t2 are positive integers;

d4, discarding the alignment mark code block after completing the alignment reorganization by using the alignment mark code block.

If step 203 is executed in the embodiment of the present application, for the receiving end, the data sent through the H interfaces of the first physical channel group and the data sent through the K interfaces of the second physical channel group are received, and the embodiment of the present application may further include the following steps:

D1～D2；

d5, rearranging the code block streams on the (M + N) virtual channels according to the alignment mark code block alignment, obtaining M × t2 data code blocks, N × t2 FEC check code blocks, and i idle code blocks, where M × t2 is less than or equal to M _ max ═ M × t1, M _ max is t1 times of M, N23 t2 is less than N _ max ═ N × t1, N _ max is t times of N, t1, t2 are positive integers, and the inserted idle code block i is equal to N _ max minus N × t 2.

D6, discarding the alignment mark code block and the i idle code blocks after completing the alignment reorganization by using the alignment mark code block.

The difference between the steps D5 to D6 and the aforementioned steps D3 to D4 lies in whether the data sent by the sender via the at most K interfaces of the second physical channel group includes idle code blocks, and if the data includes idle code blocks, the idle code blocks need to be found and then discarded.

It should be noted that, in the embodiment of the present application, after the step D4 and the step D6 are completed, the embodiment of the present application may further include the following steps:

and E1, correcting errors in the m × t2 data code blocks by using n × t2 FEC check code blocks on the FEC encoding processing sublayer.

E2, after finishing correcting the error code, discarding n × t2 FEC check code blocks, and inputting m × t2 data code blocks after correcting the error code into the physical coding sublayer.

Aiming at the situation that the alignment mark code blocks are periodically inserted into the code block stream composed of the FEC check code block and the data code block by the sending end in the embodiment, the alignment mark code blocks which can be periodically identified need to be searched, the data code block and the FEC check code block are aligned according to the mark code blocks, then the alignment mark code blocks are deleted to combine a complete code block stream, the code block stream is sent into an FEC encoding processing sublayer to be decoded, the error codes caused after the correctable data code block is transmitted are corrected, and after the error codes are corrected, the FEC check code block is deleted, and the recovered data code block is obtained.

In the embodiment of the application, for a data sending method on one side of a sending end, a receiving end side performs a receiving processing process corresponding to the sending method, receives data sent by at most H interfaces of a first physical channel group and data sent to the receiving end by at most K interfaces of a second physical channel group, and an FEC check code block uses an extra transmission channel separated from space and realizes isolation and independent transmission with the data.

In the above embodiment, the method for transmitting data provided in the present application is described, and then an apparatus for transmitting data corresponding to the method is described, please refer to fig. 5, in which an apparatus 400 for transmitting data includes:

an FEC encoding unit 401, configured to perform FEC encoding on the data code block sequence output by the physical coding sublayer by using m data code blocks as a group on the forward error correction FEC encoding processing sublayer, and generate n FEC check code blocks, where m and n are both positive integers.

A distributing unit 402, configured to distribute the M data code blocks to M virtual lanes of a first virtual lane group, and distribute the N FEC check code blocks to N virtual lanes of a second virtual lane group, where M and N are positive integers.

A multiplexing unit 403, configured to multiplex the data distributed to the first virtual channel group and the data distributed to the second virtual channel group to a first physical channel group and a second physical channel group, respectively.

It should be noted that, for the FEC encoded data processing apparatus 400 provided in the embodiment of the present application, as one of realizable manners, the following unit modules (not shown in fig. 4) may also be included:

an alignment unit, configured to insert alignment marker code blocks periodically into code block streams carried on (M + N) virtual channels of the first virtual channel group and the second virtual channel group, where each alignment marker code block also marks a serial number of a virtual channel where the alignment marker code block is located, and the alignment marker code block is used by a receiving end to perform alignment recombination recovery after the code block streams are obtained.

It should be noted that, at most H interfaces of the first physical channel group are specifically H1 electrical interfaces and H2 optical interfaces, and at most K interfaces of the second physical channel group are specifically K1 electrical interfaces and K2 optical interfaces, where H is the least common multiple of H1 and H2, and K is the least common multiple of K1 and K2, in this case, the multiplexing unit 403 provided in this embodiment of the present application may further include the following unit modules (not shown in fig. 4), as one of the realizable manners:

a multiplexing subunit, configured to multiplex the data distributed to the first virtual channel group and the data distributed to the second virtual channel group onto H1 electrical interfaces of the first physical channel group and K1 electrical interfaces of the second physical channel group, respectively, wherein the H1 is an integer multiple of the M, and the K1 is an integer multiple of the N;

and the mapping subunit is configured to multiplex and map-modulate all data multiplexed onto the H1 electrical interfaces and all data multiplexed onto the K1 electrical interfaces respectively and send the data to the H2 optical interfaces and the K2 optical interfaces, where M is an integer multiple of H2, and N is an integer multiple of K2.

It should be noted that, for the FEC encoded data processing apparatus 300 provided in the embodiment of the present application, as another implementation manner, the following unit modules (not shown in fig. 3) may also be included:

a generating unit configured to generate i idle code blocks, the idle code blocks including idle information bits, wherein i is equal to n _ max minus n;

the distributing unit 403 is further configured to distribute the i idle code blocks to N virtual lanes of the first virtual lane group, where the data distributed to the first virtual lane group includes the N FEC check code blocks and the i idle code blocks.

It should be noted that, because the contents of information interaction, execution process, and the like between the modules/units of the apparatus are based on the same concept as the method embodiment of the present invention, the technical effect brought by the contents is the same as the method embodiment of the present invention, and specific contents may refer to the description in the method embodiment of the present invention shown in fig. 2 or fig. 3, and are not described herein again.

In this embodiment of the application, the FEC encoding unit performs FEC encoding on the data code block sequence on the FEC encoding processing sublayer, with every m data code blocks as a group, to generate n FEC check code blocks, then the distribution unit distributes the data code blocks and the FEC check code blocks to the first virtual channel group and the second virtual channel group, and then the multiplexing unit multiplexes the data distributed to the first virtual channel group and the data distributed to the second virtual channel group onto the interface of the first physical channel group and the interface of the second physical channel group, respectively. Since the FEC check code block is distributed to the N virtual lanes of the second virtual lane group first and then output to the additional second physical lane group through the N virtual lanes, the data transmission bandwidth of the system is not reduced. Since the data code block and the FEC check code block are separately transmitted to the first physical channel group and the second physical channel group, the FEC check code block uses additional spatially separated transmission channels, enabling isolated and independent transmission from the data. The FEC check code block does not occupy the bandwidth of a data code block forwarding link, the FEC coding density is determined according to a network link, packet loss recovery is guaranteed to be completed at one time to the maximum extent, and air interface waste and time delay caused by retransmission of the data forwarding link are reduced.

Referring to fig. 6, another data processing apparatus 500 for FEC decoding according to an embodiment of the present application is described below, including: a first receiving unit 501, a second receiving unit 502, and one of an FEC decoding unit 503 and a transmitting unit 504, wherein,

the first receiving unit 501 receives data from a first physical channel group, and separates m data code blocks from the data, where m is a positive integer.

The second receiving unit 502 receives data from the second physical channel group, and separates n FEC check code blocks from the data stream, where n is a positive integer.

An FEC decoding unit 503, configured to correct the errors in the m data code blocks using the n FEC check code blocks at the FEC coding processing sublayer.

A sending unit 504, configured to input the m data code blocks with corrected bit errors into the physical coding sublayer.

In one design, the apparatus further comprises: a first search indexing unit 505 is configured to search for an alignment mark code block inserted in M + N code block streams composed of data code block streams on M virtual channels and FEC check code blocks on N virtual channels.

A restructuring unit 506, configured to restructure, according to the alignment mark code block, the code block sequence for code block distribution on the M + N virtual channels in an aligned manner, to obtain M data code blocks and N FEC check code blocks.

In one possible implementation, the apparatus 500 further includes:

a second searching unit 507, configured to search for an alignment mark code block inserted in a code block stream composed of the data code block streams on the M virtual channels and the FEC check code blocks on the N virtual channels.

The reassembly unit 506 is further configured to perform alignment reassembly on the code block streams on the M + N virtual channels according to the alignment mark code block to obtain M data code blocks, N FEC check code blocks, and i idle code blocks.

Referring to fig. 7, another data processing apparatus according to an embodiment of the present application will be described, where an FEC encoded data processing apparatus 600 includes:

an input device 601, an output device 602, a processor 603 and a memory 604 (wherein the number of processors 603 in the FEC encoded data processing device 600 may be one or more, one processor is taken as an example in fig. 6). In some embodiments of the present invention, the input device 601, the output device 602, the processor 603 and the memory 604 may be connected by a bus or other means, wherein the connection by the bus is exemplified in fig. 6.

The processor 603 is configured to perform the following steps: FEC encoding is carried out on a data code block sequence output by a physical encoding sublayer on a Forward Error Correction (FEC) encoding processing sublayer, wherein m data code blocks are used as a group to generate n FEC check code blocks, and m and n are both positive integers; distributing the M data code blocks to M virtual channels of a first virtual channel group, and distributing the N FEC check code blocks to N virtual channels of a second virtual channel group, wherein M and N are positive integers; multiplexing the data distributed to the first virtual channel group and the data distributed to the second virtual channel group to a first physical channel group and a second physical channel group, respectively.

In some embodiments of the invention, the processor 603 further performs the steps of: and periodically inserting alignment mark code blocks into code block streams borne on the M + N virtual channels of the first virtual channel group and the second virtual channel group, wherein each alignment mark code block also marks the serial number of the virtual channel where the alignment mark code block is located, and the alignment mark code blocks are used for aligning, recombining and restoring the code block streams after a receiving end acquires the code block streams.

In some embodiments of the present invention, the at most H interfaces of the first physical channel group are in the specific form of H1 electrical interfaces and H2 optical interfaces, the at most K interfaces of the second physical channel group are in the specific form of K1 electrical interfaces and K2 optical interfaces, H is the least common multiple of H1, H2, and K is the least common multiple of K1, K2.

The processor 603 specifically executes the following steps: multiplexing data distributed onto the first virtual channel group and data distributed onto the second virtual channel group onto H1 electrical interfaces of the first physical channel group and K1 electrical interfaces of the second physical channel group, respectively, wherein the H1 is an integer multiple of the M and the K1 is an integer multiple of the N; and respectively multiplexing and mapping and modulating all data multiplexed onto the H1 electrical interfaces and all data multiplexed onto the K1 electrical interfaces, and then sending the data to the H2 optical interfaces and the K2 optical interfaces, wherein M is an integral multiple of H2, and N is an integral multiple of K2.

In some embodiments of the invention, the processor 603 further performs the steps of: generating i idle code blocks, the idle code blocks including idle information bits; distributing the i idle code blocks over N virtual lanes of the first virtual lane group, the data distributed over the first virtual lane group including the N FEC check code blocks and the i idle code blocks.

In some embodiments of the invention, the processor 603 further performs the steps of: and transmitting all the data multiplexed on the first physical channel group and all the data multiplexed on the second physical channel group to a receiving end through a physical transmission medium.

In some embodiments of the invention, the processor 603 further performs the steps of: and discarding i idle code blocks in all data multiplexed on the second physical channel group, and transmitting all data multiplexed on the first physical channel group and n FEC check code blocks in all data multiplexed on the second physical channel group to a receiving end through a physical transmission medium.

In this embodiment of the present application, FEC encoding is performed on m data code blocks on an FEC encoding processing sublayer to generate n FEC check code blocks, then the data code blocks and the FEC check code blocks are respectively distributed to a first virtual channel group and a second virtual channel group, and then data distributed to the first virtual channel group and data distributed to the second virtual channel group are respectively multiplexed on an interface of a first physical channel group and an interface of the second virtual channel group according to bit rate change multiplexing. Since the data code block and the FEC check code block are separately transmitted to the first physical channel group and the second physical channel group, the FEC check code block uses additional spatially separated transmission channels, enabling isolated and independent transmission from the data. The FEC check code block does not occupy the bandwidth of a data code block forwarding link, the FEC coding density is determined according to a network link, packet loss recovery is guaranteed to be completed at one time to the maximum extent, and air interface waste and time delay caused by retransmission of the data forwarding link are reduced.

Referring to fig. 8, a data processing apparatus 700 for FEC decoding includes:

an input device 701, an output device 702, a processor 703 and a memory 704 (wherein the number of processors 703 in the FEC-decoded data processing device 700 may be one or more, and one processor is taken as an example in fig. 7). In some embodiments of the present invention, the input device 701, the output device 702, the processor 703 and the memory 704 may be connected by a bus or other means, wherein the connection by the bus is exemplified in fig. 7.

The processor 703 is configured to execute the following steps:

receiving first data from a first physical channel group, and separating m data code blocks from the first data, wherein m is a positive integer; receiving second data from a second physical channel group, and separating n FEC check code blocks from the second data stream, wherein n is a positive integer; and correcting the error codes in the m data code blocks by using the n FEC check code blocks on the FEC coding processing sublayer, and inputting the m data code blocks after error code correction into the physical coding sublayer.

In some embodiments of the present invention, the processor 703 further performs the following steps:

searching for alignment mark code blocks inserted in M + N code block streams consisting of data code block streams on M virtual channels and FEC check code blocks on N virtual channels; and code block sequences for code block distribution on the M + N virtual channels are aligned and recombined according to the alignment mark code blocks to obtain M data code blocks and N FEC check code blocks.

In some embodiments of the present invention, the processor 703 further performs the following steps: searching for an alignment mark code block inserted in a code block stream consisting of the data code block stream on the M virtual channels and the FEC check code blocks on the N virtual channels; and aligning and recombining the code block streams on the M + N virtual channels according to the alignment mark code blocks to obtain M data code blocks, N FEC check code blocks and i idle code blocks.

It will be understood by those skilled in the art that all or part of the steps in the method for implementing the above embodiments may be implemented by hardware that is related to instructions of a program, and the program may be stored in a computer-readable storage medium, where the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

One or more of the above modules or units may be implemented in software, hardware or a combination of both. When any of the above modules or units are implemented in software, which is present as computer program instructions and stored in a memory, a processor may be used to execute the program instructions and implement the above method flows. The processor may include, but is not limited to, at least one of: various computing devices that run software, such as a Central Processing Unit (CPU), a microprocessor, a Digital Signal Processor (DSP), a Microcontroller (MCU), or an artificial intelligence processor, may each include one or more cores for executing software instructions to perform operations or processing. The processor may be built in a system on chip (SoC) or an Application Specific Integrated Circuit (ASIC), or may be a separate semiconductor chip. The processor may further include a necessary hardware accelerator such as a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), or a logic circuit for implementing a dedicated logic operation, in addition to a core for executing software instructions to perform operations or processing. When the above modules or units are implemented in hardware, the hardware may be any one or any combination of a CPU, a microprocessor, a DSP, an MCU, an artificial intelligence processor, an ASIC, an SoC, an FPGA, a PLD, a dedicated digital circuit, a hardware accelerator, or a discrete device that is not integrated, which may run necessary software or is independent of software to perform the above method flows.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the present application has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. Accordingly, the specification and figures are merely exemplary of the present application as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the present application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method for transmitting data, used in a first device, wherein at least a first physical channel group and a second physical channel group are established between the first device and a second device, the method comprising:

FEC encoding is carried out on a data code block sequence output by a physical encoding sublayer on a Forward Error Correction (FEC) encoding processing sublayer, wherein m data code blocks are used as a group to generate n FEC check code blocks, and m and n are both positive integers;

distributing the m data code blocks to a first physical channel group;

distributing the n FEC check-code blocks to a second physical channel group.

2. The method of claim 1, further comprising:

distributing the M data code blocks to M virtual channels of a first virtual channel group, and distributing the N FEC check code blocks to N virtual channels of a second virtual channel group, wherein M and N are positive integers;

multiplexing the data distributed onto the first virtual channel group and the data distributed onto the second virtual channel group to the first physical channel group and the second physical channel group, respectively.

3. The method of claim 2, wherein distributing the M blocks of data codes over M virtual lanes of a first group of virtual lanes and distributing the N blocks of FEC check codes over N virtual lanes of a second group of virtual lanes, further comprises:

and periodically inserting alignment mark code blocks into code block streams borne on the M + N virtual channels of the first virtual channel group and the second virtual channel group, wherein each alignment mark code block also marks the serial number of the virtual channel where the alignment mark code block is located, and the alignment mark code blocks are used for aligning, recombining and restoring the code block streams after a receiving end acquires the code block streams.

4. The method according to claim 2 or 3, wherein the FEC encoding the data code block sequence output by the physical coding sublayer on the FEC encoding processing sublayer with m data code blocks as a group to generate n FEC check code blocks, and then further comprising:

generating i idle code blocks, the idle code blocks including idle information bits;

distributing the i idle code blocks over N virtual lanes of the first virtual lane group, the data distributed over the first virtual lane group including the N FEC check code blocks and the i idle code blocks.

5. The method according to any one of claims 2 to 4, wherein the multiplexing the data distributed to the first virtual channel group onto a first physical channel group and the multiplexing the data distributed to the second virtual channel group onto a second physical channel group, further comprises:

and transmitting all the data multiplexed on the first physical channel group and all the data multiplexed on the second physical channel group to a receiving end through a physical transmission medium.

6. The method of claim 5, wherein the multiplexing the data distributed to the one virtual channel group onto a first physical channel group and the multiplexing the data distributed to the second virtual channel group onto a second physical channel group further comprises:

and discarding i idle code blocks in all data multiplexed on the second physical channel group, and transmitting all data multiplexed on the first physical channel group and n FEC check code blocks in all data multiplexed on the second physical channel group to a receiving end through a physical transmission medium.

7. The method according to any of claims 1 to 6, wherein the m data code blocks and the n FEC check code blocks are distinguished by different synchronization headers, respectively.

8. A method for receiving data, wherein at least a first physical channel group and a second physical channel group are established between a second device and a first device, the method comprising:

receiving first data from a first physical channel group, and separating m data code blocks from the first data, wherein m is a positive integer;

receiving second data from a second physical channel group, and separating n FEC check code blocks from the second data stream, wherein n is a positive integer;

and correcting the error codes in the m data code blocks by using the n FEC check code blocks on the FEC coding processing sublayer, and inputting the m data code blocks after error code correction into the physical coding sublayer.

9. The method of claim 8, comprising:

searching for alignment mark code blocks inserted in M + N code block streams consisting of data code block streams on M virtual channels and FEC check code blocks on N virtual channels;

and code block sequences for code block distribution on the M + N virtual channels are aligned and recombined according to the alignment mark code blocks to obtain M data code blocks and N FEC check code blocks.

10. The method of claim 9, comprising:

searching for an alignment mark code block inserted in a code block stream consisting of the data code block stream on the M virtual channels and the FEC check code blocks on the N virtual channels;

and aligning and recombining the code block streams on the M + N virtual channels according to the alignment mark code blocks to obtain M data code blocks, N FEC check code blocks and i idle code blocks.

11. A first device, comprising:

an FEC encoding unit, configured to perform FEC encoding on a data code block sequence output by a physical coding sublayer on a forward error correction FEC encoding processing sublayer, with m data code blocks as a group, and generate n FEC check code blocks, where m and n are positive integers;

a distribution unit configured to distribute the m data code blocks to a first physical channel group; distributing the n FEC check-code blocks to a second physical channel group.

12. The first device of claim 11, wherein the distribution unit is further configured to:

the device further comprises:

a multiplexing unit, configured to multiplex the data distributed to the first virtual channel group and the data distributed to the second virtual channel group to the first physical channel group and the second physical channel group, respectively.

13. The first device of claim 12, wherein the apparatus further comprises:

and the alignment unit is used for periodically inserting alignment mark code blocks into code block streams borne on the M + N virtual channels of the first virtual channel group and the second virtual channel group, wherein each alignment mark code block also marks the serial number of the virtual channel where the alignment mark code block is located, and the alignment mark code blocks are used for alignment recombination recovery after a receiving end acquires the code block streams.

14. The first apparatus of claim 12 or 13, wherein the means further comprises:

a generating unit configured to generate i idle code blocks, where the idle code blocks include idle information bits;

the distribution unit is further configured to distribute the i idle code blocks to N virtual lanes of the first virtual lane group, where the data distributed to the first virtual lane group includes the N FEC check code blocks and the i idle code blocks.

15. A second apparatus, comprising:

a first receiving unit, configured to receive data from a first physical channel group, and separate m data code blocks from the data, where m is a positive integer;

a second receiving unit, configured to receive data from a second physical channel group, and separate n FEC check code blocks from the data stream, where n is a positive integer;

an FEC decoding unit, configured to correct, at an FEC encoding processing sublayer, errors in the m data code blocks using the n FEC check code blocks;

and the sending unit is used for inputting the m data code blocks with corrected bit errors into the physical coding sublayer.

16. The second device of claim 15, further comprising:

a first search searching unit, configured to search for an alignment marker code block inserted in M + N code block streams composed of data code block streams on M virtual channels and FEC check code blocks on N virtual channels, where data on the first virtual channel group and data distributed to the second virtual channel group are multiplexed to the first physical channel group and the second physical channel group, respectively;

and the recombination unit is used for carrying out alignment recombination on code block sequences for code block distribution on the M + N virtual channels according to the alignment mark code blocks to obtain M data code blocks and N FEC check code blocks.

17. The second device of claim 16, further comprising:

a second searching unit, configured to search for an alignment mark code block inserted in a code block stream composed of the data code block streams on the M virtual channels and the FEC check code blocks on the N virtual channels;

and the recombination unit is used for aligning and recombining the code block streams on the M + N virtual channels according to the alignment mark code blocks to obtain M data code blocks, N FEC check code blocks and i idle code blocks.

18. A first device, comprising: an input device, an output device, a memory, and a processor;

wherein the processor performs the method of any one of claims 1-7.

19. A second apparatus, comprising: an input device, an output device, a memory, and a processor;

wherein the processor performs the method of any one of claims 8-10.

20. A computer-readable storage medium comprising instructions that, when executed on a device, cause the device to perform the method of any one of claims 1-7 or 8-10.

21. A computer program product comprising instructions which, when run on an apparatus, cause the apparatus to perform the method of any one of claims 1-7 or 8-10.