WO2024001230A1

WO2024001230A1 - Bearing method, communication equipment and storage medium

Info

Publication number: WO2024001230A1
Application number: PCT/CN2023/077540
Authority: WO
Inventors: 刘峰; 杨剑
Original assignee: 中兴通讯股份有限公司
Priority date: 2022-06-28
Filing date: 2023-02-22
Publication date: 2024-01-04
Also published as: CN117354873A

Abstract

The present application provides a bearing method, a communication device, and a storage medium. The method comprises: encoding a customer service to form a service code block stream; processing the service code block stream to obtain a target service code block; and mapping the target service code block to a sub-slot in a basic unit for bearing, the basic unit being a set of a plurality of code blocks having a fixed structure, and the sub-slot being a bearing space for a fixed-length bit.

Description

Bearing method, communication equipment and storage medium

Technical field

This application relates to the field of communication technology. For example, it relates to a bearing method, communication device and storage medium.

Background technique

Flexible Ethernet FlexE technology can meet the carrying requirements of voice service characteristics and message service characteristics at the same time, becoming the future development direction of communication networks.

FlexE technology can support customer service transmission at the 5th Generation Mobile Communication Technology (5G) rate. However, for customer services at rates lower than 5G, it cannot carry out the transmission efficiently.

Contents of the invention

This application provides a carrying method, communication equipment and storage medium.

The embodiment of this application provides a bearing method, including:

Encode the customer service to form a service code block stream; process the service code block stream to obtain the target service code block; map the target service code block to the sub-slot in the basic unit for carrying, and the basic unit It is a set of multiple code blocks with a fixed structure, and the sub-slot is a fixed-length bit carrying space.

An embodiment of the present application also provides a communication device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the above-mentioned carrying method is implemented.

Embodiments of the present application also provide a storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the above-mentioned carrying method is implemented.

Description of drawings

Figure 1 is a schematic diagram of the working principle of the FlexE protocol;

Figure 2 is a schematic diagram of the location of the overhead block in the FlexE protocol time slot;

Figure 3 is a schematic flowchart of a carrying method provided by an embodiment;

Figure 4 is a schematic structural diagram of a 66-bit service code block provided by an embodiment;

Figure 5 is another structural schematic diagram of a 66-bit code block provided by an embodiment;

Figure 6 is a schematic diagram of the synchronization header bit compression process of a 66-bit code block provided by an embodiment;

Figure 7a is a first schematic diagram of the transcoding process of service code blocks provided by an embodiment;

Figure 7b is a second schematic diagram of the transcoding process of service code blocks provided by an embodiment;

Figure 7c is a third schematic diagram of the transcoding process of service code blocks provided by an embodiment;

Figure 7d is a fourth schematic diagram of the transcoding process of service code blocks provided by an embodiment;

Figure 8 is a schematic diagram of the process of carrying customer services by a basic unit according to an embodiment;

Figure 9 is a schematic diagram of a basic unit carrying a FlexE time slot according to an embodiment;

Figure 10 is a schematic structural diagram of a code block in a basic unit provided by an embodiment;

Figure 11 is a schematic diagram of the location of the overhead part in the basic unit provided by an embodiment;

Figure 12 is a schematic diagram of dividing sub-time slots in a basic unit according to an embodiment;

Figure 13 is a schematic structural diagram of a basic unit provided by an embodiment;

Figure 14 is another structural schematic diagram of a basic unit provided by an embodiment;

Figure 15 is a schematic structural diagram of a multiframe composed of multiple basic units provided by an embodiment;

Figure 16a is a first schematic diagram of the separation process of the synchronization header part and the data byte part in the target service code block provided by an embodiment;

Figure 16b is a second schematic diagram of the separation process of the synchronization header part and the data byte part in the target service code block provided by an embodiment;

Figure 16c is a third schematic diagram of the separation process of the synchronization header part and the data byte part in the target service code block provided by an embodiment;

Figure 17 is a schematic diagram of the arrangement and position of time slots when synchronization header bits are carried intensively according to an embodiment;

Figure 18 is a schematic diagram of another time slot arrangement position when synchronization header bits are carried intensively according to an embodiment;

Figure 19 is a schematic diagram of the process of centralized carrying of synchronization header bits provided by an embodiment;

Figure 20 is a schematic diagram of a process in which synchronization header bits are divided into multiple synchronization header groups and carried according to an embodiment;

Figure 21 is a first structural schematic diagram of a basic unit including check bits provided by an embodiment;

Figure 22 is a second structural schematic diagram of a basic unit including check bits provided by an embodiment;

Figure 23 is a schematic structural diagram of a carrying device according to an embodiment;

FIG. 24 is a schematic diagram of the hardware structure of a terminal device according to an embodiment.

Detailed ways

The embodiments of the present application will be described below in conjunction with the accompanying drawings.

The operations illustrated in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowchart diagrams, in some cases, the operations shown or described may be performed in a different order than herein.

Communication network is an information highway. In the past, communication content was mainly voice services. Communication networks using Synchronous Digital Hierarchy (SDH) and Optical Transport Network (OTN) technologies can well meet the delivery of voice services. . With the development of communication technology and the reduction of tariffs, communication information networks mainly carry message services with an Ethernet structure, and communication network technology has also been converted to Ethernet technology. After the FlexE technology standard was released, FlexE technology quickly became commercially available and became the development direction of future communication networks because FlexE technology meets the carrying requirements of both voice service features and message service features. FlexE technology divides 20 time slots into the 100G bit/s physical interface, which is equivalent to 20 sub-physical pipes. Different time slots are isolated from each other to meet the voice service characteristics. At the same time, each sub-time slot adopts message service characteristics. Therefore, FlexE technology meets the characteristics of voice services and message services at the same time, enabling voice services and message services to be independently carried on one network.

Figure 1 is a schematic diagram of the working principle of the FlexE protocol. The FlexE protocol combines multiple Ethernet interfaces with a transmission rate of 100G bit/s to form a large-rate transmission channel. As shown in Figure 1, four Ethernet interfaces with a transmission rate of 100G bit/s are combined through the FlexE protocol. Together, they form a 400G transmission channel, which is equivalent to the transmission rate of a 400G optical module. It solves the transmission needs of 400G services without increasing costs. It not only meets the transmission needs of 400G services, but also solves the problem of business problems. Issues of economic value delivered. The physical layer defined by the FlexE protocol is 100G, and 20 time slots are defined on the 100G physical layer. The corresponding bandwidth of each time slot is 5G bit/s. The FlexE protocol is under 64/66-bit information block encoding. Before sending the 66-bit information block, the FlexE protocol sorts and plans the 66-bit information block at the FlexE protocol layer. A 66-bit information block may include a 66-bit long data block and a 66-bit long overhead block. Figure 2 is a schematic diagram of the location of the overhead block in the FlexE protocol time slot. As shown in Figure 2, for 100G customer services, every 20 66-bit information blocks are divided into a group. There are a total of 20 information blocks in each group, representing 20 times. Slots, each time slot can transmit customer services at 5G speed, and customer services can choose one time slot or multiple time slots to bear and send. The time slot rate provided by FlexE technology is 5G bit/s, which supports customer service bearing at twice the speed of 5G. However, it cannot provide good bearer delivery for customer services with a transmission rate lower than 5G bit/s.

Based on the FlexE protocol, this application proposes a high-quality, high-efficiency, and high-reliability carrying method for low-rate, small-granule customer services. Figure 3 is a schematic flowchart of a bearer method provided by an embodiment. As shown in Figure 3, the method may include S110, S120 and S130.

In S110, the customer service is encoded to form a service code block stream.

In this embodiment, customer services can be understood as low-rate small-grain customer services with transmission rates less than 5G bit/s, that is, various customer services with transmission rates less than 5G bit/s, such as customers with transmission rates of 1G, 100M, and 10M. business.

In this embodiment, encoding the customer service can be 64/66 encoding, which can be understood as adding 2 bits to the 64-bit customer service data and extending it into a 66-bit service code block. The added 2 bits can be used as a synchronization header. bits that precede the 64-bit code block before expansion. The added 2-bit code block can be used to characterize the type of service code block. The added two bit values can be "01" or "10". "01" indicates that the service code block is a data code block, "10" indicates that the service code block is a control code block, and the synchronization header bit is located in the service code block. At the front of the block, the 66-bit service code block is sent out from the physical interface; when receiving, the 66-bit length service code block is identified from the code block received by the physical interface, and the 66-bit length service code block is recovered. The original 64-bit code blocks are extracted and the customer service is reassembled.

Figure 4 is a schematic structural diagram of a 66-bit service code block provided by an embodiment. Figure 4 is an 802.3 protocol 64/66 encoding rule. Each code block consists of 66 bits. The first 2 bits are the synchronization header of the code block. , the synchronization header bit is "01" to represent the data code block, and the following 8 bytes, that is, the 64-bit bit position is the 8-byte data content; the synchronization header bit is "10" to represent the control code block, and the control code block is The first byte content indicates the type of control code block, and the next 7 bytes indicate the content of the control code block. The content of the 7 bytes is determined by the type of control code block. The S code block and T code block in Figure 4 both belong to the control code block. The first byte content in the S code block is 0x78, indicating that the control code block is an S code block; the T code block can be used as the end code block, or Carrying the customer byte content, the customer byte content is located in the last 7 bytes of the code block. There are 8 types of T code blocks in the Ethernet standard: T0, T1, T2, T3, T4, T5, T6, T7. The first byte content of the T0 code block is 0x87. The code block does not carry customer information. T1 The first byte content of the code block is 0x99, carrying 1 byte of customer information. The first byte content of the T2 code block is 0x99, carrying 2 bytes of customer information, and so on. The T7 code block The first byte content is 0xFF, carrying 7 bytes of customer information.

In S120, the service code block stream is processed to obtain a target service code block.

In this embodiment, processing the service code block stream may include: adding, deleting, code block compression, or transcoding code blocks to the service code block stream.

In this embodiment, the processing includes one or more of the following:

Add or delete idle code blocks in the service code blocks included in the service code block stream; add or delete maintenance management information code blocks in the service code blocks included in the service code block stream; modify the service code blocks The service code blocks included in the stream are synchronized header compressed; the service code blocks included in the service code block stream are transcoded.

In one embodiment, according to the time slot rate of the basic unit, an appropriate amount or Delete idle code blocks so that the rate of the service code block stream adapts to the time slot rate of the basic unit.

In this embodiment, by adding or deleting idle code blocks in the 66-bit service code block stream, the rate of the service code block stream can be adjusted.

In this embodiment, according to the time slot rate of the basic unit, an appropriate amount of maintenance management information code blocks are added or deleted in the service code block stream, so that the rate of the target service code block stream adapts to the time slot rate of the basic unit.

In this embodiment, a maintenance management information code block is added to the 66-bit service code block stream. The maintenance management information code block can carry maintenance management information and can implement fault detection. Deleting or adding maintenance management information code blocks can make the rate of the target service code block stream adapt to the time slot rate of the basic unit.

In this embodiment, synchronization header compression is performed on the service code blocks in the service code block stream, and the 66-bit service code block stream is compressed into a 65-bit target service code block.

In this embodiment, in order to improve the carrying efficiency, the 66-bit service code block can be compressed or transcoded, for example, the 66-bit code block is compressed into a 65-bit code block, and the synchronization header bit is compressed from 2 bits to 1 bit. The number of information bits in the code block is saved, thereby saving network bandwidth.

Figure 5 is another structural schematic diagram of a 66-bit code block provided by an embodiment. As shown in Figure 5, the first two bits of the 66-bit code block are synchronization header bits. When the synchronization header bit is normal, there are only two valid values: "10" or "01". The synchronization header value is "10", which means that the code block is a control code block. The content of the first byte in the control code block, that is, the control word content, determines what kind of control code block the control code block belongs to. The control word corresponding to the S code block can The control words corresponding to "0x78", T code blocks and S code blocks can be "0x87", "0x99", "0xAA", "0xFF", etc.; both idle code blocks and S code blocks belong to control code blocks, and the corresponding The control word can be "0x1E"; the control word corresponding to the maintenance management information code block can be "0x4B". When the value of the synchronization header code block is "01", it means that the code block is a data code block, referred to as a D code block.

In this embodiment, since the synchronization header bits include 2 bits, but the synchronization header bits can only represent two different code block types, the synchronization header bits can be compressed from 2 bits to 1 bit. Figure 6 is a schematic diagram of the synchronization header bit compression process of a 66-bit code block provided by an embodiment. As shown in Figure 6, for example, the synchronization header bit is compressed from "10" to "1" and from "01" is "0". In the application, the synchronization header bits can also be compressed from "10" to "0" and from "01" to "1".

In one embodiment, the service code blocks in the service code block stream are transcoded, and the 66-bit service code blocks are transcoded into 257-bit target service code blocks.

In this embodiment, the Institute of Electrical and Electronics Engineers (IEEE) 802.3 transcoding standard can be used to convert four 66-bit code blocks into one 257-bit code block. Figures 7a-7b show transcoding modes in which four different types of 66-bit code blocks are converted into one 257-bit code block. Figure 7a is a first schematic diagram of the transcoding process of service code blocks provided by an embodiment. Figure 7a shows the first type of transcoding mode. Transcoding mode 1 includes transcoding of four 66-bit data code blocks. is a 257-bit code block; Figure 7b is a second schematic diagram of the transcoding process of the service code block provided by an embodiment. Figure 7b shows the second type of transcoding mode. Transcoding mode 2 includes a 66-bit The control code block and three 66-bit data code blocks are transcoded into a 257-bit code block; Figure 7c is a third schematic diagram of the transcoding process of the service code block provided by an embodiment. Figure 7c shows the third Type of transcoding mode, transcoding mode 3 includes three 66-bit data code blocks and one 66-bit control code block transcoded into a 257-bit code block; Figure 7d shows the service code block provided by an embodiment The fourth schematic diagram of the transcoding process, Figure 7d shows the fourth type of transcoding mode. Transcoding mode 4 includes four 66-bit control code blocks transcoded into one 257-bit code block. A 257-bit code block obtained after transcoding in the above four different transcoding modes only has a 1-bit synchronization header. Each time the transcoding occurs, the 8 synchronization header bits in the 4 code blocks are turned into a synchronization header. bits, saving 7 bits of synchronization header, thereby saving bandwidth. Transcoding a 66-bit code block into a 257-bit code block is a standard content of IEEE 802.3 and will not be explained again.

In S130, map the target service code block to be carried on a sub-slot in the basic unit.

In this embodiment, the basic unit may be called a basic unit frame, a basic frame, a cell, a code group, etc. There is no restriction on the format of the basic unit here.

In this embodiment, the format of the basic unit is determined, and sub-slots are divided into the basic unit. All sub-slots can be divided into one basic unit, or multiple basic units can be composed into a multiframe, and all sub-time slots can be divided into multiple basic units in a multiframe.

In this embodiment, the synchronization header bits and the data part in the target service code block can be mapped and carried separately, and the synchronization header bits of multiple target service code blocks are carried together.

In this embodiment, the synchronization header bits of all target service code blocks can be carried together, or all the synchronization header bits can be divided into multiple groups, and the synchronization header bits of each group can be carried together.

In this embodiment, check bits can be set in the basic unit to check and correct the synchronization header bits in the target service code block; part of the overhead bits and part of the synchronization header bits in the target service code block can also be combined Together, part of the overhead bits and part of the synchronization header bits are checked and corrected.

In this embodiment, the basic unit transmits through the time slot bearer of Flexible Ethernet.

The basic unit can be transmitted through the 5G time slot of Flexible Ethernet. For example, the time slot of Flexible Ethernet can be a 66-bit code block.

In this embodiment, for customer services with a rate lower than 5G, high-quality, high-efficiency, and high-reliability transmission can be achieved by mapping the target service code blocks to sub-slots in the basic unit.

FIG. 8 is a schematic diagram of the process of carrying customer services by a basic unit according to an embodiment. As shown in Figure 8, the customer service first performs 64/66 encoding to form a 66-bit code block stream; then the 66-bit code block can be compressed or transcoded, for example, the 66-bit code block is compressed into a 65-bit code block. code block, or transcode four 66-bit code blocks into one 257-bit code block; finally, the code block can be mapped to the basic unit On the sub-slot, the transmission is carried on the flexible Ethernet time slot.

In this embodiment, the basic unit is a set of multiple code blocks with a fixed structure. In one embodiment, the structure of the fixed-structure code block includes a start code block, one or more data code blocks, and an end code block; the start code block is used to indicate the start of the basic unit; the data code block is used to Carrying customer services; the end code block is used to indicate the end of the basic unit.

The basic unit is transmitted through the FlexE 5G time slot. Since the FlexE time slot is a 66-bit code block, the basic unit can also be composed of 66-bit code blocks to be suitable for transmission in the FlexE technology interface.

Figure 9 is a schematic diagram of a basic unit carried through FlexE time slots provided by an embodiment. As shown in Figure 9, the basic unit is composed of multiple code blocks with a length of 66 bits. The composition structure can be: S code blocks + n D code blocks +T code block, n is a natural positive integer, which is a fixed value. The S code block is the start block, indicating the beginning of the basic unit; the D code block is the data block, used to carry customer services; the T code block is the end block, indicating the end of the basic unit. A basic unit is a collection of multiple code blocks with a fixed structure, usually of fixed length.

Figure 10 is a schematic structural diagram of a code block in a basic unit provided by an embodiment. The expanded structure of the basic unit defined by S code blocks + n D code blocks + T code blocks is shown in Figure 10. Each line in the figure represents a code block, and the length of each code block is 66 bits. The first line It is an S code block, the middle is a D code block, and the last is a T code block (T7 type code block). The first byte in the S code block and T code block is the code block control word, which are "0x78" and "0xFF" respectively. In addition to the 8 byte positions in the D code block that can carry customer services, the next few byte positions in the S code block and T code block can also carry customer services.

In one embodiment, the code block of the fixed structure further includes the following parts: an overhead part; a synchronization header part; a synchronization header verification part; the overhead part is located in the middle and front position of the basic unit, and the overhead part indicates Characteristic content of the basic unit.

In this embodiment, each code block includes a synchronization header part, which may be a 2-bit synchronization header. Each code block also includes a synchronization header check part. The synchronization header check part can be k-bit check bits. The synchronization header check part can correct the erroneous information bits sent.

In this embodiment, overhead information, that is, the overhead part, is generally set up in the basic unit. In most cases, the overhead information is at the front of the basic unit, and the customer service is at the back of the basic unit. Overhead information is used to indicate the characteristic content of the basic unit, such as version number, serial number, management channel information value, negotiation information value, check value, etc.

FIG. 11 is a schematic diagram of the location of the overhead part in the basic unit provided by an embodiment. As shown in Figure 11, the overhead byte OH can be located at the back of the S code block, that is, overhead position one, or it can be located at the first D code block, that is, overhead position two, or it can be located at the first T code block. , that is, overhead position three. In Figure 11, the cell overhead part consists of 5 or 7 bytes, and the number of overhead bytes can also be 3, 4, 5, 6, 7.....etc. various lengths. The overhead part may include but is not limited to the following information: multiframe indication information, overhead channel indication information, timeslot increase adjustment notification information, timeslot validation indication, timeslot adjustment request information, timeslot adjustment response information, general delivery channel information, The client number information, sub-slot number information, and check information on the time slot, such as Cyclic Redundancy Check (CRC), are used as check information.

In this embodiment, the corresponding sub-slot is a fixed-length bit bearing space. In one embodiment, the sub-time slot is obtained by dividing the payload area in the data code block of the basic unit. One sub-time slot is located in some bit positions of multiple data code blocks. The sub-time slot The length is a multiple of the preset value.

In this embodiment, sub-slots are divided into sub-slots in the payload area of the basic unit. The sub-slots are fixed-length bit bearing spaces used to carry code block information content of customer services. The size of a sub-slot can be any value among 8, 65, 66, 257, or an integer multiple of these values.

Figure 12 is a schematic diagram of dividing sub-time slots in a basic unit according to an embodiment. As shown in Figure 12, the size of a sub-slot can be 8 bits, 65 bits, 66 bits, 257 bits, etc., or an integer multiple of these length bits. L is used to represent the sub-slot bit length. Only 64 bits (8 bytes) in a D code block can carry customer service information content. When the size of a sub-slot is multiple bits or is not an integer multiple of 64, a sub-slot can be located in multiple D codes. block.

FIG. 13 is a schematic structural diagram of a basic unit provided by an embodiment. As shown in Figure 13, the basic unit consists of S code blocks + several D code blocks + T code blocks. The basic unit includes an overhead area and multiple sub-slots. The overhead area and payload area are located in several D code blocks. When the sub-slot length L in a basic unit is 65 bits and the number of sub-slots m is 480, it is equivalent to L=65 and m=480. Of course, L can also be equal to 8, 65, 66, 257, or multiples of these lengths, such as 2*8, 3*8, 4*8, ....., 2*65, 3*65, 4*65, ....., or 2*66, 3*66, 4*66..., or 2*257, 3*257, 4*257, etc.

In this embodiment, the payload area of the basic unit can be divided into multiple sub-time slots, each sub-time slot can carry one customer service, and the customer service can also be carried on multiple sub-time slots.

In one embodiment, one or more of the following code blocks are inserted between the basic units: at least one idle code block; at least one maintenance information management code block; the maintenance information management code block is used to monitor the service quality of the communication channel. In this case, the communication channel is the channel carrying the basic unit.

In this embodiment, there is no restriction on the way of inserting code blocks between basic units.

In one embodiment, at least one idle code block can be inserted between the basic units; in one embodiment, at least one maintenance information management code block can be inserted between the basic units; in one embodiment, at least one idle code block can be inserted between the basic units. At least one idle code block and at least one maintenance information management code block are inserted between them.

Figure 14 is another structural schematic diagram of a basic unit provided by an embodiment. As shown in Figure 14, in order to monitor the speed and quality of the basic unit, a small amount of maintenance management is sometimes inserted between the basic units when sending the basic unit. The information code block is Operation Administration and Management (Operation Administration and Maintenance (OAM) information code block. The OAM information code block carries maintenance management information and is used to monitor the service quality status of the basic unit pipeline. Due to the clock frequency difference between all devices on the network, the basic unit needs to adjust the rate when transmitting on the network. When the basic unit passes through each device on the network, each device needs to adjust the received basic unit stream to its own station. The sending clock frequency of the device is then sent out according to the sending clock frequency of the device. When the basic unit actually transmits, appropriate idle code blocks, namely IDLE code blocks, referred to as I code blocks, will be inserted between the basic units. The idle code block does not carry any useful information and is inserted when sending and deleted when receiving. It does not affect the normal transmission of the basic unit. By changing the number of idle blocks in the basic unit stream, the actual speed of the basic unit stream can be changed. When the basic unit flow speed is less than the sending speed of the physical port, an appropriate amount of idle blocks will be inserted into the basic unit flow (between the two basic units before and after). After adding idle blocks, the actual speed of the basic unit flow will increase (the basic unit's The number has not changed); when the basic unit flow speed is greater than the sending speed of the physical port, an appropriate amount of idle blocks in the basic unit flow will be deleted. After deleting some of the idle blocks, the actual speed of the basic unit flow can be reduced. Since the addition or deletion operation is only for idle code blocks, it does not change the number of basic units and the overall content of the cell, and the content carried by the basic unit is not affected.

In this embodiment, the division method of the sub-time slots includes one or more of the following: dividing all sub-time slots in a basic unit; dividing all sub-time slots in a multi-frame; wherein the multi-frame is composed of Composed of multiple basic units.

In this embodiment, multiple sub-slots can be divided into one basic unit.

In one embodiment, a multiframe structure composed of multiple basic units may be divided into sub-slots.

In the application, all sub-time slots can be divided into one basic unit, or multiple basic units can be formed into a multiframe structure, and all sub-time slots can be divided into the multi-frame structure, with only some sub-time slots in each basic unit. Figure 15 is a schematic structural diagram of a multiframe composed of multiple basic units provided by an embodiment. As shown in Figure 15, each basic unit can be divided into 30 sub-time slots, and every 16 basic units form a multiframe. There are a total of 480 sub-slots in the frame. Each sub-time slot can carry 4 code blocks. The client code block is compressed and transcoded into a 65-length code block. There are 30 sub-time slots in each basic unit. Each sub-time slot carries 4 client code blocks. In the data part, 30 sub-slots carry a total of 30*4=120 code blocks of data, with a total of 120 bits of synchronization header. Each basic unit can also be divided into 60 sub-time slots, and every 8 basic units form a multiframe. There are a total of 480 sub-time slots in a multiframe. Each sub-slot can carry 2 code blocks. The client code block is compressed and transcoded into a 65-length code block. There are 60 sub-slots in each basic unit, and each sub-slot carries the data part of 2 client code blocks. Each basic unit can also be divided into 120 sub-time slots. Every 4 basic units form a multiframe. There are a total of 480 sub-time slots in a multi-frame. Each sub-time slot can carry 1 or 2 code blocks.

In one embodiment, mapping the target service code block to be carried on a sub-slot in the basic unit includes: mapping the target service code block to be carried on a sub-slot in the basic unit, or mapping the target service code block to be carried on a sub-slot in the basic unit. The service code block is mapped to multiple sub-slots in the basic unit and carried.

In terms of implementation, the basic unit can be divided into many sub-time slots, and customer services can be carried on some of the sub-time slots. Multiple customer services can be carried in one basic unit, or multiple basic units can be grouped together to form a basic unit. In the multiframe structure, each basic unit is divided into some sub-time slots, and all sub-time slots are divided into all basic units in the basic unit group to carry customer services. The customer services are carried on the sub-time slots of multiple basic units. The number of sub-time slots to be carried is selected according to the bandwidth size of the customer service. The bandwidth of the customer service matches the number of sub-time slots to meet the bandwidth requirements of the customer service.

In one embodiment, mapping the target service code block to the sub-slot in the basic unit includes: separating the synchronization header bits and data in the target service code block; mapping the synchronization header bit to the basic unit. The synchronization header position in the unit is carried; the data is mapped to the sub-slot in the basic unit and carried.

The basic unit payload area is mainly located in the D code block. There are 64 bits in each D code block that can be used as the payload area to carry customer services. When the customer code block is carried, that is, the compressed or transcoded customer code block is Code blocks with a length of 65 bits, code blocks with a length of 66 bits, and code blocks with a length of 257 bits. The relationship between the 64-bit length of the payload area in the D code block and the length of the code block being carried is not an integer multiple. In this case, according to the The positions of the sub-slots that carry the length division of the customer code block are not very regular, as shown in the sub-slot division results in Figure 11. In order to facilitate the division of sub-slots, the synchronization header part and the data byte part of the target service code block can be carried separately.

Figure 16a is a first schematic diagram of the separation process of the synchronization header part and the data byte part in the target service code block provided by an embodiment. Figure 16a shows the process of separating the synchronization header part and the data byte part in the 65-bit code block. For the 65-bit code block, the 1-bit synchronization header bit and the 64-bit data part in the 65-bit code block are separated. Therefore, all synchronization header bits are collected and transmitted individually, and all data bits are individually transmitted. Figure 16b is a second schematic diagram of the separation process of the synchronization header part and the data byte part in the target service code block provided by an embodiment. Figure 16b shows the process of separation of the synchronization header part and the data byte part in the 66-bit code block. For 66-bit code blocks, each code block has 2 synchronization header bits, and the 2-bit synchronization headers of all code blocks are separated and concentrated for carrying. Figure 16c is a third schematic diagram of the separation process of the synchronization header part and the data byte part in the target service code block provided by an embodiment. Figure 16c shows the process of separation of the synchronization header part and the data byte part in the 257-bit code block. For 257-bit code block, each code block has 1 synchronization header bit, and the 1-bit synchronization header of all code blocks is separated and concentrated for carrying. For code blocks with a target service code block length of 65 bits or 66 bits, after the synchronization header bits and data bits are separated, since the length of the data part is 64 bits, the payload area in a D code block is also 64 bits long. are equal, a D code block can exactly store the data bit part of a client code block, and each D code block carries the data part of a client code block. In this way, the synchronization header area and the sub-slot area are divided into the basic unit, and the sub-time slot area is divided into The slot only stores the data part of the code block. The sub-slot size can be 64 bits, or a multiple of 64 bits. In this way, a sub-slot is exactly carried by one or more D code blocks. Each sub-slot has The positions are exactly the same and arranged regularly to facilitate customer services to be mapped or Demapping simplifies processing complexity.

In one embodiment, a basic unit includes a preset number of sub-slots, and each sub-slot carries the data part of the target service code block.

In this embodiment, the preset number can be any even number.

In one embodiment, the preset number may be 480, that is, one basic unit may be divided into 480 sub-slots.

In one embodiment, mapping the synchronization header bits to the synchronization header position bearer in the basic unit includes: mapping the synchronization header bits together to the synchronization header position bearer in the basic unit; or mapping the synchronization header bits into groups and then respectively mapping them to the synchronization header position bearer in the basic unit. The synchronization header position in the base unit is carried.

In this embodiment, all the synchronization header bits can be gathered together and mapped to the synchronization header position in the basic unit for carrying. The sub-slots in the basic unit correspond to storing the data part of the target service code block. The basic unit needs to be carried when carrying The encapsulation and transmission of the basic unit frame can be completed only when the synchronization header bits of all sub-slots are collected.

FIG. 17 is a schematic diagram of a time slot arrangement position when synchronization header bits are carried in a concentrated manner according to an embodiment. As shown in Figure 17, the overhead byte OH is located in the T code block, the synchronization header bit occupies several D code blocks, each time slot occupies several D code blocks, and the position of each time slot in different D code blocks is In the same way, it is convenient to map and extract target business code blocks. FIG. 18 is a schematic diagram of another time slot arrangement position when synchronization header bits are carried intensively according to an embodiment. As shown in Figure 18, the overhead bytes are located in D code blocks, the synchronization header bits also occupy several D code blocks, and each time slot occupies several D code blocks. The position of each time slot is similar and the same, which facilitates the target service code block. Perform mapping and extraction.

In this embodiment, when the target service code block carried is 65 bits in length, each target service code block is divided into a 1-bit synchronization header part and a 64-bit data part. A basic unit is divided into 480 sub-time slots. Each sub-time slot is 64 bits in size. Each sub-time slot is carried in a fixed D code block and carries the data part of a target service code block. The position rules of all sub-time slots are the same. The data part of a target service code block is carried on a sub-slot.

In this embodiment, when the target service code block carried is 257 bits in length, for the 257-bit target service code block, the data part is 256 bits, which is four times the length of 64 bits, corresponding to 4 D code blocks. Bearing space bit size, sub-slots can be carried using 4 D code blocks.

Figure 19 is a schematic diagram of a process for centralized carrying of synchronization header bits according to an embodiment. As shown in Figure 19, the synchronization header bits can be placed before the sub-slot. In applications, the synchronization header bits can also be placed after the sub-slot. In Figure 19, there are 480 sub-slots. Each sub-slot corresponds to carrying the data part of a code block. Each code block has 1 synchronization header bit, a total of 480 synchronization header bits. The 480 synchronization header bits are concentrated to carry .

In this embodiment, all the synchronization header bits can be grouped, and then each group of synchronization header bits can be mapped to the corresponding synchronization header position in the basic unit for carrying.

In one embodiment, grouping synchronization header bits includes: setting all synchronization header bits in a preset number of sub-slots as a synchronization header group.

The preset number can include any one of 8, 16, 32, and 64.

In one embodiment, all synchronization header bits in every 8 sub-slots can be set as one group; in one embodiment, all synchronization header bits in every 16 sub-slots can be set as one group; in one In an embodiment, all synchronization header bits in every 32 sub-slots may be set as one group; in one embodiment, all synchronization header bits in every 64 sub-slots may be set as a group. In the application, any sub-time slot can be grouped into a group, and the synchronization header bits of the code blocks in a group of sub-time slots are collectively transmitted.

In one embodiment, the number of preset sync header bits included in the one sync header group is a multiple of the first preset number.

In this embodiment, there is no limit to the value of the first preset number. The preset synchronization header bits can be understood as synchronization header bits included in a synchronization header group.

In one embodiment, the first preset number is 8. Correspondingly, the preset number of synchronization header bits is one or more of the following: 8; 64; 128; 256.

In this embodiment, a synchronization header group may include 8-bit synchronization header bits, 64-bit synchronization header bits, 128-bit synchronization header bits, 256-bit synchronization header bits, etc.

In one embodiment, the synchronization header bits can be divided into many synchronization header groups. The number of synchronization header bits in each synchronization header group can be 64 bits. The synchronization header bits in each synchronization header group can be placed in a D code block. Medium load. The synchronization header group can be placed before the corresponding sub-time slot or after the corresponding sub-time slot, corresponding to the data content of the previous or subsequent sub-time slot code block.

In this embodiment, the 64-bit synchronization header bits of 64 code blocks corresponding to every 64 sub-time slots can be set as a synchronization header group; the 64-bit synchronization header bits in every 32 sub-time slots can be set as a synchronization header Group; the 64 synchronization header bits in every 16 sub-time slots can be set as a synchronization header group; the 64 synchronization header bits in every 8 sub-time slots can also be set as a synchronization header group.

FIG. 20 is a schematic diagram of a process in which synchronization header bits are divided into multiple synchronization header groups and carried according to an embodiment. In Figure 20, the synchronization header group is located before the corresponding multiple sub-slot groups. If one sub-slot only carries one target service code block, and each target service code block has only one synchronization header bit, for example, a 65-bit target service code block and a 257-bit target service code block have only one synchronization header bit, then The 64-bit synchronization header bits of the 64 code blocks corresponding to each 64 sub-time slots are set as a group; if one sub-time slot only carries 1 target service code block, and each target service code block has 2 synchronization header bits, For example, a 66-bit code block has a two-bit synchronization header, or a sub-slot carries 2 target service code blocks, and each target service code block has 1 synchronization header bit. Then the 64 synchronization header bits in every 32 sub-slots are set as a synchronization header group. If a sub-slot only carries 2 target service code blocks, and each target service code block has 2 synchronization header bits, for example, a 66-bit code block has a 2-bit synchronization header, or the sub-slot carries 4 target service codes block, and each target service code block has 1 synchronization header bit, then the 64 synchronization header bits in every 16 sub-slots are set as a synchronization header group; if one sub-slot only carries 4 target service code blocks , each target service code block has 2 synchronization header bits (for example, a 66-bit code block has two synchronization headers), or the sub-slot carries 8 target service code blocks, and each target service code block has 1 synchronization bit header bits, then the 64-bit synchronization header bits in every 8 sub-slots are set as a synchronization header group. The total number of synchronization header bits in each synchronization header group is 64 bits, which is exactly the same as the space size for carrying customer services in a D code block. This ensures that the storage locations of all synchronization header groups in the basic unit remain fixed.

In this embodiment, when receiving synchronization header bits in one synchronization header group, target service code blocks carried on sub-slots corresponding to other synchronization header groups can be mapped or encapsulated at the same time.

The synchronization header bits in each synchronization header group are concentrated for transmission. If each synchronization header group corresponds to 16 sub-time slots, the basic unit only needs to receive the target number of service code blocks in 16 sub-time slots to complete these goals. For mapping and encapsulation of service code blocks, the basic unit can receive, map, and send at the same time. It does not need to wait until all 480 sub-slot target service code blocks have been collected before mapping and sending, which can reduce the number of target service codes during mapping. The waiting delay of the block can also reduce the complexity of the processing circuit.

In one embodiment, parity bits are set in the basic unit.

In the 66-bit code block determined by the 802.3 encoding rules, the 2-bit synchronization header bit can only take two states: "10" or "01", which can achieve single-bit error detection. When a single-bit error occurs in the 2-bit synchronization header bits during transmission, the two-bit synchronization header bits become "00" or "11", so that the receiving end can detect the error in the synchronization header bits. According to the error code blocks are processed. When a 66-bit code block is compressed into a 65-bit target service code block or transcoded into a 257-bit target service code block, the synchronization header bit in the code block only has a 1-bit value, and it is impossible to determine whether there is an error in the synchronization header bit during the transmission process. , the receiving end cannot know when an error occurs in the synchronization header bits, and will process it according to the synchronization header content after the error, causing the code block to become another type of code block, such as treating the data code block as a control code block, or treating the control code block as a data code block to extract customer business processing and recover the erroneous customer business.

In this embodiment, a check bit can be added in addition to the synchronization header bit content. The check bit can detect and correct the synchronization header bit content. When an error occurs in the synchronization header bit, it can be calculated which bit in the synchronization header bit is Bit errors occur, and the error content is corrected. According to the principle of information bit error detection and error correction, for m-bit length information bits, k-bit check bits are added, and the erroneous bits in the information bits can be detected under the condition that m+k+1<2 ^k . This in turn corrects the transmitted erroneous information bits.

In this embodiment, the check bits set in the basic unit may include first check bits and second check bits. The first parity bits and the second parity bits may include different numbers of parity bits.

In one embodiment, the check bits include first check bits, and the first check bits indicate that a preset check algorithm is used to check and correct the synchronization header bits in the target service code block.

The preset verification algorithm includes one or more of the following: BCH code; RS code; Hamming code.

In this embodiment, a first check bit can be set in the synchronization header bits, and the synchronization header bits in the target service code block can be checked and error corrected through the first check bit. The first check bit can use BCH code, RS code, Hamming code and other algorithms for verification and error correction.

In one embodiment, when the length of the synchronization header bits is less than 502 bits, it is only necessary to add a first check bit of length 9 bits to implement verification and error correction of the synchronization header bits. In application, for a 65-bit target service code block, there are 480 sub-slots on the basic unit, and each sub-slot carries the data part of a target service code block, then the synchronization headers of the 480 code blocks have a total of 480 synchronization header bits. , 480 synchronization header bits plus 9 first check bits are combined and transmitted. The 9 first check bits can be used to implement the checksum error correction of the 480 synchronization header bits.

In one embodiment, when the synchronization header bits are carried together for transmission, a check value, that is, a check bit, can be set correspondingly. FIG. 21 is a first structural schematic diagram of a basic unit including check bits provided by an embodiment. As shown in Figure 21, a check value is added after the synchronization header bit. When a single-bit error occurs in the synchronization header bit, the check value can be used to determine which position of the synchronization header bit has an error, and then correct the erroneous synchronization header bit.

In an embodiment, when the synchronization header bits are sent using a packet bearer, a corresponding check value can be set for each synchronization header group. Figure 22 is a second structural schematic diagram of a basic unit including check bits provided by an embodiment. As shown in Figure 22, a check value is added after the synchronization header bits in each synchronization header group.

In one embodiment, the first check bits include different number of check bits, and the different number of check bits correspond to different error correction capabilities; the number of check bits included in the first check bits is the same as The sum of the number of checked synchronization header bits corresponding to the first check bit is a multiple of the second preset number.

In this embodiment, the second preset number can be any integer value, and is not limited here.

In one embodiment, the second preset number is 8. Correspondingly, multiples of the second preset number include one or more of the following: 8; 32; 64; 128.

In this embodiment, the second preset number can be 8, then the sum of the number of check bits included in the first check bit and the number of checked synchronization header bits corresponding to the first check bit is 8. Multiples can include 8, 32, 64, 128, etc.

In one embodiment, the number of check bits of the first check bit includes one or more of the following:

7 check bits, corresponding to 1 bit of error correction capability, the sum of the corresponding number of first check bits and the number of first checked synchronization header bits corresponding to the first check bit is 64, so The number of first synchronization header bits to be verified is 57; 13 check bits, corresponding to 2 bits of error correction capability, the corresponding first check bit number and the second check bit corresponding to the first check bit The sum of the number of synchronization header bits to be verified is 64, the number of bits of the second synchronization header to be verified is 51; 8 check bits, corresponding to 1 bit of error correction capability, corresponding to the first check bit The sum of the number of bits and the number of third check synchronization header bits corresponding to the first check bit is 128, and the number of third check synchronization header bits is 120; 15 check bits correspond to error correction The capacity is 2 bits. The sum of the corresponding number of first check bits and the number of fourth check synchronization header bits corresponding to the first check bit is 128. The fourth checked synchronization header bits The number is 113; 22 check bits, corresponding to 3 bits of error correction capability, the sum of the corresponding number of first check bits and the number of fifth check synchronization header bits corresponding to the first check bit is 128. The number of bits of the fifth synchronization header to be verified is 106.

In this embodiment, using different check bits can correspond to different error correction capabilities. One bit of error correction capability can be understood as the ability to correct one erroneous bit, and 2 bits of error correction capability can be understood as the ability to correct 2 erroneous bits. The ability to make error corrections.

In one embodiment, when the sum of the number of first check bits and the number of checked synchronization header bits corresponding to the first check bit is equal to 64, 57 synchronization header bits and 7 check bits can be used, The corresponding error correction capability is 1 bit.

In one embodiment, when the sum of the number of first check bits and the number of checked synchronization header bits corresponding to the first check bit is equal to 64, 51 synchronization header bits and 13 check bits may also be used. , the corresponding error correction capability is 2 bits.

In one embodiment, when the sum of the number of first check bits and the number of checked synchronization header bits corresponding to the first check bit is equal to 128, 120 synchronization header bits and 8 check bits can be used, The corresponding error correction capability is 1 bit.

In one embodiment, when the sum of the number of first check bits and the number of checked synchronization header bits corresponding to the first check bit is equal to 128, 113 synchronization header bits and 15 check bits may also be used. , corresponding to 2 bits of error correction capability.

In one embodiment, when the sum of the number of first check bits and the number of checked synchronization header bits corresponding to the first check bit is equal to 128, 106 synchronization header bits and 22 check bits may also be used. , corresponding to 3 bits of error correction capability.

For example, there are 57 synchronization header bits in each group, and 7 check bits are added to combine and transmit together. The BCH code algorithm is used, BCH(64,57,t=1), which means that the entire bit length is 64 bits, which is exactly one D The code block can carry 57 information bits (i.e. synchronization header bits) and check bits. 64-57=7 bits, t=1 means that error correction can be performed in a 1-bit scenario, so that error correction of a single bit error in the 57-bit synchronization header bit can be achieved. The BCH (64,51,t=2) algorithm can also be used, which means that the entire bit length is 64 bits, the information bits are 51 bits, the check bits 64-51=13 bits, and t=2 means the error correction capability is 2 bits, capable of error correction in scenarios where up to 2 bit errors occur among the 51 synchronization header bits. When the total number of synchronization header bits and check bits is 64 bits, they can be carried in one D code block. When the total number of synchronization header bits and check bits is 128 bits, they can be stored in 2 D code blocks. In this case, you can use The algorithm is BCH (128, 120, t = 1): it means that the entire bit length is 128 bits, of which the synchronization header bit is 120 bits, the check bit is 128-120 = 8 bits, t = 1 means that 1 bit can be achieved Error correction in bit error scenarios. When using the BCH (128, 113, t = 2) algorithm, it means that the entire bit length is 128 bits, of which the synchronization header bits are 113 bits, the check bits are 128-113 = 15 bits, and t = 2 means that the maximum that can be achieved is no more than 2 Error correction in bit-error scenarios. When using the BCH (128, 106, t = 3) algorithm, it means that the entire bit length is 128 bits, of which the synchronization header bit is 106 bits, the check bit is 128-106 = 22 bits, t = 3 means that the maximum that can be achieved is no more than 3 Error correction in bit-error scenarios.

In this embodiment, a second check bit can be set in the synchronization header bits, and the second check bit can perform verification and error correction on the overhead bits and synchronization header bits in the target service code block.

In one embodiment, the basic unit includes a second check bit, and the second check bit indicates checking and error correction of the combined bits in the target service code block, and the combined bit is composed of the The target service code block is composed of a first preset number of overhead bits and a second preset number of synchronization header bits, and the first preset number and the second preset number are different number of bits.

In this embodiment, the first preset number of digits can be any number of digits, and the second preset number of digits can be any number of digits different from the first preset number of digits.

In this embodiment, the second check bit can effectively protect the erroneous bits in the synchronization header bits. In the application, the overhead part information, that is, the overhead bits, and the synchronization header information, that is, the synchronization header bits, can be protected together.

In one embodiment, the second check bits include 7 check bits. Correspondingly, the first preset number of overhead bits is 33 overhead bits, and the second preset number of overhead bits is 24. Bit synchronization header bit.

In this embodiment, when the target service code block includes 33 overhead bits and 24 synchronization header bits, 7 check bits can be added to perform checksum error correction on 57 bits.

For example, in Figure 22, there are 57 synchronization header bits in each bit header group, and 7 check bits are added for verification. When there are 480 time slots in the basic unit, each time slot has only 1 code block, and each code block has only 1 synchronization header bit, there are a total of 480 synchronization header bits, and the synchronization header is divided into 9 groups, the first group is 24 Bit synchronization header; each group from the second to ninth group has 57-bit synchronization header, that is, 480=24+8*57. First group lieutenant general The 33 overhead bits and the 24 synchronization header bits are combined into 57 bits, and the 33 overhead bits and the 24 synchronization header bits are checked and corrected using 7 check bits. From the second group to the ninth group, the 57-bit synchronization header uses 7 parity bits for verification and error correction.

An embodiment of the present application also provides a carrying device. Figure 23 is a schematic structural diagram of a bearing device according to an embodiment. As shown in Figure 23, the bearing device can be configured in communication equipment and includes:

The encoding module 110 is configured to encode customer services to form a service code block stream; the processing module 120 is configured to process the service code block stream to obtain a target service code block; the bearer module 130 is configured to encode the target service code block The code block is mapped to a sub-slot in a basic unit, which is a set of multiple code blocks with a fixed structure, and the corresponding sub-slot is a fixed-length bit carrying space.

The bearer device of this embodiment maps customer services with a rate lower than 5G to sub-slots in the basic unit through the bearer module, thereby achieving high-quality, high-efficiency, and high-reliability transmission.

In one embodiment, the processing includes one or more of the following:

In one embodiment, the structure of the fixed-structure code block includes a start code block, one or more data code blocks, and an end code block; the start code block is used to indicate the start of the basic unit; the data code block is For carrying customer services; the end code block is used to indicate the end of the basic unit.

In one embodiment, the sub-time slot is obtained by dividing the payload area in the data code block of the basic unit. One sub-time slot is located in some bit positions of multiple data code blocks. The sub-time slot The length of the gap is a multiple of the preset value.

In an embodiment, the sub-slot division method includes one or more of the following:

All sub-slots are divided into one basic unit; all sub-time slots are divided into one multiframe; wherein the multiframe is composed of multiple basic units.

In one embodiment, mapping the target service code block to be carried on a sub-slot in a basic unit includes:

Map the target service code block to a sub-slot in the basic unit for carrying, or transfer the target service code block to The service code block is mapped to multiple sub-slots in the basic unit and carried.

In an embodiment, mapping the target service code block to the sub-slot in the basic unit includes:

Separate the synchronization header bits and data in the target service code block; map the synchronization header bits to the synchronization header position bearer in the basic unit; map the data to the sub-slots in the basic unit for bearer.

In one embodiment, mapping the synchronization header bits to the synchronization header position bearer in the basic unit includes:

The synchronization header bits are mapped together to the synchronization header position bearer in the basic unit; or the synchronization header bits are grouped and mapped to the synchronization header position bearer in the basic unit respectively.

In one embodiment, a check bit module is further included, configured to set check bits in the basic unit.

In one embodiment, the check bits include first check bits, which indicate using a preset check algorithm to check and correct synchronization header bits in the target service code block. ; The preset verification algorithm includes one or more of the following: BCH code; RS code; Hamming code.

In one embodiment, the first check bits include different number of check bits, and the different number of check bits correspond to different error correction capabilities; the first check bits include the number of check bits. The sum of the number of checked synchronization header bits corresponding to the first check bit is a multiple of the second preset number.

7 check bits, corresponding to 1 bit of error correction capability, the sum of the corresponding number of first check bits and the number of first checked synchronization header bits corresponding to the first check bit is 64, so The number of first synchronization header bits to be verified is 57; 13 check bits, corresponding to 2 bits of error correction capability, corresponding to the first check bit The sum of the number of check bits and the number of second checked synchronization header bits corresponding to the first check bit is 64, and the number of second checked synchronization header bits is 51; 8 check bits, Corresponding to 1 bit of error correction capability, the sum of the corresponding number of first check bits and the number of third check synchronization header bits corresponding to the first check bit is 128, and the third checked synchronization The number of header bits is 120; 15 check bits, corresponding to 2 bits of error correction capability, the corresponding number of first check bits and the number of fourth check synchronization header bits corresponding to the first check bit The sum is 128, the number of the fourth verified synchronization header bits is 113; 22 check bits, corresponding to 3 bits of error correction capability, the corresponding number of first check bits and the first check bit The sum of the number of fifth verification synchronization header bits corresponding to the parity bits is 128, and the number of fifth verification synchronization header bits is 106.

In one embodiment, the basic unit includes a second check bit, and the second check bit indicates that the combined bits in the target service code block are checked and corrected, and the combined bits are composed of the The target service code block is composed of a first preset number of overhead bits and a second preset number of synchronization header bits, and the first preset number and the second preset number are different number of bits.

In one embodiment, the second check bits include 7 check bits. Correspondingly, the first preset number of overhead bits is 33 overhead bits, and the second preset number of overhead bits is 24 synchronization header bits.

In one embodiment, the basic unit transmits through a time slot bearer of Flexible Ethernet.

In one embodiment, an insertion module is further included, configured to insert one or more of the following code blocks between the basic units:

At least one idle code block; at least one maintenance information management code block; the maintenance information management code block is used to monitor the service quality status of the communication channel, and the communication channel is a channel carrying basic units.

The bearing device proposed in this embodiment has the same concept as the bearing method proposed in the above embodiment. Technical details not described in detail in this embodiment can be referred to any of the above embodiments, and this embodiment has the same effect as performing the bearing method.

An embodiment of the present application also provides a communication device. Figure 24 is a schematic diagram of the hardware structure of a terminal device provided by an embodiment. As shown in Figure 24, the terminal device provided by the present application includes a memory 520, a processor 510 and A computer program is stored in the memory and can be run on the processor. When the processor 510 executes the program, the above-mentioned carrying method is implemented.

The terminal device may also include a memory 520; the processor 510 in the terminal device may be one or more, one processor 510 is taken as an example in Figure 24; the memory 520 is used to store one or more programs; the one or more A program is executed by the one or more processors 510, so that the one or more processors 510 implement the bearer method as described in the embodiment of this application.

The terminal device also includes: a communication device 530, an input device 540, and an output device 550.

The processor 510, memory 520, communication device 530, input device 540 and output device 550 in the terminal device can be connected through a bus or other means. In Figure 24, connection through a bus is taken as an example.

The input device 540 may be used to receive input numeric or character information, and generate key signal input related to user settings and function control of the terminal device. The output device 550 may include a display device such as a display screen.

Communication device 530 may include a receiver and a transmitter. The communication device 530 is configured to perform information transceiver communication according to the control of the processor 510 .

As a computer-readable storage medium, the memory 520 can be configured to store software programs, computer-executable programs and modules, such as program instructions/modules corresponding to the carrying method described in the embodiments of the present application (for example, the encoding module 110 in the carrying device , processing module 120 and bearer module 130). The memory 520 may include a stored program area and a stored data area, where the stored program area may store an operating system and an application program required for at least one function; the stored data area may store data created according to the use of the terminal device, etc. In addition, memory 520 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some examples, the memory 520 may include memory located remotely relative to the processor 510, and these remote memories may be connected to the terminal device through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.

Embodiments of the present application also provide a storage medium. The storage medium stores a computer program. When the computer program is executed by a processor, any of the carrying methods described in the embodiments of the present application is implemented.

The carrying method includes: encoding customer services to form a service code block stream; processing the service code block stream to obtain a target service code block; mapping the target service code block to a sub-time slot in a basic unit Bearing, the basic unit is a set of multiple code blocks with a fixed structure, and the corresponding sub-slot is a bearer space of fixed length bits.

The computer storage medium in the embodiment of the present application may be any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but is not limited to: an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. Examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more conductors, a portable computer disk, a hard drive, Random Access Memory (RAM), Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM), flash memory, optical fiber, portable CD-ROM, optical storage devices, Magnetic storage device, or any suitable combination of the above. A computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave carrying computer-readable program code therein. Such propagated data signals may take many forms, including but not limited to: electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device .

Program code embodied on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, radio frequency (Radio Frequency, RF), etc., or any suitable combination of the above.

Computer program code for performing operations of the present application may be written in one or more programming languages, including object-oriented programming languages such as Java, Smalltalk, C++, and conventional A procedural programming language, such as the "C" language or similar programming language. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In situations involving remote computers, the remote computer can be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (such as an Internet service provider through the Internet). connect).

The above descriptions are only exemplary embodiments of the present application and are not used to limit the protection scope of the present application.

Those skilled in the art will understand that the term user terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser or a vehicle-mounted mobile station.

Generally speaking, the various embodiments of the present application may be implemented in hardware or special purpose circuitry, software, logic, or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the application is not limited thereto.

Embodiments of the present application may be implemented by a data processor of the mobile device executing computer program instructions, for example in a processor entity, or by hardware, or by a combination of software and hardware. Computer program instructions may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or in the form of a Source or object code written in any combination of one or more programming languages.

Any block diagram of a logic flow in the figures of this application may represent program operations, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program operations and logic circuits, modules, and functions. Computer programs can be stored on memory. The memory may be of any type suitable for the local technical environment and may be implemented using any suitable data storage technology, such as but not limited to Read-Only Memory (ROM), Random Access Memory (RAM), optical Memory devices and systems (Digital Video Disc (DVD) or Compact Disk (CD)), etc. Computer-readable media may include non-transitory storage media. The data processor may be any device suitable for the local technical environment Types, such as but not limited to general-purpose computers, special-purpose computers, microprocessors, digital signal processors (Digital Signal Processing, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic devices (Field-Programmable Gate Array) , FPGA) and processors based on multi-core processor architecture.

Claims

A carrying method including:

Encode customer services to form a service code block stream;

Process the service code block stream to obtain the target service code block;

The target service code block is mapped to a sub-slot in a basic unit and carried. The basic unit is a set of multiple code blocks with a fixed structure. The sub-slot is a fixed-length bit bearing space.
The method according to claim 1, wherein the processing includes at least one of the following:

Add or delete idle code blocks in the service code blocks included in the service code block stream; add or delete maintenance management information code blocks in the service code blocks included in the service code block stream; modify the service code blocks The service code blocks included in the stream are synchronized header compressed; the service code blocks included in the service code block stream are transcoded.
The method according to claim 1, wherein the plurality of code blocks with a fixed structure include a start code block, at least one data code block and an end code block;

The start code block is used to indicate the start of the basic unit;

The data code block is used to carry customer services;

The end code block is used to indicate the end of the basic unit.
The method according to claim 3, wherein the plurality of code blocks with a fixed structure further include the following parts: an overhead part, a synchronization header part and a synchronization header verification part;

The overhead portion is located at the center front position of the base unit, and the overhead portion indicates the feature content of the base unit.
The method according to claim 1, wherein the sub-time slot is obtained by dividing the payload area in the data code block of the basic unit, and one sub-time slot is located in some bit positions of multiple data code blocks. , the length of the sub-slot is a multiple of the preset value.
The method according to claim 1, wherein the sub-slot division method includes at least one of the following:

Divide all sub-time slots in a basic unit; divide all sub-time slots in a multi-frame;

Wherein, the multiframe is composed of multiple basic units.
The method according to claim 1, wherein mapping the target service code block to be carried on a sub-slot in a basic unit includes:

The target service code block is mapped to be carried on one sub-time slot in the basic unit, or the target service code block is mapped to be carried on multiple sub-time slots in the basic unit.
The method according to claim 7, wherein mapping the target service code block to be carried on a sub-slot in a basic unit includes:

Separate the synchronization header bits and data in the target service code block;

Map the synchronization header bits to the synchronization header position bearer in the basic unit;

The data is mapped to the sub-slots in the basic unit and carried.
The method according to claim 8, wherein a basic unit includes a preset number of sub-slots, and each sub-slot carries the data part of the target service code block.
The method according to claim 8, wherein mapping the synchronization header bits to a synchronization header position bearer in the basic unit includes:

The synchronization header bits are mapped together to the synchronization header position bearer in the basic unit; or the synchronization header bits are grouped and mapped to the synchronization head position bearer in the basic unit respectively.
The method according to claim 10, wherein said grouping the synchronization header bits includes:

Set all synchronization header bits in a preset number of sub-slots as a synchronization header group.
The method according to claim 11, wherein the number of preset synchronization header bits included in a synchronization header group is a multiple of the first preset number.
The method according to claim 12, wherein the first preset number is 8, and the preset number of synchronization header bits is at least one of the following:

8;64;128;256.
The method of claim 1, further comprising:

A parity bit is set in the basic unit.
The method according to claim 14, wherein the check bits include first check bits, the first check bits indicate using a preset check algorithm to perform synchronization header bits in the target service code block. Checksum error correction;

The preset verification algorithm includes at least one of the following: BCH code; RS code; Hamming code.
The method according to claim 15, wherein the first check bits include different check bit numbers, and the different check bit numbers correspond to different error correction capabilities;

The sum of the number of check bits included in the first check bits and the number of checked synchronization header bits corresponding to the first check bits is a multiple of the second preset number.
The method of claim 16, wherein the second preset number is 8, and the Multiples of the two preset quantities include at least one of the following:

8;32;64;128.
The method according to claim 16, wherein the number of check bits of the first check bit includes at least one of the following:

7 check bits, corresponding to 1 bit of error correction capability. The sum of the number of check bits of the first check bit and the number of first checked synchronization header bits corresponding to the first check bit is 64 , the first verified synchronization header bit number is 57;

13 check bits, corresponding to 2 bits of error correction capability. The sum of the number of check bits of the first check bit and the number of second checked synchronization header bits corresponding to the first check bit is 64 , the second verified synchronization header bit number is 51;

8 check bits, corresponding to 1 bit of error correction capability, the sum of the number of check bits of the first check bit and the number of third check synchronization header bits corresponding to the first check bit is 128, The number of third synchronization header bits to be verified is 120;

15 check bits, corresponding to 2 bits of error correction capability. The sum of the number of check bits of the first check bit and the number of fourth check synchronization header bits corresponding to the first check bit is 128, The fourth verified synchronization header bit number is 113;

22 check bits, corresponding to 3 bits of error correction capability, the sum of the number of check bits of the first check bit and the number of fifth check synchronization header bits corresponding to the first check bit is 128, The number of fifth synchronization header bits to be verified is 106.
The method according to claim 1, wherein the basic unit includes a second check bit, the second check bit indicates checking and error correction of the combined bits in the target service code block, so The combined bits are composed of a first preset number of overhead bits and a second preset number of synchronization header bits in the target service code block, and the first preset number and the second preset number of bits are different number of digits.
The method according to claim 19, wherein the second check bits comprise 7 check bits, the first preset number of overhead bits is 33 overhead bits, and the second preset number of overhead bits is The bit is the 24-bit synchronization header bit.
The method according to claim 1, wherein the basic unit transmits through a time slot bearer of Flexible Ethernet.
The method according to claim 1, further comprising: inserting at least one of the following code blocks between the basic units:

At least one idle code block; at least one maintenance information management code block;

The maintenance information management code block is used to monitor the service quality status of the communication channel, and the communication channel is the channel carrying the basic unit.
A communication device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, any one of claims 1-22 is implemented. The carrying method described in the item.
A storage medium that stores a computer program. When the program is executed by a processor, the carrying method according to any one of claims 1-22 is implemented.