CN203406971U

CN203406971U - DCA bit signal encoding circuit in FPD-LINK LVDS video transmission

Info

Publication number: CN203406971U
Application number: CN201320556438.9U
Authority: CN
Inventors: 陈庆华
Original assignee: CHENGDU ARTEC ELECTRONICS CORP
Current assignee: CHENGDU CORPRO TECHNOLOGY CO., LTD.
Priority date: 2013-09-09
Filing date: 2013-09-09
Publication date: 2014-01-22
Anticipated expiration: 2023-09-09

Abstract

The utility model discloses a DCA bit signal encoding circuit in FPD-LINK LVDS video transmission. The DCA bit signal encoding circuit in FPD-LINK LVDS video transmission comprises a counter, a state detection unit, a state encoding and position register, an 8b-10b encoder and a control signal encoding and DCA serial output device, wherein an output end of the counter is respectively connected with the state detection unit and the control signal encoding and DCA serial output device, and an output end of the state detection unit is connected with the control signal encoding and DCA serial output device after sequentially passing through the state encoding and position register and the 8b-10b encoder. The DCA bit signal encoding circuit utilizes externally-inputted video control signals such as HS, VS and DE to complete a function of state detection, so state positioning on the video control signals is effectively realized, decoder state decoding information is provided, DCA bit series signals are generated, FPD-LINK LVDS video control signals can be processed, and various states of inputted video control signals can be normally encoded.

Description

DCA position Signal coding circuit in a kind of FPD-LINK LVDS transmission of video

Technical field

The utility model relates to a kind of FPD-LINK LVDS control signal DCA position signal generation device of video, particularly relates to DCA position Signal coding circuit in a kind of PFD-LINKII transmission of video.

Background technology

The different chipsets of FPD-Link series have been optimized in serial pay(useful) load, also optimize those application that they support simultaneously.The reference of common serial pay(useful) load is explained just as 28 Bits Serial frames.Consisting of of 28 Bits Serial frames: 24 bit data positions, 2 embedded clock informations and 2 Serial Control positions for linking.Therefore,, for the data of every 24, what reality sent is 28 bit string line positions.

The efficiency 24/28(86% of Here it is basic linkage).24 bit data are modified to balance, random and data scrambling.Doing is like this AC coupled in order to support to chain, and when transmitting relatively static data, contributes to reduce ISI(intersymbol interference) impact.These two clock bits are fixed, one high (C1) one low (C0).Dual serial control bit, is noted as DCA (A) and DCB (B) conventionally, to DES, provides information to recover data, linking status and pattern.DCA position supports 24 RGB chipsets to encode to the state of the video synchronization signal in serial data stream.DCA position plays a part crucial to recovery data, and DCA coded system provides the rule of receiving terminal decoding.

Utility model content

The purpose of this utility model is to overcome the deficiencies in the prior art, video control signal HS, VS and the DE of a kind of utilization from outside input are provided, completion status measuring ability well, effectively video control signal is done to state location, provide its decoder states decoded information, DCA position Signal coding circuit in the FPD-LINK LVDS transmission of video of generation DCA Bits Serial signal.

The purpose of this utility model is achieved through the following technical solutions: DCA position Signal coding circuit in a kind of FPD-LINK LVDS transmission of video, and it comprises counter, state detection unit, state encoding and location register, 8b-10b encoder and control signal coding and DCA serial follower; Wherein, counter is for obtaining the count value of cycle count, for Signal coding provides temporal information; State detection unit is for carrying out state-detection to input signal, and in the cycle, records the information of its correlation behavior in count value; The counting position when state information that state encoding and location register provide state detection unit is carried out state encoding and state switching is deposited; 8b-10b encoder carries out secondary coding by information, and 8b data are converted into 10b data; Control signal coding and DCA serial follower are exported 10b data according to a definite sequence serial, form the DCA signal of serial output; The output of counter is connected with control signal coding and DCA serial follower with state detection unit respectively, and the output of state detection unit is successively by connection control signal coding and DCA serial follower after state encoding and location register and 8b-10b encoder.

Described input signal comprises HS signal, VS signal and DE signal.

The beneficial effects of the utility model are:

1, utilize from video control signal HS, VS and the DE of outside input, completion status measuring ability well, effectively video control signal is done to state location, its decoder states decoded information is provided, generate DCA Bits Serial signal, can process FPD-LINK LVDS video control signal, to the various states of input video control signal, can normally encode;

2, an integrated protection mechanism, the secondary coding setting of 8b-10b device, makes DCA position more can suppress the error interference bringing in transmission, and all coding circuits are all based on a simple counter, and whole cataloged procedure is controlled in order.

Accompanying drawing explanation

Fig. 1 is system configuration schematic diagram of the present utility model;

Fig. 2 is that HS signal condition of the present utility model detects and the location drawing;

Fig. 3 is that DE signal condition of the present utility model detects and the location drawing;

Fig. 4 is that VS signal condition of the present utility model detects and the location drawing;

Fig. 5 is the utility model HS, VS and DE signal condition code pattern;

Fig. 6 is the utility model control signal coding and DCA Bits Serial output map.

Embodiment

Below in conjunction with the drawings and specific embodiments, further illustrate the technical solution of the utility model, but the content that the utility model is protected is not limited to the following stated.

As shown in Figure 1, DCA position Signal coding circuit in a kind of FPD-LINK LVDS transmission of video, it comprises counter, state detection unit, state encoding and location register, 8b-10b encoder and control signal coding and DCA serial follower; Wherein, counter is for obtaining the count value cycle of cycle count, if selection cycle is 130, for Signal coding provides temporal information; State detection unit is used for input signal to carry out state-detection, and in the interior information that records its correlation behavior of count value cycle 130; The counting position when state information that state encoding and location register provide state detection unit is carried out state encoding and state switching is deposited; 8b-10b encoder carries out secondary coding by information, and 8b data are converted into 10b data, to improve information antijamming capability; Control signal coding and DCA serial follower are exported 10b data (if selection cycle is at 130 o'clock according to a definite sequence serial, 10b data are formed to 13 10b data in order, by serial, export this 130 Bit datas again), form the DCA signal that serial is exported; The output of counter is connected with control signal coding and DCA serial follower with state detection unit respectively, and the output of state detection unit is successively by connection control signal coding and DCA serial follower after state encoding and location register and 8b-10b encoder.

Described input signal comprises HS signal, VS signal and DE signal.

In FPD-LINK LVDS transmission of video of the present utility model, the course of work of DCA position Signal coding circuit comprises the following steps:

S1: input control signal DE, HS and VS are encoded, detect rising edge and the trailing edge of DE, HS and VS signal;

S2: counter be take a fixed value as loop cycle counting, if selection cycle is 130, obtains respectively rising edge and counter values corresponding to trailing edge of DE, HS and VS and deposits;

S3: in the difference interval within the fixed cycle, the conditional code of DE signal and row field signal is delivered to 8b_10b coder transitions with rise and fall along the locating information of locating and become 10b data, and each of this data assignment within the fixed cycle, to DCA position, is realized and take DE, HS and the VS Signal coding that fixed value is loop cycle.

Row field signal in step S3 comprises HS signal and VS signal, and wherein, HS signal is row signal, and VS signal is field signal.

As shown in Figures 2 and 3, HS and DE signal have 6 states within the fixed cycle 130, first decline and rise afterwards, first rise and decline afterwards, single trailing edge, single rising edge, high level state and low level state, correspondence is encoded to 3 Bit datas 100 respectively, 101, 010, 011, 001 and 000, by counter records, be there is the position of trailing edge and rising edge simultaneously, in figure, HS_LOC1 and HS_LOC2 represent that the position of rising edge and trailing edge information appears in HS signal, in figure, DE_LOC1 and DE_LOC2 represent that the position of trailing edge and rising edge information appears in DE signal.

As shown in Figure 4, VS signal only has 4 states within the fixed cycle 130, be single trailing edge, single rising edge, high level state and low level state, correspondence is encoded to 2

bit numbers

10,11,01 and 00 respectively, by counter records, occurred the position of trailing edge or rising edge, and the VS_LOC1 in figure represents that the position along information appears in VS signal simultaneously.

As shown in Figure 5, HS and DE have respectively 3 bit status coded messages, VS has 2 bit status coded messages, form the register information state_code of 8, HS_LOC1, HS_LOC2, DE_LOC1, DE_LOC2 and VS_LOC1 are also 8 digit counter numerical value simultaneously, through upper these data, through 8b-10b, convert 6 10 Bit datas to.

Fig. 6 is the data of interior DCA Bits Serial output of fixed cycle 130, the information of obtaining within the fixed cycle is encoded in certain sequence, i.e. state_code, HS_LOC1, HS_LOC2, VS_LOC1, DE_LOC1, DE_LOC2,0,0,0,252,252,252,252.Above data are all 10 Bit datas after 8b-10b code conversion, 130 bit data altogether, and the output of DCA Bits Serial carry out serial output successively by this 130 bit data high position.

Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing), unless narration especially all can be replaced by other equivalences or the alternative features with similar object.That is,, unless narration especially, each feature is an example in a series of equivalences or similar characteristics.

Although the utility model in conjunction with the preferred embodiments mode is described, it will be appreciated by those skilled in the art that and do not deviating under the prerequisite of spirit and scope of the present utility model, can be by using known equivalent way to change the utility model.Description related to the preferred embodiment is considered to be exemplary description rather than limits scope of the present utility model above, and scope of the present utility model is limited by the accompanying claims.

Claims

1. a DCA position Signal coding circuit in FPD-LINK LVDS transmission of video, is characterized in that: it comprises counter, state detection unit, state encoding and location register, 8b-10b encoder and control signal coding and DCA serial follower; Wherein, counter is for obtaining the count value of cycle count, for Signal coding provides temporal information; State detection unit is for carrying out state-detection to input signal, and in the cycle, records the information of its correlation behavior in count value; The counting position when state information that state encoding and location register provide state detection unit is carried out state encoding and state switching is deposited; 8b-10b encoder carries out secondary coding by information, and 8b data are converted into 10b data; Control signal coding and DCA serial follower are exported 10b data according to a definite sequence serial, form the DCA signal of serial output; The output of counter is connected with control signal coding and DCA serial follower with state detection unit respectively, and the output of state detection unit is successively by connection control signal coding and DCA serial follower after state encoding and location register and 8b-10b encoder.

2. DCA position Signal coding circuit in a kind of FPD-LINK LVDS transmission of video according to claim 1, is characterized in that: described input signal comprises HS signal, VS signal and DE signal.