CN106803903A - The decoding circuit of video control signal in a kind of FPD LINK transmission of video - Google Patents
The decoding circuit of video control signal in a kind of FPD LINK transmission of video Download PDFInfo
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- CN106803903A CN106803903A CN201710141522.7A CN201710141522A CN106803903A CN 106803903 A CN106803903 A CN 106803903A CN 201710141522 A CN201710141522 A CN 201710141522A CN 106803903 A CN106803903 A CN 106803903A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
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- Synchronisation In Digital Transmission Systems (AREA)
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Abstract
The invention discloses a kind of decoding circuit of video control signal in FPD LINK transmission of video, including：Counter, with a fixed cycle cycle count；DCA signals deposit extraction unit, DCA Bits Serials data are stored according to the fixed cycle, when the DCA Bits Serials data storage has synchronizing sequence, the location information at video effective data gating signal DE, the status information of row field signal and rise and fall edge is sent within the current fixed cycle；Decoder module, receives the location information and is converted into eight bit data；State decoded positions deposit unit, for storing the eight bit data；State recovery unit, for recovering video effective data gating signal DE, video line synchronization signal HS and video field synchronizing signal VS signals according to the location information.The present invention can decode that DCA Bits Serial signals, the FPD LINK LVDS signals of input is normally decoded.
Description
Technical field
The present invention relates to FPD-LINK II LVDS technical field of video transmission, more particularly to a kind of FPD-LINK videos
The decoding circuit of video control signal in transmission.
Background technology
Serial pay(useful) load optimizes the different chipsets of FPD-LINK series, while those for also optimizing their supports should
With.The reference of common serial pay(useful) load is explained just as 28 Bits Serial frames.The composition of 28 Bits Serial frames is：24 data bit, 2
The Serial Control position that the embedded clock information in position and 2 are used for link.Therefore, the data for every 24, what is actually occurred is
28 bit string line positions.This thus, the efficiency of basic linkage is 24/28（86%）.24 data be modified to it is balance, random and
The data of scrambling, this is done to support the AC coupled for chaining, and when the data of relative quiescent are transmitted, help to subtract
Few ISI（Intersymbol interference）Influence.Two clock bits are fixed, and one high（C1）, one low（C0）.Dual serial control bit
Generally it is noted as DCA（A）And DCB（B）, for providing information to recover data, linking status and pattern to DES.DCA branch
24 RGB chipsets are held to encode the state of the video synchronization signal in serial data stream.DCA plays to recovering data
Crucial effect, and DCA coded systems provide the rule of receiving terminal decoding.
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, there is provided video control in a kind of FPD-LINK transmission of video
The decoding circuit of signal, can decode that DCA Bits Serial signals, the FPD-LINK LVDS signals of input is normally decoded.
The purpose of the present invention is achieved through the following technical solutions：Video control in a kind of FPD-LINK transmission of video
The decoding circuit of signal, including：
Counter, with a fixed cycle cycle count；
DCA signals deposit extraction unit, DCA Bits Serials data are stored according to the fixed cycle, when the DCA bit strings
When having synchronizing sequence in row data, by video effective data gating signal DE and the state of row field signal within the current fixed cycle
The location information of information and video effective data gating signal DE and row field signal rise and fall at sends；
Decoder module, the location information that the reception DCA signals deposit extraction unit sends is converted into eight bit data；
State decoded positions deposit unit, for storing the eight bit data that the decoder module is obtained；
State recovery unit, for recovering video according to the location information stored in the state decoded positions deposit unit
Valid data gating signal DE, video line synchronization signal HS and video field synchronizing signal VS.
Preferably, the DCA signals deposit extraction unit includes：
Memory module, for the DCA Bits Serials data to be stored according to the fixed cycle；
Synchronizing sequence detection module, for detecting in the DCA Bits Serials data whether there is synchronizing sequence；
Data conversion module, during for having synchronizing sequence in the DCA Bits Serials data, by video effective data gating signal
The status information of DE, video line synchronization signal HS and video field synchronizing signal VS, and video effective data gating signal DE, regard
The rise and fall of frequency line synchronising signal HS and video field synchronizing signal VS deposit into ten bit data along corresponding counter values；
Locating module, for the DCA be signal in have synchronizing sequence when, by DE and row field signal within the current fixed cycle
Location information at of status information and DE and row field signal rise and fall send.
Preferably, the decoder module is 10B-8B decoder modules.
Preferably, the fixed cycle is 130.
The beneficial effects of the invention are as follows：The present invention can decode that DCA Bits Serial signals, make the FPD-LINK LVDS of input
Signal can normally be decoded.
Brief description of the drawings
Fig. 1 is the circuit block diagram of the decoding circuit of video control signal in a kind of FPD-LINK transmission of video of the invention；
Fig. 2 is the schematic diagram of DCA Bits Serial data in the fixed cycle；
Fig. 3 is the schematic diagram of state decoded positions deposit unit；
Fig. 4 is recovered a graph of a relation between signal by state recovery unit；
Fig. 5 is recovered another graph of a relation between signal by state recovery unit；
Fig. 6 is recovered another graph of a relation between signal by state recovery unit.
Specific embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to
It is as described below.
As shown in figure 1, in a kind of FPD-LINK transmission of video video control signal decoding circuit, including counter, DCA
Signal deposit extraction unit, decoder module, state decoded positions deposit unit and state recovery unit.
The counter is counted with a fixed cycle cycle count, the i.e. counter by loop cycle of a fixed value, than
Such as with 130 for the cycle is circulated counting.
The DCA signals deposit extraction unit, and DCA Bits Serials data are stored according to the fixed cycle, work as institute
State in DCA Bits Serial data when having synchronizing sequence, by video effective data gating signal DE and Hang Chang within the current fixed cycle
The location information hair of the status information and video effective data gating signal DE of signal and row field signal rise and fall at
Go out.
Specifically, the DCA signals deposit extraction unit includes memory module, synchronizing sequence detection module, data conversion
Module and locating module.Memory module is used to be stored the DCA Bits Serials data according to the fixed cycle；Synchronous sequence
Whether row detection module is used to detect in the DCA Bits Serials data there is synchronizing sequence；Data conversion module is used in the DCA
It is when having synchronizing sequence in Bits Serial data, video effective data gating signal DE, video line synchronization signal HS and video field is same
The status information of step signal VS, and video effective data gating signal DE, video line synchronization signal HS and video field synchronization letter
The rise and fall of number VS deposit into ten bit data along corresponding counter values；Locating module is used in the DCA is signal
When having synchronizing sequence, within the current fixed cycle by the status information of video effective data gating signal DE and row field signal, with
And the location information of video effective data gating signal DE and row field signal rise and fall at sends.
The location information that the decoder module reception DCA signals deposit extraction unit sends is converted into eight bit data,
Wherein decoder module uses 10B-8B decoder modules.As shown in Fig. 2 acquired information within the fixed cycle is compiled in certain sequence
Code, i.e. state_code, HS_LOC1, HS_LOC2, VS_LOC1, DE_LOC1, DE_LOC2,0,0,0,252,252,252,
252, above-mentioned data are all 8 bit datas that 10B-8B decoder modules obtained after decoding conversion, and the input of DCA Bits Serials is
Serial input is carried out successively by an above-mentioned data high position.
State decoded positions deposit unit is used to store the eight bit data that the decoder module is obtained.As shown in figure 3, video
Line synchronising signal HS and video effective data gating signal DE have 3 bit status coding informations, video field synchronizing signal VS respectively
There are 2 state encoding information, the register information state_code of composition one 8.While HS_LOC1, HS_LOC2, DE_
LOC1, DE_LOC2 and VS_LOC1 are also 8 digit counter numerical value；The above data are turned by the decoding of 10B-8B decoder modules
Obtained after changing.
State recovery unit is used to be recovered according to the location information stored in the state decoded positions deposit unit
Video effective data gating signal DE, video line synchronization signal HS and video field synchronizing signal VS.As shown in Figure 4, Figure 5 and Figure 6,
As a example by being 130 by the fixed cycle, video line synchronization signal HS and video effective data gating signal DE have 6 within the fixed cycle
State, that is, rise after falling before, first rise decline afterwards, single trailing edge, single rising edge, high level state and low level shape
State, corresponds to be encoded to 3 bit datas 100,101,010,011,001 and 000 respectively, while under being occurred by internal counter record
Drop edge and the position of rising edge, are represented that video line synchronization signal HS occurs along the position of information by HS_LOC1 in figure and HS_LOC2
Put, in figure DE_LOC1 and DE_LOC2 come represent video effective data gating signal DE occur along information position.Video field is same
Step signal VS only has 4 states, i.e., single trailing edge, single rising edge, high level state and low level shape within the fixed cycle
State, corresponds to be encoded to 2 bit numbers 10,11,01 and 00 respectively, while there is trailing edge or rising edge by internal counter record
Position, is represented that video field synchronizing signal VS occurs along the position of information by the VS_LOC1 in figure.
The above is only the preferred embodiment of the present invention, it should be understood that the present invention is not limited to described herein
Form, is not to be taken as the exclusion to other embodiment, and can be used for various other combinations, modification and environment, and can be at this
In the text contemplated scope, it is modified by the technology or knowledge of above-mentioned teaching or association area.And those skilled in the art are entered
Capable change and change does not depart from the spirit and scope of the present invention, then all should be in the protection domain of appended claims of the present invention
It is interior.
Claims (4)
1. in a kind of FPD-LINK transmission of video video control signal decoding circuit, it is characterised in that including：
Counter, with a fixed cycle cycle count；
DCA signals deposit extraction unit, DCA Bits Serials data are stored according to the fixed cycle, when the DCA bit strings
When having synchronizing sequence in row data, by video effective data gating signal DE and the state of row field signal within the current fixed cycle
The location information of information and video effective data gating signal DE and row field signal rise and fall at sends；
Decoder module, the location information that the reception DCA signals deposit extraction unit sends is converted into eight bit data；
State decoded positions deposit unit, for storing the eight bit data that the decoder module is obtained；
State recovery unit, for recovering video according to the location information stored in the state decoded positions deposit unit
Valid data gating signal DE, video line synchronization signal HS and video field synchronizing signal VS.
2. in a kind of FPD-LINK transmission of video according to claim 1 video control signal decoding circuit, its feature
It is that the DCA signals deposit extraction unit includes：
Memory module, for the DCA Bits Serials data to be stored according to the fixed cycle；
Synchronizing sequence detection module, for detecting in the DCA Bits Serials data whether there is synchronizing sequence；
Data conversion module, during for having synchronizing sequence in the DCA Bits Serials data, by video effective data gating signal
The status information of DE, video line synchronization signal HS and video field synchronizing signal VS, and video effective data gating signal DE, regard
The rise and fall of frequency line synchronising signal HS and video field synchronizing signal VS deposit into ten bit data along corresponding counter values；
Locating module, for the DCA be signal in have synchronizing sequence when, by DE and row field signal within the current fixed cycle
Location information at of status information and DE and row field signal rise and fall send.
3. in a kind of FPD-LINK transmission of video according to claim 1 video control signal decoding circuit, its feature
It is that the decoder module is 10B-8B decoder modules.
4. in a kind of FPD-LINK transmission of video according to claim 1 video control signal decoding circuit, its feature
It is that the fixed cycle is 130.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710141522.7A CN106803903B (en) | 2017-03-10 | 2017-03-10 | Decoding circuit of video control signal in FPD-LINK video transmission |
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| CN201710141522.7A CN106803903B (en) | 2017-03-10 | 2017-03-10 | Decoding circuit of video control signal in FPD-LINK video transmission |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114040151A (en) * | 2021-09-28 | 2022-02-11 | 惠州华阳通用电子有限公司 | Decoding method and device for panoramic all-around system |
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| CN106803903B (en) | 2020-09-29 |
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