CN103199869B - 8b/10b decoding circuit based on rd+ - Google Patents
8b/10b decoding circuit based on rd+ Download PDFInfo
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Abstract
The invention discloses an 8b/10b decoding circuit based on rd+. 10 bit data of external input are divided to front 6 bit data and rear 4 bit data to be respectively fed into a 6b preprocessing module and a 4b preprocessing module, and first data character data and first control character data, generated after the front 6 bit data are preprocessed through the 6b preprocessing module, are respectively sent to a 5b/6b data character decoder based on the rd+ and a 5b/6b control character decoder based on the rd+; second data character data and second control character data, generated after the rear 4 bit data are preprocessed through the4b preprocessing module, are respectively sent to a 3b/4b data character decoder based on the rd+ and a 3b/4b control character decoder based on the rd+; and data are all sent to a data merging module after the data are decoded by four decoders, and appropriate data are chosen and synthesized into 8 bit data to be outputted. The 8b/10b decoding circuit based on the rd+ can save a large quantity of resources of a memorizer.
Description
Technical field
The present invention relates to a kind of decoding circuit, more particularly to a kind of 8b/10b decoding circuits based on rd+.
Background technology
8b/10b, also referred to as 8 bit/10 bits, are the encoding mechanisms of many high-speed serial bus employings at present, such as
1394b, Serial ATA, PCI Express, Infini-band, Fibre Channel (netted passage), RapidIO etc. are total
Line or network etc..
One of characteristic of 8b/10b codings is to ensure DC balances, using 8b/10b coded systems, " 0 " that can cause to send,
" 1 " quantity keeps basically identical, and continuous " 1 " or " 0 " must be inserted into one that is, per 5 less than 5 after continuous " 1 " or " 0 "
Position " 0 " or " 1 ", so as to ensure signal DC balance, it that is, link time-out when will not occur DC imbalance.By 8b/10b
Coding, it is ensured that the serial data of transmission can correctly be restored in receiving terminal, in addition, using some special codes
(being K codes in PCI-Express buses), the work that receiving terminal can be helped to be reduced, and can be in early discovery number
According to the error of transmission of position, mistake is suppressed to continue generation.8b/10b codings are that one group of continuous 8 data is resolved into into two groups of numbers
According to, one group 3, one group 5, it is encoded after respectively become one group 4 data and the data of a group 6, so as to constitute one
The data is activation of group 10 is gone out.Conversely, decoding is that the input data of 1 group 10 is obtained into 8 data bit through conversion.Data
What value can be unified is expressed as DX.Y or KX.Y, and wherein D is expressed as data character, and K is expressed as control character, and X represents input
Low 5 EDCBA of initial data, Y represent high 3 HGF of the initial data of input.
Existing 8b/10b decoding circuits realize that 8b/10b is decoded using the method tabled look-up mostly, with the 8b/10b of data character
As a example by decoding, existing 8b/10b decoding circuits need depositor that 512 width are 8 bits to store related data, and occupancy is deposited
Memory resource is more.
The content of the invention
The technical problem to be solved is to provide a kind of 8b/10b decoding circuits based on rd+, can save in a large number
Memory resource.
For solve above-mentioned technical problem, the present invention provide the 8b/10b decoding circuits based on rd+ by 6b pretreatment modules,
4b pretreatment modules, based on the 5b/6b data character decoders of rd+, based on the 5b/6b control character decoders of rd+, based on rd
+ 3b/4b data character decoders, based on the 3b/4b control character decoders of rd+, data combiners block and two XORs
Module composition；
Outer input data is 10 bit datas, and 10 bit data is split as front 6 bit data and rear 4 bit data,
Front 6 bit data is input to the 6b pretreatment modules, and rear 4 bit datas are input to the 4b pretreatment modules；
One current character polar signal, is separately input to the 6b pretreatment modules and the first XOR module；The current word
Symbol polar signal represents the polarity of current input character, and the 6b pretreatment modules are right under the control of current character polar signal
Front 6 bit data carries out pretreatment operation, and exports the first data character data, the first control character data and the first pole
Property change indications signal；
First XOR module is used to enter the current character polar signal and the first change in polarity indications signal
Row XOR processes and exports the second character polar signal；
The second character polar signal is separately input to the 4b pretreatment modules and the second XOR module；The 4b is pre-
Processing module carries out pretreatment operation under the control of the second character polar signal to 4 bit datas after described, and exports second
Data character data, the second control character data and the second change in polarity indications signal；
Second XOR module is used to enter the second character polar signal and the second change in polarity indications signal
The process of row XOR, produces next character polar signal, and next character polar signal is externally exported；
The first data character data input to the 5b/6b data character decoders based on rd+ are processed, and
Export the first data character decoding data and the first data character decoding indications signal；
The first control character data input to the 5b/6b control character decoders based on rd+ are processed, and
Export the first control character decoding data and the first control character decoding indications signal；
The second data character data input to the 3b/4b data character decoders based on rd+ are processed, and
Export the second data character decoding data and the second data character decoding indications signal；
The second control character data input to the 3b/4b control character decoders based on rd+ are processed, and
Export the second control character decoding data and the second control character decoding indications signal；
The first data character decoding data, the first data character decoding indications signal, the first control character solution
Code data, the first control character decoding indications signal, the second data character decoding data, the second data character decoding indications
Signal, the second control character decoding data and the second control character decode indications signal input to the data combiners block,
Processed and exported the output data and an indicator signal of one 8 bits.
The present invention can in a large number save memory resource, and by taking the 8b/10b decodings of data character as an example, the present invention only needs 83
The depositor of bit and 32 5 bits carrys out data storage, and shared storage resource is only existing 8b/10b decoding circuits
4.492%, resource saves effect highly significant.
Description of the drawings
With reference to the accompanying drawings and detailed description the present invention is further detailed explanation：
Accompanying drawing is 8b/10b decoding circuit structure chart of the embodiment of the present invention based on rd+.
Specific embodiment
Involved rd inconsistent, the also referred to as polarity that refers to run character in the present invention, that is, refer in character 1 number and
0 number is inconsistent；Wherein, rd+ is more than 1 to 0 in character, now inconsistent for just (+)；Rd- is that 1 to 0 in character is lacked,
It is now inconsistent for negative (-).
With reference to shown in accompanying drawing, the 8b/10b decoding circuits based on rd+ are split as 10 bit datas of outside input
Front 6 bit data and rear 4 bit data, are respectively fed to 6b pretreatment modules and 4b pretreatment modules.Front 6 bit data Jing 6b are pre-
After processing module pretreatment, first data character data data_6b and the first control character data ctl_6b of generation are sent respectively
Toward 5b/6b data characters decoder and the 5b/6b control character decoders based on rd+ based on rd+.4 bit data Jing 4b afterwards
After pretreatment module pretreatment, the second data character data data_4b of generation and the second control character data ctl_4b are distinguished
It is sent to the 3b/4b data characters decoder based on rd+ and the 3b/4b control character decoders based on rd+.Finally, tetra- solutions of Jing
The decoded data of code device are all sent to data combiners block, and the data combiners block selects suitable data from these data,
It is merged into the data of 8 bits and is exported by data output end dout.First XOR module to 6b pretreatment modules by exporting
The first change in polarity indications signal rd_flag_6b and current character polar signal crd carry out xor operation produce the second pole
Property change indications signal rd_6b, do further computing for controlling 4b pretreatment modules.Second XOR module is by pre- to 4b
The second change in polarity indications signal rd_flag_4b and the second change in polarity indications signal rd_6b of processing module output enters
Row xor operation, produces next character polar signal nrd and exports.
The process that front 6 bit input data changes into the data that can carry out rd+ decodings is by the 6b pretreatment modules, such as
The current character polar signal crd of fruit outside input is rd- domains, then by input data respectively according to data character transformation rule and
Control character transformation rule is transformed into rd+ domains from rd- domains, is sent to based on the 5b/6b data characters of rd+ by its outfan respectively
Decoder and the 5b/6b control character decoders based on rd+；If the current character polar signal crd of outside input is rd+
Domain, then directly by input data be sent to 5b/6b data characters decoder based on rd+ and based on rd+ by its outfan respectively
5b/6b control character decoders；In the semipolar change of process of data preprocessing, by the first change in polarity indications signal
Rd_flag_6b is exported.
The process that rear 4 bit input data changes into the data that can carry out rd+ decodings is by the 4b pretreatment modules, such as
The current character polar signal crd of fruit outside input is rd- domains, then by input data respectively according to data character transformation rule and
Control character transformation rule is transformed into rd+ domains from rd- domains, is sent to based on the 3b/4b data characters of rd+ by its outfan respectively
Decoder and the 3b/4b control character decoders based on rd+；If the current character polar signal crd of outside input is rd+,
Then directly input data is sent to into 3b/4b data characters decoder based on rd+ and based on rd+'s by its outfan respectively
3b/4b control character decoders；In the semipolar situation of change of process of data preprocessing, believed by the second change in polarity indications
Number rd_flag_4b output.
The 5b/6b data character decoders based on rd+ are to decode rule to carry out 5b/ based on the rd+ of data character
The decoder of 6b decoding operates, the operation done is：By the first data character data data_6b according to data character rd
+ decoding rule produces the first data character decoding data dout_data_6b carrying out 5b/6b decodings, and described first
Data character decoding indications signal flag_data_6b is then used for representing whether the decoding operate is successful.
The 5b/6b control character decoders based on rd+ are to decode rule to carry out 5b/ based on the rd+ of control character
The decoder of 6b decoding operates, the operation done is：By the first control character data ctl_6b according to control character rd+
Decode rule to carry out 5b/6b decodings, produce the first control character decoding data dout_ctl_6b, and described first controls
Character decoder indications signal flag_ctl_6b processed is then used for representing whether the decoding operate is successful.
The 3b/4b data character decoders based on rd+ are to decode rule to carry out 3b/ based on the rd+ of data character
The decoder of 4b decoding operates, the operation done is：By the second data character data data_4b according to data character rd
+ decode rule to carry out 3b/4b decodings, the second data character decoding data dout_data_4b output is produced, and it is described
Second data character decoding indications signal flag_data_4b is then used for representing whether the decoding operate is successful.
The 3b/4b control character decoders based on rd+ are to decode rule to carry out 3b/ based on the rd+ of control character
The decoder of 4b decoding operates, the operation done is：By the second control character data ctl_4b according to control character rd+
Decode rule to carry out 3b/4b decodings, produce the second control character decoding data dout_ctl_4b, and described second controls
Character decoder indications signal flag_ctl_4b processed is then used for representing whether the decoding operate is successful.
The data combiners block is that suitable data are selected from four groups of input datas, is merged into the data of eight bits simultaneously
Output；The operation done is：If the first data character decoding indications signal flag_data_6b and second number
All represent that respective decoding operate is successful according to Character decoder indications signal flag_data_4b, then by first data
Used as low 5, the second data character decoding data dout_data_4b is used as high by 3 for Character decoder data d0ut_data_6b
Position, is merged into the output data of 8 bit bit wides, and it is data word that indicator signal symhol represents current output
Symbol；If the first control character decoding indications signal flag_ctl_6b and second control character decoding indications
Signal flag_ctl_4b represents that respective decoding operate is successful, then by the first control character decoding data dout_
Used as low 5, the second control character decoding data dout_ctl_4b is merged into 8 bit bit wides to ctl_6b as high 3
The output data, and it is control character that indicator signal symhol represents current output.
The first XOR module is of the current character polar signal crd and 6b pretreatment module to outside input
One change in polarity indications signal rd_flag_6b does XOR, and exports the second change in polarity indications letter by outfan
Number rd_6b.
The second XOR module is second to the second change in polarity indications signal rd_6b and 4b pretreatment module
Change in polarity indications signal rd_flag_4b does XOR, and exports next character polar signal nrd by outfan.
A specific embodiment is presented herein below.
With reference to shown in accompanying drawing, when the data of outside input are 10 ' b10_1000_0011, and current character polar signal crd
For rd+ domains when, data split front 6 bit data be 6 ' b00_0011, afterwards 4 bit datas be 4 ' b1010.
In 6b pretreatment modules, front 6 bit data and current character polar signal crd are sent into after 6b pretreatment modules,
It is identical with the polarity of decoding because current character polar signal crd is rd+ domains, therefore input data is directly passed through its outfan
Output, the first data character data data_6b for obtaining and the first control character data ctl_6b are all 6 ' b00_0011, and 6b
Polarity represented by first change in polarity indications signal rd_flag_6b of pretreatment module there occurs change.
In the first XOR module, because the polarity represented by the first change in polarity indications signal rd_flag_6b occurs
Change, therefore the second change in polarity indications signal rd_6b negating for current character polar signal crd, it is rd- domains.
In 4b pretreatment modules, afterwards 4 bit datas and the second change in polarity indications signal rd_6b send into 4b pretreatment
After module, due to the second change in polarity indications signal rd_6b polarity be rd- domains, with decoding opposite polarity, therefore will input
The b1010 of data 4 ' is transformed into rd+ domains according to data character transformation rule and control character transformation rule from rd- domains respectively, and second
Data character data data_4b and the second control character data ctl_4b are all 4 ' b0101, the second of the output of 4b pretreatment modules
Polarity represented by change in polarity indications signal rd_flag_4b also there occurs change.
In the second XOR module, because the polarity represented by the second change in polarity indications signal rd_flag_4b occurs
Change, therefore next character polar signal nrd is negating for the second change in polarity indications signal rd_6b, be rd+ domains.
In the 5b/6b data character decoders based on rd+, the b00_0011 of input data 6 ' is carried out based on data character
Rd+ decode rule to carry out 5b/6b decodings after, obtain the first data character decoding data dout_data_6b for 5 ' b0, the
One data character decoding indications signal flag_data_6b is expressed as failure.
In the 5b/6b control character decoders based on rd+, the b00_0011 of input data 6 ' is carried out based on control character
Rd+ decode rule to carry out 5b/6b decodings after, the first control character decoding data dout_ctl_6b for obtaining be 5 ' b1_
1100, the first control character decoding indications signal flag_ctl_6b is expressed as successfully.
In the 3b/4b data character decoders based on rd+, the b0101 of input data 4 ' is carried out based on data character
After rd+ decodes rule to carry out 3b/4b decodings, the second data character decoding data dout_data_4b for obtaining is 3 ' b101,
Second data character decoding indications signal flag_data_4b is expressed as successfully；
In the 3b/4b control character decoders based on rd+, the b0101 of input data 4 ' is carried out based on control character
After rd+ decodes rule to carry out 3b/4b decodings, the second control character decoding data dout_ctl_4b for obtaining is 3 ' b101, the
Two control characters decoding indications signal flag_ctl_4b is expressed as successfully.
In data combiners block, when receive four groups be decoded after data after, due to the first data character decoding indicate
Symbol signal flag_data_6b is expressed as failure, and the first control character decoding indications signal flag_ctl_6b and second is controlled
Character decoder indications signal flag_ctl_4b processed is expressed as successfully, therefore output data is by the first control character decoding data
Dout_ctl_6b and the second control character decoding data dout_ctl_4b are constituted, wherein the first control character decoding data
Dout_ctl_6b does low 5, and the second control character decoding data dout_ctl_4b does high 3, and the data after merging are：8’
B1011_1100, and indicator signal symbol is expressed as control character, i.e. K28.5.
The present invention has been described in detail above by specific embodiment and embodiment, but these not constitute it is right
The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Enter, these also should be regarded as protection scope of the present invention.
Claims (8)
1. a kind of 8b/10b decoding circuits based on rd+, it is characterised in that：By 6b pretreatment modules, 4b pretreatment modules, it is based on
The 5b/6b data character decoders of rd+, based on the 5b/6b control character decoders of rd+, the 3b/4b data characters based on rd+
Decoder, based on the 3b/4b control character decoders of rd+, data combiners block and two XOR module compositions；
Outer input data is 10 bit datas, and 10 bit data is split as front 6 bit data and rear 4 bit data, described
Front 6 bit data is input to the 6b pretreatment modules, and rear 4 bit datas are input to the 4b pretreatment modules；
One current character polar signal, is separately input to the 6b pretreatment modules and the first XOR module；The current character pole
Property signal represents the polarity of current input character, and the 6b pretreatment modules are under the control of current character polar signal to described
Front 6 bit data carries out pretreatment operation, and exports the first data character data, and the first control character data and the first polarity become
Change indications signal；
First XOR module is different for carrying out to the current character polar signal and the first change in polarity indications signal
Or process and export the second character polar signal；
The second character polar signal is separately input to the 4b pretreatment modules and the second XOR module；The 4b pretreatment
Module carries out pretreatment operation under the control of the second character polar signal to rear 4 bit datas, and exports the second data
Character data, the second control character data and the second change in polarity indications signal；
The second XOR module is used to enter the second character polar signal and the second change in polarity indications signal
The process of row XOR, produces next character polar signal, and next character polar signal is externally exported；
The first data character data input to the 5b/6b data character decoders based on rd+ are processed, and are exported
First data character decoding data and the first data character decoding indications signal；
The first control character data input to the 5b/6b control character decoders based on rd+ are processed, and are exported
First control character decoding data and the first control character decoding indications signal；
The second data character data input to the 3b/4b data character decoders based on rd+ are processed, and are exported
Second data character decoding data and the second data character decoding indications signal；
The second control character data input to the 3b/4b control character decoders based on rd+ are processed, and are exported
Second control character decoding data and the second control character decoding indications signal；
The first data character decoding data, the first data character decoding indications signal, the first control character decoding data,
First control character decoding indications signal, the second data character decoding data, the second data character decoding indications signal, the
Two control character decoding datas and the second control character decode indications signal input to the data combiners block, are processed
And export the output data and an indicator signal of one 8 bits.
2. decoding circuit as claimed in claim 1, it is characterised in that：The 6b pretreatment modules are by front 6 bit data
Changing into can carry out the data that rd+ decodes computing, if the current character polar signal of outside input is rd-, by institute
State front 6 bit data and be transformed into rd+ domains from rd- domains according to data character transformation rule and control character transformation rule respectively, and
The the first data character data produced after conversion, the first control character data are sent to respectively based on the 5b/6b data characters of rd+
Decoder and the 5b/6b control character decoders based on rd+；If the current character polar signal of outside input is rd+,
Then front 6 bit data directly produces the first data character data, the first control character data, and is sent to respectively based on rd+
5b/6b data characters decoder and the 5b/6b control character decoders based on rd+；Occur in process of data preprocessing
Change in polarity situation, by the first change in polarity indications signal output.
3. decoding circuit as claimed in claim 1, it is characterised in that：The 4b pretreatment modules will rear 4 bit datas
Changing into can carry out the data that rd+ decodes computing, if the second character polar signal is rd-, will rear 4 bit numbers
According to according to data character transformation rule and control character transformation rule being transformed into rd+ domains from rd- domains respectively, and will produce after conversion
The second data character data, the second control character data are sent to respectively the 3b/4b data characters decoder based on rd+ and are based on
The 3b/4b control character decoders of rd+；If the second character polar signal is rd+, rear 4 bit datas are direct
The second data character data, the second control character data are produced, and is sent to respectively based on the 3b/4b data character decoders of rd+
With the 3b/4b control character decoders based on rd+；The change in polarity situation occurred in process of data preprocessing, by second
Change in polarity indications signal output.
4. decoding circuit as claimed in claim 1, it is characterised in that：The 5b/6b data character decoders based on rd+ are
The decoder of 5b/6b decoding operates is carried out based on the rd+ decodings rule of data character, the operation done is：By described first
Data character data carry out 5b/6b decodings according to the rd+ decoding rules of data character, produce the first data character decoding
Data, and first data character decoding indications signal is then used for representing whether the decoding operate is successful.
5. decoding circuit as claimed in claim 1, it is characterised in that：The 5b/6b control character decoders based on rd+ are
The decoder of 5b/6b decoding operates is carried out based on the rd+ decodings rule of control character, the operation done is：By described first
Control character data carry out 5b/6b decodings according to the rd+ decoding rules of control character, produce the first control character decoding
Data, and first control character decoding indications signal is then used for representing whether the decoding operate is successful.
6. decoding circuit as claimed in claim 1, it is characterised in that：The 3b/4b data character decoders based on rd+ are
The decoder of 3b/4b decoding operates is carried out based on the rd+ decodings rule of data character, the operation done is：By described second
Data character data carry out 3b/4b decodings according to the rd+ decoding rules of data character, produce the second data character decoding
Data, and second data character decoding indications signal is then used for representing whether the decoding operate is successful.
7. decoding circuit as claimed in claim 1, it is characterised in that：The 3b/4b control character decoders based on rd+ are
The decoder of 3b/4b decoding operates is carried out based on the rd+ decodings rule of control character, the operation done is：By described second
Control character data carry out 3b/4b decodings according to the rd+ decoding rules of control character, produce the second control character decoding
Data, and second control character decoding indications signal is then used for representing whether the decoding operate is successful.
8. decoding circuit as claimed in claim 1, it is characterised in that：The data combiners block is from four groups of input datas
Suitable data are selected, the data of 8 bits is merged into and is exported；The operation done is：If the first data character decoding
Indications signal and second data character decoding indications signal all represent that respective decoding operate is successful, then by institute
The first data character decoding data is stated as low 5, the second data character decoding data is merged into 8 bits as high 3
The output data of bit wide, and it is data character that the indicator signal represents current output；If first control
Character decoder indications signal and second control character decoding indications signal all represent that respective decoding operate is successfully
, then using the first control character decoding data as low 5, the second control character decoding data is closed as high 3
And into the output data of 8 bit bit wides, and it is control character that the indicator signal represents current output.
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|---|---|---|---|---|
| US4665517A (en) * | 1983-12-30 | 1987-05-12 | International Business Machines Corporation | Method of coding to minimize delay at a communication node |
| CN101674089A (en) * | 2009-10-19 | 2010-03-17 | 中国科学院声学研究所 | High-speed 8B/10B coder, decoder and processing method thereof for error input |
| CN101764617A (en) * | 2009-12-22 | 2010-06-30 | 清华大学 | Encoding method of 9B/10B code |
| CN102487307A (en) * | 2010-12-06 | 2012-06-06 | 中国航空工业集团公司第六三一研究所 | EOF (end of file) polarity selection method used for FC (fiber channel) protocol |
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2012
- 2012-01-06 CN CN201210004088.5A patent/CN103199869B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4665517A (en) * | 1983-12-30 | 1987-05-12 | International Business Machines Corporation | Method of coding to minimize delay at a communication node |
| CN101674089A (en) * | 2009-10-19 | 2010-03-17 | 中国科学院声学研究所 | High-speed 8B/10B coder, decoder and processing method thereof for error input |
| CN101764617A (en) * | 2009-12-22 | 2010-06-30 | 清华大学 | Encoding method of 9B/10B code |
| CN102487307A (en) * | 2010-12-06 | 2012-06-06 | 中国航空工业集团公司第六三一研究所 | EOF (end of file) polarity selection method used for FC (fiber channel) protocol |
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