CN101674089A - High-speed 8B/10B coder, decoder and processing method thereof for error input - Google Patents
High-speed 8B/10B coder, decoder and processing method thereof for error input Download PDFInfo
- Publication number
- CN101674089A CN101674089A CN 200910236064 CN200910236064A CN101674089A CN 101674089 A CN101674089 A CN 101674089A CN 200910236064 CN200910236064 CN 200910236064 CN 200910236064 A CN200910236064 A CN 200910236064A CN 101674089 A CN101674089 A CN 101674089A
- Authority
- CN
- China
- Prior art keywords
- module
- code word
- input
- character
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a high-speed 8B/10B coder, a decoder and a processing method thereof for error input. The coder comprises a data character precoding module, a RD calculating module and a data character precoding correction module, and the coder adopts a pipeline structure and a parallel processing method; the data character precoding module, the data character precoding correction module and the RD calculating module are respectively precoded and then post collected; the data character precoding module precodes input data in first-stage flow water, and calculates whether the current input code word can cause RD to turn by a RD_turn module; the RD calculating module calculates a RD value passing through the code word in second-stage flow water, and calculates the obtained RD value byusing the former clock period to correct the precoded result of the current code word. The invention respectively adopts the pipeline structure and the parallel processing method when being applied in a high-speed serial interface, thus simplifying the circuit design, shortening the key path and improving speed.
Description
Technical field
The present invention relates to the transfer encoding technical field of digital communication, particularly a kind of high speed 8B/10B encoder and to the processing method of mistake input, (＞1Gbps) 8B/10B encoder and logic realization method thereof promptly at a high speed.
Background technology
The 8B/10B transfer encoding is to be to propose in 4486739 the United States Patent (USP) " Byte Oriented DC Balanced (0,4) 8B/10B Partition BlockTransmission Code " at publication number by Albert X.Widmer and Peter A.Franaszek nineteen eighty-three.This transfer encoding transmission bandwidth is little, transition density is high, characteristics such as edge transition are arranged repeatedly in the code word run length, each code word, thereby is easy to alignment synchronously fast, dc balance.Dc balance is meant that " 0 " and " 1 " quantity of coding back data is consistent substantially, can avoid the input of receiver that dc shift is arranged, and the driving to AC coupled load, long cable and optical-electric module becomes possibility like this.So the dc balance technology is widely used in the high-speed serial bus.
Along with more and more higher, the speed of the Code And Decode of 8B/10B also there has been higher requirement to the requirement of serial line interface volume of transmitted data and speed.Publication number is that the patent " based on the 16B/20B encoder logic implementation method of two 8B/10B encoders " of CN1300971C and United States Patent (USP) " 8B/10BEncoder System And Method " that publication number is 6295010B1 all are to come raising speed by a plurality of encoder of Parallel Implementation, can increase area of chip like this.Publication number is that 6977599 United States Patent (USP) " 8B/10B Encoding AndDecoding for High Speed Applications " and publication number are that 6911921 United States Patent (USP) " 5B/6B-T; 3B/4B-T and Partitioned 8B/10B-T and 10B/12B Transmission Codes; and TheirImplementation for High Operating Rates " then is by improving the speed that circuit structure improves single 8B/10B encoder, but it mainly adopts combinational logic to realize Code And Decode, has very dark logical depth, cause critical path oversize, thereby influenced the speed of 8B/10B encoder to a certain extent, and all paid attention in the implementation of 8B/10B encoder the coding of data character and DC Balance Control and ignored control character and the DC equilibrium problem of data character data flow when transmitting at interval.
Summary of the invention
The objective of the invention is to, overcome the problems referred to above that the 8B/10B encoder exists in the prior art, thus the processing method that a kind of high speed 8B/10B encoder is provided and mistake is imported, to adapt to the demand of high-speed interconnect.
In order to solve the problems of the technologies described above, the invention provides a kind of 8B/10B encoder based on pipeline organization and parallel processing technique.At first, during this 8B/10B encoder transfer encoding, coding module and RD (run disparity) computing module are separated, in first order flowing water, the input data are carried out precoding, and calculate current enter code word and whether can cause RD to overturn, in the streamline of the second level, calculate, and the RD value of utilizing a clock cycle to calculate gained comes the precoding result of current code word is revised through the RD value after the current code word; Then, when this 8B/10B encoder is encoded to 8B/10B, do not need to judge earlier that the input data are control character or data character, but simultaneously it is encoded according to the coding rule of data character and control character respectively, the control character flag bit K according to input selects output to two kinds of codings again.Thereby, when input is control character, also can guarantee the dc balance of the data character coding of itself and front and back, then only it is carried out the data character coding in the implementation method of present 8B/10B encoder, do not consider simultaneously problem to the control character coding; At last, during this 8B/10B decoder is decoded to 8B/10B, be divided into decoding, error detection (the unbalanced detection and the code word error detection that comprise code stream) and character types are judged (data character or control character) several sections, in the first order streamline 10 bits input data are carried out 6B/5B decoding and 4B/3B decoding, and the lack of uniformity of calculating 6B and 4B data, carry out the code word error detection in the streamline of the second level, character types are judged and RD calculates and lack of uniformity is judged and decoded result is selected, and in the implementation method of present 8B/10B decoder, only detected the lack of uniformity mistake of code stream, and ignored judgement to the code word type, and the vicious situation of enter code word, just in some open papers, mention error character is sorted out, then with the method for independent combinational logic realization the differentiation of wrong numeral.The present invention adopts in respectively to 6B and 4B codeword decoding 6B sign indicating number and the 4B sign indicating number to this input to put the error flag position, then the decision logic 10B code word code word mistake whether of judging input by simple combinational logic again according to the value of its error flag position.
Specifically, in order to solve the problems of the technologies described above, the invention provides a kind of high speed 8B/10B encoder, comprise: data character precoding module 10a, RD computing module 20a, 20b and data character precoding correcting module 30a is characterized in that: this high speed 8B/10B encoder adopts pipeline organization and method for parallel processing;
Described data character precoding module 10a and data character precoding correcting module 30a, RD computing module 20b carry out precoding respectively and the back is revised, whether described data character precoding module 10a carries out precoding to the input data in first order flowing water, and calculate current enter code word by RD_turn module 20a and can cause RD to overturn; Described RD computing module 20b calculates in the streamline of the second level through the RD value after the current code word, and the RD value of utilizing a clock cycle to calculate gained comes the precoding result of current code word is revised;
Described data character precoding module 10a is connected to data character precoding correcting module 30a and output by the one-level register; Described RD_turn module 20a is connected to RD computing module 20b and output by the one-level register; Described RD computing module 20b is connected to data character precoding correcting module 30a and control character precoding correcting module 30b and RD computing module 20b by the one-level register.
A kind of improvement as technique scheme, described encoder is encoded simultaneously according to the coding rule of data character and control character respectively, and described encoder also comprises control character precoding module 10b, control character coding correcting module 30b and data/control character selection module 40; Described data character coding correcting module 30a is connected data/control character with control character coding correcting module 30b and selects module 40, and described data/control character selects module 40 according to the control character flag bit K that imports two kinds of codings to be selected output.
When this 8B/10B encoder carries out the 8B/10B coding, do not need to judge earlier that the input data are control character or data character, but simultaneously it is encoded according to the coding rule of data character and control character respectively, control character flag bit K according to input selects output to two kinds of codings again, thereby, when input is control character, also can guarantee the dc balance of the data character coding of itself and front and back.
As another improvement of technique scheme, during precoding, give tacit consent to current RD value for negative, described data character precoding module 10a carries out 5B/6B coding and 3B/4B coding with it as data character; Described control character precoding module 10b encodes as control character it to it, and calculates the change information through RD after the current code word.
As another improvement of technique scheme, described data character coding correcting module 30a and control character coding correcting module 30b are used for controlling according to the RD value that last one-period calculates gained and deposits register in the back correction of coding.
In order to solve the problems of the technologies described above, the present invention also provides a kind of high speed 8B/10B decoder, comprise data decode module 50, lack of uniformity flag bit computing module 60 and lack of uniformity calculating and unbalanced error detect circuit module 80, it is characterized in that: this high speed 8B/10B decoder adopts the structure of streamline and parallel processing, can decode and detect the unbalanced mistake of code stream simultaneously; Described data decode module 50 and lack of uniformity flag bit computing module 60, lack of uniformity calculate and unbalanced error detect circuit module 80 is used for respectively enter code word is decoded and unbalanced error detection;
Described data decode module 50 is decoded to enter code word in first order streamline, if be input as the efficient coding code word, it is decoded according to coding rule, if be input as the invalid code code word, then it is decoded as a fixing error flag code word, and obtains being used for lack of uniformity calculating and the needed flag bit of unbalanced error detect circuit 80 calculating by flag bit computing modules 60 such as lacks of uniformity;
Described lack of uniformity is calculated and unbalanced error detect circuit module 80 carries out in the streamline of the second level that lack of uniformity is judged and the RD calculating of current code word, and utilizes the RD value of a clock cycle calculating gained to come whether current code word unbalanced mistake is taken place and judge;
The input data are connected to described data decode module 50 and lack of uniformity flag bit computing module 60 by first order register, in first order streamline, 10 bits input data are carried out 6B/5B decoding and 4B/3B decoding, and the lack of uniformity of calculating 6B and 4B data, the output of described lack of uniformity flag bit computing module 60 is connected to lack of uniformity by second level register and calculates and unbalanced error detect circuit module 80, and the value of RD is re-used as the input of self by third level register.
As a kind of improvement of technique scheme, described 8B/10B decoder also comprises code word error detection and character types judge module 70 and dateout selection module 90;
In the 8B/10B coding rule, the efficient coding of data character has 440 kinds of combinations, and the efficient coding of control character has 24 kinds of combinations, be 464 kinds of combinations of efficient coding result, the 10B code word then has 210 kinds of combinations, and totally 1024 kinds of combinations promptly have 560 kinds of invalid code code word as a result;
Described code word error detection and character types judge module 70, whether the enter code word that is used to detect encoder is invalid code code word as a result, carry out the code word error detection, and be used to judge that enter code word is data character or control character before encoding, carry out the code word type and judge;
Described dateout is selected module, is used for according to the unbalanced error flag of the output position of lack of uniformity calculating and unbalanced error detect circuit module 80 code word or the fixing error flag code word of decoding being selected output;
Described code word error detection and character types judge module 70 carry out the code word error detection in the streamline of the second level, 6B sign indicating number and 4B sign indicating number to this input in respectively to 6B and 4B codeword decoding are put the error flag position, then the decision logic 10B code word code word mistake whether of judging input by simple combinational logic again according to the value of its error flag position.
In the implementation method of described 8B/10B decoder, not only detected the lack of uniformity mistake of code stream, but also the code word type has been judged, and the vicious situation of identification enter code word; During the decoding of described 8B/10B decoder, described lack of uniformity judgement and RD computing module can not only detect the lack of uniformity mistake of code stream, but also the code word type is judged, and the vicious situation of identification enter code word, but the RD of current code word calculates only relevant with the input of current code word, and is irrelevant with the RD of a last code word, do not influence the RD calculating of back code word and the unbalanced detection of back code word, embodied wrong indiffusion function.This function is that present 8B/10B decoder is unexistent.
As another improvement of technique scheme, described data decode module 50,6 flag bits that are used to produce; Described code word error detection and character types judge module 70 are judged code word mistake and code word type by these flag bits;
Described 6 flag bits comprise: code_err4 represents that the 4B code word of importing makes a mistake; Code_err6 represents that the 6B code word of importing makes a mistake; The p_28 mark represents that the code word of importing is " 001111 " or " 110000 "; The p1 mark represents that the 6B code word of importing is " 111010 " or " 000101 " or " 110110 " or " 001001 " or " 101110 " or " 010001 " or " 011110 " or " 100001 "; The p2 mark represents that the 4B code word of importing is " 1000 " or " 0001 ";
If code_err (code_err=code_err6|code_err4) is 1, then judge the code word mistake;
If K is (K=p_28| (p1﹠amp; P2)), be 1, then former code word is a control character; Be 0, then former code word is a data character.
A kind of preferred as technique scheme, described lack of uniformity calculate and unbalanced error detect circuit 80 in, signal E_Dx3 and p4 as or the input of door OR1, its output is imported as the selection signal of the MUX MUX1 of alternative; The input of E_D7 and p6 conduct or door OR2, its output is as the selection signal input of the MUX MUX2 of alternative; Disp6 and RD are as the two paths of signals input of the MUX MUX2 and the XOR gate XOR2 of alternative; The output signal rd of alternative MUX MUX2 and disp4 signal are as two signal inputs of XOR gate XOR1; The output signal rd of alternative MUX MUX2 and disp4 are as the two paths of signals input of alternative MUX MUX1; P4 and p6 signal are imported as the signal of inverter N1 and inverter N2 respectively; The output signal of alternative MUX MUX1 is as the D signal input part of d type flip flop D1, and its output Q end is the signal input of alternative MUX MUX2 and XOR gate XOR2 as the RD signal; The clk termination clock signal of d type flip flop D1; The output conduct of inverter N1 and XOR gate XOR1 and two input signals of door AND1; The output conduct of XOR gate XOR2 and inverter N2 and two input signals of door AND2; With door AND1 and with the output signal of door AND2 as or the input signal of door OR3, it is output as the RD_err signal.
Preferred as another of technique scheme, the flag bit that described lack of uniformity flag bit computing module 60 is produced comprises:
The E_D7 flag bit is represented to import the 6B code word and is " 000111 " or " 111000 ";
The E_Dx3 flag bit is represented to import the 4B code word and is " 0011 " " 1100 ";
Whether the number of " 0 " and " 1 " of p4 sign note bit representation input 4B code word equates that equal then p4 is 1, otherwise is 0;
Whether the number that the p6 marker bit represents to import " 0 " and " 1 " of 6B code word equates that equal then p6 is 1, otherwise is 0;
Disp4 is the quantity of the quantity of " 1 " in the 1 flag bit expressive notation input 4B code stream greater than " 0 ", is the quantity of the quantity of " 0 " in 0 expression 4B code stream greater than " 1 ";
Disp6 is the quantity of the quantity of " 1 " in the 1 flag bit expressive notation input 6B code stream greater than " 0 ", is the quantity of the quantity of " 0 " in 0 expression 6B code stream greater than " 1 "; But, when input 6B code word is " 111000 " or " 000111 ", put p6=0, wherein the former puts disp6=1, and the latter puts disp6=0; When input 4B code word is " 1100 " or " 0011 ", put p4=0, wherein the former puts disp4=1, and the latter puts disp4=0.
In order to solve the problems of the technologies described above, it is a kind of based on the processing method of high speed 8B/10B encoder to the Code And Decode of mistake input that the present invention also provides, and this method may further comprise the steps:
(1) when the type code position of enter code word K is 1, and enter code word is not when being 12 control characters stipulating in the 8B/10B coding rule, the input signal that encoder is described is wrong, this moment, data character precoding module 10a encoded its unification according to the 10B sign indicating number of a direct current equilibrium, and through passing to control character coding correcting module 30b behind the one-level register, select module 40 through passing to data/control character after revising, and finally select coding result output by the K signal.
When (2) input signal of decoder was wrong, if this yard do not belong to the coding result scope of 8B/10B coding schedule, then data decode module 50 was decoded its unification according to a specific character; If this yard is unbalanced with the direct current of a last sign indicating number, then dateout selects the unbalanced error flag position that module 90 is calculated according to lack of uniformity and unbalanced error detect circuit module 80 produces to select a specific character as output.
Regular coding when adopting dc balance code word of the present invention as the encoder input error, and the fixedly decoding during as the decoder input error with the corresponding true form of the fixed codeword of this dc balance are so that the enter code word of upper-layer protocol identification error.
The present invention has stipulated that the coding " 0011110010 " of K28.4 or " 1100001101 " (low level in a preceding high position in the back) are the error flag of encoder; The source code of K28.4 " 10011100 " (high-order preceding low level back) is the error flag sign indicating number of decoder.During the 8B/10B coding, be that 1 explanation input is a control character if control character flag bit K occurs, but enter code word is not when being 12 control characters in the coding rule, illustrates that then input code makes mistakes, just be fixed this moment encodes according to K28.4; During the 8B/10B decoding, if input code detects mistake, then be fixed and be decoded as K28.4, so just can guarantee to have the dc balance of the transmission code stream of staggering the time when the encoder input code, and can make coder-decoder simple in structure, also be convenient to upper-layer protocol identification and handle the mistake of enter code word, and the code word that is used for error identification being not limited to K28.4, can also be other code words that possess non-data characters coding of direct current equilibrium.Innovation part of the present invention is to come coding and decoding enter code word mistake with a balanced code word of fixing direct current, and this is that existing 8B/10B encoder does not have.
The present invention adopts streamline and technology parallel processing, and Code And Decode was finished in two cycles, has improved the speed of encoder; Adopt the RD value after first cycle is carried out current code word precoding and calculating process current code word in the cataloged procedure, RD result after the last code word of process that second period obtains according to last one-period again revises precoding, and calculates the RD of next cycle.Shorten critical path, accelerated the speed of encoder; In the decode procedure, in the unbalanced testing process of code stream the time, run into the code word of unbalanced mistake after, with wrong code word Unified coding, give upper-layer protocol and handle, transmission just need not be interrupted like this, and the RD of correct calculation subsequent codewords, realized wrong indiffusible function.
The invention has the advantages that encoder of the present invention is applied in the HSSI High-Speed Serial Interface, all adopt pipeline organization and method for parallel processing, thereby simplified circuit design, shortened critical path, and improved speed.
Encoder among the present invention, the method that adopts precoding and back to revise is raised the efficiency, avoided the process that just can encode after obtaining current RD value, and input character is used as data character and control character is encoded simultaneously, last according to the K signal of input two kinds of codings are selected output again, can guarantee that like this output code flow accomplishes the direct current equilibrium fully; Decoder among the present invention has adopted particular electrical circuit, energy error detecting code character error and unbalanced mistake, thus realize wrong indiffusion; Regular coding when adopting the dc balance code word as the encoder input error, and the fixedly decoding during as the decoder input error with the corresponding true form of the fixed codeword of this dc balance are so that the enter code word of upper-layer protocol identification error.In a word, the present invention is simpler, saves logical resource, helps to reduce chip area, and the present invention also has correct code word is carried out the function that the code word type is judged output, and this also is the existing not available function of 8B/10B decoder.Code word error-detecting method among the present invention also is different from the method that existing open paper proposes.In addition, the present invention has also gone out its character types to the correct codeword decoding of input.
Description of drawings
Fig. 1 is existing 8B/10B coding and decoding signal flow graph;
Fig. 2 is a 8B/10B coding and decoding signal flow graph of the present invention;
Fig. 3 is the structured flowchart of the exemplary coder that adopts the 8B/10B transfer encoding and encode;
Fig. 4 is the signal flow graph of the exemplary coder that adopts the 8B/10B transfer encoding and encode;
Fig. 5 is the structured flowchart of the exemplary decoder that adopts the 8B/10B transfer encoding and decode;
Fig. 6 is the signal flow graph of the exemplary decoder that adopts the 8B/10B transfer encoding and decode;
Fig. 7 is the state transition graph that is used to judge the RD state;
Fig. 8 is the circuit diagram of unbalanced calculating and detection module in the decoder.
Embodiment
The present invention will be further described below in conjunction with the drawings and specific embodiments.
8B/10B encoder as shown in Figure 3 comprises the two-stage streamline, and wherein first order streamline comprises the RD_turn computing module of data character precoding module, control character precoding module, data and control character; Second level streamline comprises: data character precoding correcting module, control character coding correcting module, RD computing module, data/control character are selected module.Described data character precoding module and data character precoding correcting module carry out precoding and the correction of 5B/6B and 3B/4B respectively to the data character.The eight bit data HGFEDCBA of input sends in three modules of first order streamline through register, and a control character Kin of input is sent to RD computing module in the streamline of the second level by the two-stage register; The result of calculation of data and control character RD_turn computing module is sent to RD computing module in the streamline of the second level by register, and the result of calculation RD_m of RD computing module outputs to register; The coding result of data character precoding module is connected to data character precoding correcting module by register, the coding result of control character precoding module is sent to control character precoding correcting module by register, sends into again in RD computing module and data character and the control character precoding correcting module through the RD_m signal of register; Guide data character and control character are revised precoding, and data character and the revised result of control character precoding select output through a selector by the K signal.
Described cataloged procedure has been introduced parameters R D (running disparity) and has been represented degree of unbalance.Wherein RD+ represent " 1 " in the code word number more than the number that equals " 0 ", unnecessary the equal'sing of number " 1 " the number of " 0 " in the last code word of " RD-" expression.RD by a last code word selects the 10bit code word of current code word correspondence as output.Encode for data character, the 8bit data are divided into low 5 and high 3, respectively it is carried out 5B/6B coding and 3B/4B coding, that the 5B/6B coding is selected is the RD that a last byte code produces, and is the encode rd of generation of the adjacent 5B/6B in front and the 3B/4B coding is selected.The RD value that whole byte code produced is obtained by the 3B/4B coding.Listed as following table 1,2 and 3:
Table 1
Table 2
Table 3
According to the code word identical or step-by-step negate of RD+, sign indicating number is divided into neutral sign indicating number and polar code with the RD-coding.Wherein neutral sign indicating number is meant that the coding result of this yard has only a kind of possible result, and the number of " 0 " equals the number of " 1 " in this coding; Polar code is meant the difference according to RD, and coding has two kinds of different possible outcomes.
Code device signal flow graph as shown in Figure 4, in order to accelerate encoder speed, do not judge that earlier the input data are control character or data character, parallel to the input data according to control character and data character encode simultaneously, the calculating of RD, according to the Kin signal it is selected output more at last.First order module is carried out precoding to enter code word, is divided into 5B/6B precoding, 3B/4B precoding and the control character precoding of data character.During precoding all the situation according to RD-enter code word is encoded, (what be used for respectively indicating 5B/6B coding and 3B/4B coding as p_56 and p_34 is neutral yard or polar code to obtain code word pre_abcdei, pre_fghj, c_pre_abcdeifghj and some flag bits in the middle of a group; Whether rd_turn_56 is used for indicating through the rd behind the 5B/6B coding opposite with input RD, and 1 expression is opposite, and 0 expression is identical).Calculate respectively in the time of precoding through the RD after the current code word and whether want negate with respect to the RD of a last code word.In like manner need simultaneously input character to be calculated RD_turn respectively as control character and data character.In the module of the second level,, middle code word is revised according to the RD of a last code word.Data character precoding correcting module is divided into the correction of 5B/6B coding and the 3B/4B coding is revised.In 5B/6B coding correcting module, input RD and p_56 are control bits, if RD﹠amp; P_56=1, then exporting 6bit sign indicating number abcdei is middle code word step-by-step negate., otherwise output equals middle code word.In the 3B/4B coding correcting module, if code word is not equal to 1110 in the middle of the 4bit, rd and p_34 are as control bit, if rd﹠amp; P_34=1, then exporting 4bit sign indicating number fghj is code word step-by-step negate in the middle of the 4bit, otherwise output equals middle code word; If code word is 1110 in the middle of the 4bit, this moment, 5B/6B coding revised output e, i and rd, p_34 were as control bit, if rd﹠amp; E﹠amp; I=1 then exports fghj=1000, if rd﹠amp; E﹠amp; I=1 then exports fghj=0111, otherwise if rd﹠amp; P_34=1, fghj=0001 then, fghj=1110 under all the other situations.In the control character precoding correction, RD is a control bit, if RD=1 then is output as the middle code word step-by-step of 10bit negate, otherwise output equals middle code word.By Kin revised control character coding and data character coding are selected as output, and selected overturn flag bit or control character upset flag bit of data character carried out XOR as final RD_turn with the RD value of the last one-period of process register and obtain new RD value.
8B/10B decoder as shown in Figure 5 also comprises two-stage flowing water, and wherein first order streamline comprises input data decode module, the 6B of input data and the lack of uniformity computing module of 4B sign indicating number; Second level streamline comprises code word error detection and character types judge module, unbalanced calculating and detection module and dateout selection module.
Described input data decode module is divided into 6B/5B decoding and 4B/3B decoding, and decoded results is sent into code word error detection and the character types judge module and the dateout selection module of second level flowing water through register; The result of calculation of the 6B of input data and the lack of uniformity computing module of 4B sign indicating number is sent into unbalanced calculating and unbalanced error detection module through register, unbalanced calculating of process and its output of unbalanced error detection are as the input of dateout selection module, and this signal is through the input of conduct oneself again after register.8B/10B decoder signal flow graph shown in Figure 6, in input data decode module, if 6B and 4B are input as the valid data behind the coding in table 1, the table 2, then it is decoded as 5B and 3B according to data in the table, when input 6B sign indicating number is 001111 or 110000, it is decoded as 11100, is input as misdata, put code_err6 or code_err4 respectively and be 1 and be used for mark 6B sign indicating number or 4B sign indicating number mistake otherwise look; If one of them is wrong for 6B or 4B data, then whole data are idle character, i.e. code_err=code_err6|code_err4.
By table 3 can shown in the coding of the spcial character seen two characteristics are arranged: the first, the coding of eight spcial characters of K28.x, wherein abcdei is 001111 or 110000, and this being coded in definitely is impossible in the digital coding; 2.; The second, to select to completely contradict to the 4B sign indicating number selection of " 7 " with the data character coding in the kx.7 coding, 1000 or 0111 coding appears in the fghj in spcial character, and can employing 0001 or 1110 in digital coding under the kindred circumstances.Thereby p_28 is set,, p1 and p2 be used for sign and judge whether input is 12 effective control codes., when abcdei was 001111 or 110000, putting p_28 was 1; When abcdei can be decoded as D23,27,29,30 o'clock, putting p1 was 1, when fghj is 1000 or 0111, was 1 with p2 set; P_28, p1, p2 are 0 under all the other situations; As p_28| (p1﹠amp; P2)=1 o'clock, the input data are control data just, put K=1.6 flag bits of unbalanced degree computing module output of 6B sign indicating number and 4B sign indicating number, wherein, p6,, p4 is respectively the polarity mark position of 6B sign indicating number and 4B sign indicating number, if the number of " 1 " and " 0 " equates in this code word, putting it is 1, represents that this sign indicating number is neutral sign indicating number; Otherwise be changed to 0, represent that this sign indicating number is polar code.When code word was neutrality, corresponding disparity flag bit disp was just effective.When the number of " 1 " was more than the number of " 0 " in the code stream, disp was 1; Otherwise, then be 0.
Similarly should be encoded to 111000 in order preventing, and error coded to be at 000111 o'clock, to detect the situation of the code error of not coming out, must to abcdei be 000111 and 111000 and fghj be 1100 and did special processing at 0011 o'clock.Though their " 0 " and " 1 " number equate, its corresponding p=0 must be set.When being input as 000111 or 0011, put disp6 and disp4 is 0; When being input as 111000 or 1100, put disp6 and disp4 is 1.So just can detect the unbalanced mistake of such yard, but since force mark these four neutral sign indicating numbers be polar code, and changed corresponding disp sign, this can cause the RD computing module to make a mistake, because these four code books are neutral sign indicating number, RD when the RD of data should keep importing afterwards through them, but become disp6 and disp4 this moment.In order to prevent this wrong the generation, also being provided with two flag bits is E_D7 and E_Dx3.When input abcdei was 000111 or 111000, E_D7 was changed to 1, otherwise it is 0; When input fghj was 0011 or 1100, E_Dx.3 was changed to 1, otherwise it is 0.
Unbalanced calculating and detection module in the decoder shown in Figure 8, wherein unbalanced calculating section as shown in Figure 7, the polarity that presents after the coded data of positive polarity and negative polarity is transmitted in the transfer of data just is the coded data polarity of self, and the data polarity after the neutral coded data transmission is then inherited the polarity of data.In 8B/10B decoder shown in Figure 5, if P6 or E_D7 are 1, data abcdei is neutral sign indicating number; If P4 or E_Dx3 are 1 o'clock, data fghj is neutral sign indicating number.So with they or as selecting signal.In the unbalanced test section, equate with disp6, illustrate that then the unbalanced mistake of DC has taken place for the abcdei of current data and the fghj of last data as if RD; If rd equates with disp4, illustrate that then the balanced mistake of DC has taken place for the abcdei of current data and current data fghj, promptly
Be 1 and detected the unbalanced mistake of DC, but because when p=1, the disp invalidating signal, thereby
With
Have only just effective when p4=0 and p6=0 respectively.
This module has wrong indiffusion function.Owing to when n+1 sign indicating number carried out the unbalanced detection of DC, need use the RDn+1 that n input code calculates.If n sign indicating number is wrong, then the RDn+1 that is obtained by it also is wrong, this moment is if n+1 input code is a correct non-neutral sign indicating number, then owing to used wrong RDn+1, decoder can mistake this correct sign indicating number is detected be the unbalanced error code of DC, its decoding is output as 10011100, but while RDn+2 equals the RD of n+1 sign indicating number, then is correct.Thereby utilize RDn+2 when detecting, just can not make a mistake again to n+3 sign indicating number; If n+1 input code is correct neutral sign indicating number, and because this moment p4, p6 are 0, decoder can not be detected. as wrong sign indicating number, thereby can export correct decoded result, but wrong RDn+1 can propagate along with the neutral sign indicating number of input, up to running into a non-neutral sign indicating number, just can be corrected to the RD of this non-neutral sign indicating number, thereby obtain correct RD, code stream decoding device afterwards will be correct detects and decodes it.
In a word, when in the input code flow when wrong, decoder can detect it, but may cause decoder that a correct sign indicating number of back is judged as error code simultaneously.But the code stream of detection that decoder can both be correct and decoding back after this.Because the probability that makes a mistake of link is very little, and this minor issue fully can be by the identification of the agreement on upper strata, and corrected by software, thereby this minor issue is very little to the whole system Effect on Performance.But if will on hardware, correct this minor issue, then need much more very logics the misdeem type of error code and the reason that leads to errors, thereby obtain correct sign indicating number, correct RD, can make pipeline stall like this, greatly reduce transmission rate, so think that this there is no need.
Dateout is selected in the module, has just considered idle character during owing to decoding, and simultaneously the idle character of importing has been decoded as K28.4, thereby exported when selecting and only need consider that the situation that the unbalanced mistake of direct current takes place gets final product.If RD_err is 1, then put and be output as K28.4, otherwise, be output as decoded output.
The present invention comprehensively is achieved under the process conditions of SIMC 90nm through DC, and this encoder all can be carried out work in the 900MHZ frequency under various PVT conditions, and area is about 1500um
2The present invention can be applicable in the design of encoder of the above HSSI High-Speed Serial Interface of 5Gbps, has application scenarios widely.
It should be noted last that above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention is had been described in detail with reference to embodiment, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1, a kind of high speed 8B/10B encoder, comprise: data character precoding module (10a), RD computing module (20a, 20b) with data character precoding correcting module (30a), it is characterized in that: this high speed 8B/10B encoder adopts pipeline organization and method for parallel processing;
Described data character precoding module (10a) and data character precoding correcting module (30a), RD computing module (20b) carry out precoding respectively and the back is revised, whether described data character precoding module (10a) is carried out precoding to the input data in first order flowing water, and can cause RD to overturn by the current enter code word of RD_turn module (20a) calculating; Described RD computing module (20b) calculates in the streamline of the second level through the RD value after the current code word, and the RD value of utilizing a clock cycle to calculate gained comes the precoding result of current code word is revised;
Described data character precoding module (10a) is connected to data character precoding correcting module (30a) and output by the one-level register; Described RD_turn module (20a) is connected to RD computing module (20b) and output by the one-level register; Described RD computing module (20b) is connected to data character precoding correcting module (30a) and control character precoding correcting module (30b) and RD computing module (20b) by the one-level register.
2, high speed 8B/10B encoder according to claim 1, it is characterized in that: described encoder is encoded simultaneously according to the coding rule of data character and control character respectively, and described encoder also comprises control character precoding module (10b), control character coding correcting module (30b) and data/control character selection module (40); Described data character coding correcting module (30a) is connected data/control character with control character coding correcting module (30b) and selects module (40), and described data/control character selects module (40) according to the control character flag bit K that imports two kinds of codings to be selected output.
3, high speed 8B/10B encoder according to claim 2 is characterized in that: during precoding, give tacit consent to current RD value for negative, described data character precoding module (10a) is carried out 5B/6B coding and 3B/4B coding with it as data character; Described control character precoding module (10b) is encoded as control character it to it, and calculates the change information through RD after the current code word.
4, high speed 8B/10B encoder according to claim 2, it is characterized in that: described data character coding correcting module (30a) and control character coding correcting module (30b) are used for controlling according to last one-period calculating gained and the RD value that deposits register in the back correction of coding.
5, a kind of high speed 8B/10B decoder, comprise data decode module (50), lack of uniformity flag bit computing module (60) and lack of uniformity calculating and unbalanced error detect circuit module (80), it is characterized in that: this high speed 8B/10B decoder adopts the structure of streamline and parallel processing, can decode and detect the unbalanced mistake of code stream simultaneously; Described data decode module (50) and lack of uniformity flag bit computing module (60), lack of uniformity are calculated and unbalanced error detect circuit module (80) is used for respectively enter code word is decoded and unbalanced error detection;
Described data decode module (50) is decoded to enter code word in first order streamline, if be input as the efficient coding code word, it is decoded according to coding rule, if be input as the invalid code code word, then it is decoded as a fixing error flag code word, and obtains being used for that lack of uniformity is calculated and unbalanced error detect circuit (80) calculates needed flag bit by flag bit computing modules (60) such as lacks of uniformity;
Described lack of uniformity is calculated and unbalanced error detect circuit module (80) carries out in the streamline of the second level that lack of uniformity is judged and the RD calculating of current code word, and utilizes the RD value of a clock cycle calculating gained to come whether current code word unbalanced mistake is taken place and judge;
The input data are connected to described data decode module (50) and lack of uniformity flag bit computing module (60) by first order register, in first order streamline, 10 bits input data are carried out 6B/5B decoding and 4B/3B decoding, and the lack of uniformity of calculating 6B and 4B data, the output of described lack of uniformity flag bit computing module (60) is connected to lack of uniformity by second level register and calculates and unbalanced error detect circuit module (80), and the value of RD is re-used as the input of self by third level register.
6, high speed 8B/10B decoder according to claim 5 is characterized in that: described 8B/10B decoder also comprises code word error detection and character types judge module (70) and dateout selection module (90);
Described code word error detection and character types judge module (70), whether the enter code word that is used to detect encoder is invalid code code word as a result, carry out the code word error detection, and be used to judge that enter code word is data character or control character before encoding, carry out the code word type and judge;
Described dateout is selected module, is used for according to the unbalanced error flag of the output position of lack of uniformity calculating and unbalanced error detect circuit module (80) code word or the fixing error flag code word of decoding being selected output;
Described code word error detection and character types judge module (70) carry out the code word error detection in the streamline of the second level, 6B sign indicating number and 4B sign indicating number to this input in respectively to 6B and 4B codeword decoding are put the error flag position, then the decision logic 10B code word code word mistake whether of judging input by simple combinational logic again according to the value of its error flag position.
7, high speed 8B/10B decoder according to claim 6 is characterized in that: described data decode module (50), 6 flag bits that are used to produce; Described code word error detection and character types judge module (70) are judged code word mistake and code word type by these flag bits;
Described 6 flag bits comprise: code_err4 represents that the 4B code word of importing makes a mistake; Code_err6 represents that the 6B code word of importing makes a mistake; The p_28 mark represents that the code word of importing is " 001111 " or " 110000 "; The p1 mark represents that the 6B code word of importing is " 111010 " or " 000101 " or " 110110 " or " 001001 " or " 101110 " or " 010001 " or " 011110 " or " 100001 "; The p2 mark represents that the 4B code word of importing is " 1000 " or " 0001 ";
If code_err=code_err6|code_err4 is 1, then judge the code word mistake;
If K=p_28| is (p1﹠amp; P2) be 1, then former code word is a control character; Be 0, then former code word is a data character.
8, high speed 8B/10B decoder according to claim 6, it is characterized in that, in described lack of uniformity calculating and the unbalanced error detect circuit (80), the input of signal E_Dx3 and p4 conduct or door OR1, its output is as the selection signal input of the MUX MUX1 of alternative; The input of E_D7 and p6 conduct or door OR2, its output is as the selection signal input of the MUX MUX2 of alternative; Disp6 and RD are as the two paths of signals input of the MUX MUX2 and the XOR gate XOR2 of alternative; The output signal rd of alternative MUX MUX2 and disp4 signal are as two signal inputs of XOR gate XOR1; The output signal rd of alternative MUX MUX2 and disp4 are as the two paths of signals input of alternative MUX MUX1; P4 and p6 signal are imported as the signal of inverter N1 and inverter N2 respectively; The output signal of alternative MUX MUX1 is as the D signal input part of d type flip flop D1, and its output Q end is the signal input of alternative MUX MUX2 and XOR gate XOR2 as the RD signal; The clk termination clock signal of d type flip flop D1; The output conduct of inverter N1 and XOR gate XOR1 and two input signals of door AND1; The output conduct of XOR gate XOR2 and inverter N2 and two input signals of door AND2; With door AND1 and with the output signal of door AND2 as or the input signal of door OR3, it is output as the RD_err signal.
9, high speed 8B/10B decoder according to claim 5 is characterized in that: the flag bit that described lack of uniformity flag bit computing module (60) is produced comprises:
The E_D7 flag bit is represented to import the 6B code word and is " 000111 " or " 111000 ";
The E_Dx3 flag bit is represented to import the 4B code word and is " 0011 " " 1100 ";
Whether the number of " 0 " and " 1 " of p4 sign note bit representation input 4B code word equates that equal then p4 is 1, otherwise is 0;
Whether the number that the p6 marker bit represents to import " 0 " and " 1 " of 6B code word equates that equal then p6 is 1, otherwise is 0;
Disp4 is the quantity of the quantity of " 1 " in the 1 flag bit expressive notation input 4B code stream greater than " 0 ", is the quantity of the quantity of " 0 " in 0 expression 4B code stream greater than " 1 ";
Disp6 is the quantity of the quantity of " 1 " in the 1 flag bit expressive notation input 6B code stream greater than " 0 ", is the quantity of the quantity of " 0 " in 0 expression 6B code stream greater than " 1 "; But, when input 6B code word is " 111000 " or " 000111 ", put p6=0, wherein the former puts disp6=1, and the latter puts disp6=0 when input 4B code word is " 1100 " or " 0011 ", puts p4=0, wherein the former puts disp4=1, and the latter puts disp4=0.
10, a kind of based on the processing method of high speed 8B/10B encoder to the mistake input, this method may further comprise the steps:
(1) when the type code position of enter code word K is 1, and enter code word is not when being 12 control characters stipulating in the 8B/10B coding rule, the input signal that encoder is described is wrong, data character precoding module this moment (10a) is encoded its unification according to the 10B sign indicating number of a direct current equilibrium, and through passing to control character coding correcting module (30b) behind the one-level register, select module (40) through passing to data/control character after revising, and finally select coding result output by the K signal;
When (2) input signal of decoder was wrong, if this yard do not belong to the coding result scope of 8B/10B coding schedule, then data decode module (50) was decoded its unification according to a specific character; If this yard is unbalanced with the direct current of a last sign indicating number, then dateout selects module (90) to select a specific character as output according to the unbalanced error flag position that lack of uniformity is calculated and unbalanced error detect circuit module (80) produces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910236064 CN101674089B (en) | 2009-10-19 | 2009-10-19 | High-speed 8B/10B coder, decoder and processing method thereof for error input |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910236064 CN101674089B (en) | 2009-10-19 | 2009-10-19 | High-speed 8B/10B coder, decoder and processing method thereof for error input |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101674089A true CN101674089A (en) | 2010-03-17 |
| CN101674089B CN101674089B (en) | 2013-01-09 |
Family
ID=42021117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910236064 Expired - Fee Related CN101674089B (en) | 2009-10-19 | 2009-10-19 | High-speed 8B/10B coder, decoder and processing method thereof for error input |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101674089B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138889A (en) * | 2012-12-05 | 2013-06-05 | 无锡华大国奇科技有限公司 | High-speed 8B/10B encoding device and coder |
| CN103199866A (en) * | 2012-01-06 | 2013-07-10 | 上海华虹集成电路有限责任公司 | 8b/10b decoding circuit based on rd- |
| CN103516477A (en) * | 2012-06-29 | 2014-01-15 | 华为技术有限公司 | Data transmission method and device |
| CN105263023A (en) * | 2015-10-26 | 2016-01-20 | 西安电子科技大学 | Network code stream real-time receiving method based on high-speed decoding platform |
| CN103199869B (en) * | 2012-01-06 | 2017-05-10 | 上海华虹集成电路有限责任公司 | 8b/10b decoding circuit based on rd+ |
| CN107395539A (en) * | 2017-08-31 | 2017-11-24 | 华南理工大学 | A kind of 8B10B encoder design methods the agreement suitable for JESD204B |
| WO2018040824A1 (en) * | 2016-08-31 | 2018-03-08 | 深圳市中兴微电子技术有限公司 | Data encoding method, data decoding method, devices, and data storage medium |
| CN109889306A (en) * | 2019-01-16 | 2019-06-14 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of coding polarity calculation method for high speed fibre digital transmission system |
| CN111030953A (en) * | 2019-12-04 | 2020-04-17 | 中科芯集成电路有限公司 | Low-delay 8B/10B coding method and device |
| CN112865807A (en) * | 2021-01-11 | 2021-05-28 | 电子科技大学 | 8B/10B coding and decoding circuit with anti-radiation function |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6295010B1 (en) * | 1998-07-02 | 2001-09-25 | Seagate Technology, Llc | 8B/10B encoder system and method |
| CN1300971C (en) * | 2004-01-16 | 2007-02-14 | 中国科学院计算技术研究所 | Method for realizing 16b/20b encoder logic based on double 8b/10b encoder |
| CN101409563A (en) * | 2008-11-25 | 2009-04-15 | 西安电子科技大学 | Apparatus for storing and pre-encoding data of quasi-cyclic shift low-density checkout code |
-
2009
- 2009-10-19 CN CN 200910236064 patent/CN101674089B/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199866A (en) * | 2012-01-06 | 2013-07-10 | 上海华虹集成电路有限责任公司 | 8b/10b decoding circuit based on rd- |
| CN103199866B (en) * | 2012-01-06 | 2017-03-15 | 上海华虹集成电路有限责任公司 | 8b/10b decoding circuits based on rd |
| CN103199869B (en) * | 2012-01-06 | 2017-05-10 | 上海华虹集成电路有限责任公司 | 8b/10b decoding circuit based on rd+ |
| CN103516477A (en) * | 2012-06-29 | 2014-01-15 | 华为技术有限公司 | Data transmission method and device |
| CN103138889A (en) * | 2012-12-05 | 2013-06-05 | 无锡华大国奇科技有限公司 | High-speed 8B/10B encoding device and coder |
| CN105263023B (en) * | 2015-10-26 | 2018-08-03 | 西安电子科技大学 | Network code stream real-time reception method based on high-speed decoding platform |
| CN105263023A (en) * | 2015-10-26 | 2016-01-20 | 西安电子科技大学 | Network code stream real-time receiving method based on high-speed decoding platform |
| WO2018040824A1 (en) * | 2016-08-31 | 2018-03-08 | 深圳市中兴微电子技术有限公司 | Data encoding method, data decoding method, devices, and data storage medium |
| CN107395539A (en) * | 2017-08-31 | 2017-11-24 | 华南理工大学 | A kind of 8B10B encoder design methods the agreement suitable for JESD204B |
| CN109889306A (en) * | 2019-01-16 | 2019-06-14 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of coding polarity calculation method for high speed fibre digital transmission system |
| CN109889306B (en) * | 2019-01-16 | 2021-12-17 | 中国航空工业集团公司洛阳电光设备研究所 | Encoding polarity calculation method for high-speed optical fiber digital transmission system |
| CN111030953A (en) * | 2019-12-04 | 2020-04-17 | 中科芯集成电路有限公司 | Low-delay 8B/10B coding method and device |
| CN112865807A (en) * | 2021-01-11 | 2021-05-28 | 电子科技大学 | 8B/10B coding and decoding circuit with anti-radiation function |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101674089B (en) | 2013-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101674089B (en) | High-speed 8B/10B coder, decoder and processing method thereof for error input | |
| US5625644A (en) | DC balanced 4B/8B binary block code for digital data communications | |
| US7113550B2 (en) | Technique for improving the quality of digital signals in a multi-level signaling system | |
| CN1713626B (en) | Voltage level coding system and method | |
| JP5575237B2 (en) | Data encoding using combined data mask and data bus inversion | |
| US5525983A (en) | Method and apparatus for implementing a type 8B6T encoder and decoder | |
| US6876315B1 (en) | DC-balanced 6B/8B transmission code with local parity | |
| CN103370879A (en) | Power and pin efficient chip-to-chip communications with common-mode rejection and SSO resilience | |
| US6333704B1 (en) | Coding/decoding system of bit insertion/manipulation line code for high-speed optical transmission system | |
| CN104995612A (en) | Methods and systems for chip-to-chip communication with reduced simultaneous switching noise | |
| CN102761389B (en) | Asynchronous master-slave serial communication system, data transmission method and control module | |
| CN101938328A (en) | Signal processing apparatus, information processing apparatus, coding method, and data transmission method | |
| CN101847997B (en) | 9B/10B coder-decoder and realization method thereof | |
| EP2526492A1 (en) | Multiple word data bus inversion | |
| CN103118251A (en) | Multi-level data transmission method and system | |
| CN105791828B (en) | Binary arithmetic coder and its coding method | |
| US5892466A (en) | Coding scheme for transmitting data | |
| US8208578B2 (en) | Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect | |
| US5818362A (en) | 5B4T coding scheme | |
| KR100281738B1 (en) | Encoding and decoding method of nibble inversion and block inversion code, code and decoder | |
| CN111726312A (en) | Differential signal processing apparatus, operation method thereof and method of electronic signaling | |
| US9559872B2 (en) | Signal transmission system | |
| CN113949388B (en) | Coder-decoder and coding-decoding method for serializer/deserializer system | |
| CN102844988B (en) | The method of line coding and device | |
| JPH05284037A (en) | High-speed serial binary data receiver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130109 Termination date: 20151019 |
|
| EXPY | Termination of patent right or utility model |