CN1300971C - Method for realizing 16b/20b encoder logic based on double 8b/10b encoder - Google Patents
Method for realizing 16b/20b encoder logic based on double 8b/10b encoder Download PDFInfo
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Abstract
The present invention relates to the technical field of digital communication, which particularly relates to a logical realization method for a 16b/20b encoder based on double 8b/10b encoders. A 16b/20b encoder is formed on the basis of two 8b/10b encoders, so the problem of time sequence tension caused by a 16b/20b encoder which is directly composed of two 8b/10b encoders and is used for a DDR data source is solved. The run excursion prediction of the 8b/10b encoder is succinctly realized under the condition of a small portion of logical resources. The situation that an encoder unit becomes an entire logic critical path is avoided. Meanwhile, the normalization of the 8b/10b run of double data can be ensured. The present invention provides the scheme that the predicted run excursion is used as an input terminal of the run excursion of the 8b/10b encoder for forcedly controlling the polarities of output encodes of the 8b/10b encoder. The present invention can be further used for realizing 8b/10b encoding generic sets in a larger scale.
Description
Technical field
The present invention relates to digital communication technology field, particularly a kind of 16b/20b encoder logic implementation method based on two 8b/10b encoders, especially use two 8b/10b coder module to add a kind of DDR of being suitable for of a small amount of logical constitution (Double Data Rate, two) transfer of data and meet the 16b/20b encoder implementation method of distance of swimming balance code requirement along data transfer rate.
Background technology
8b/10b encoding scheme and its implementation are the technical result of the 1980s, and the DC component of having controlled easily on the serial transmission circuit owing to it is widely used in communication technical field, fiber optic telecommunications equipment for example, serial to parallel conversion place.Under the 8b/10b coding criterion, when 10 bit data serializations of output are transmitted, on transmission line, can not occur 6 continuous ' 0 ' or 6 continuous ' 1 ', and can guarantee in detection ruler degree arbitrarily that ' 0 ' can not surpass 5 with the difference (distance of swimming balanced deflection) of ' 1 ' number simultaneously.This balance for the DC component on the control serial link is very favourable.Simultaneously, this coded system provides the character synchronizing information, and is also very beneficial for recovered clock.On the specific implementation method, this encoding scheme is taked the method by the synthetic 8b/10b of 3b/4b and 5b/6b, 8 data to be encoded is divided into high 3 and low 5 two groups, extracts the distance of swimming respectively and is offset, be encoded to 4 and 6 two groups respectively, synthesize 10 coding then.The benefit of doing like this is with the coding tasks in parallelization, reduces the combinational logic time-delay as far as possible, saves storage space, improves encoder performance.Coding output result is decided to be low level approximately and sends earlier.In addition, in order to realize pure transfer of data some specific function in addition, the 8b/10b encoding scheme is 256 (2
8) plant outside the data character coding, increased by 12 spcial character codings, with extra signal Key=1 (key: the order sign) represent; Corresponding therewith, 256 general data codings are then represented with Key=0.What the present invention mentioned is general-purpose industrial standard 8b/10b code set.
Owing to the DDR technology do not occur proposing 8b/10b encoding scheme fashion, therefore when the 8b/10b encoding scheme is used for pair along device, can bring difficulty to hardware designs.Common parallel-to-serial converter spare runs on two along clock mode under the time, and what at first will consider is the original position problem, promptly need to determine who serial data to begin alignment from, otherwise parallelization 10 bit word afterwards can't correctly convert 8 codings to.The 8b/10 encoding scheme be this situation prepared some comma (comma: symbol comma), whenever the serial to parallel conversion device detects a comma sequence, will determine the once original position of decoding by the information in this character symbol.The feature of Comma character is (XXX1111100)
BPerhaps (XXX0000011)
B, promptly two zero back are right after five one or two one back and are right after five zero.They also are continuous five one or five zero codings of only several appearance in the 8b/10b coded set.Yet, when if the distance of swimming balance between continuous two 10 codings does not satisfy the 8b/10b standard, it is unexpected that the comma character just might appear, that is to say comma characteristic character latter two 10 coding compositions in succession of elder generation again, thereby destroy the initial aligned position of decoder, cause Content of Communication decoding failure.
Single built-in distance of swimming balancing unit of 8b/10b encoder along work, can realize that thereby distance of swimming balance avoids the two 8b/10b encoders along work of unexpected comma. to be combined along the 8b/10b encoder by two lists of working respectively with clock upper edge and lower edge in essence, the disparity_out of each encoder (disparity: distance of swimming balanced deflection) link to each other, thereby realize the temporal mutual succession that the distance of swimming is offset with the disparity_in of another encoder.But the problem that this scheme exists is to realize that in fact the line of distance of swimming succession has crossed over the two phase clock territory, thereby become the critical path of sequential.For example, be under the situation of 100MHz in clock frequency, the signal on this line send time of delay and input sum settling time must be less than 5ns, i.e. clock cycle of half; If by dividing equally estimation, respectively be 2.5ns then, otherwise will cause sequential in violation of rules and regulations, make the circuit can't operate as normal.And to require the settling time of 2.5ns in the clock cycle be obviously harsh under the situation of 10ns, so become critical path.And this sequential requirement is necessary satisfied, can not rely on the method that increases latch to alleviate.
Summary of the invention
In view of the foregoing, we change traditional two along the 8b/10b coder structure, the feedback model of distance of swimming skew is changed into predictive mode in advance, and the work clock with a pair of 8b/10b encoder unites two into one simultaneously, has realized meeting the high speed 16b/20b encoder of distance of swimming standard at an easy rate.
The 8b/10b encoder is directly used in the DDR transfer of data can bring many difficulties to logical design, and distance of swimming Balance Control and raising clock frequency are wherein more scabrous a pair of contradiction.
The object of the present invention is to provide a kind of simple and easy logic realization method of 16b/20b encoder, both can guarantee that the DDR data according to the 8b/10b standard balance distance of swimming, can not reduce the operating rate of encoder again.
In order to reduce design overhead and to reduce design cost, the route based on existing 8b/10b encoder structure 16b/20b encoder has been taked in invention.Before two 8b/10b encoders arranged side by side, increase level encoder pre-treatment predicting unit, be used for generating in advance the distance of swimming skew input of disp_in, realize correct coding timely with control 8b/10b encoder.
Description of drawings
Fig. 1 is a 16b/20b encoder top layer logic diagram of the present invention.
Fig. 2 is the logical construction schematic diagram of Fore-Coder of the present invention inside.
Fig. 3 is a 16b/20b encoder method flow chart of the present invention.
Fig. 4 is 16b/20b encoder of the present invention (just along a clock) work schedule schematic diagram.
Embodiment: as shown in Figure 1, Z0 and Z1 are respectively 9 data to be encoded, comprise respectively that wherein a command-control signal key.Y is 20 coded data output, meets the maximum run offset-limited.Encoder-0 (encoder: encoder) and Encoder-1 be two identical 8b/10b encoders of logical construction (2,3), all have and force distance of swimming skew Enable Pin (force_disp) and distance of swimming skew input (disp_in), and force distance of swimming skew Enable Pin always to place effective status (' 1 ').General programmable logic device supplier can provide the 8b/10b IP-Core of maturation to the user.In addition, be provided with a word preface among Fig. 1 and select signal input Endian (tail preface, be long numeric data a high position in advance or the low level order of going ahead of the rest), for the output of ' 1 ' expression Encoder-1 encoder preceding, for the output of ' 0 ' expression Encoder-0 encoder preceding.Fore-Coder (precoding unit) (4) is a distance of swimming skew predicting unit, also is core of the present invention.It finishes the prediction to distance of swimming skew in a clock cycle, prediction of output result, giving encoder Encoder-0 (2) is identical latch with Encoder-1 (3) .reg0 (1) with reg1 (5), can constitute by simple d type flip flop, purpose is that the data (Z0 and Z1) that make input postpone a bat clock, so that the distance of swimming skew of calculating output with Fore-Coder is controlled at five unit (Encoder-0 that same clock is mentioned along last arrival 8b/10b encoder Encoder-0 and Encoder-1. here, Encoder-1, Fore-Coder, reg-0, reg1) all synchronous by same clock source (Clock), constituted the 16b/20b encoder framework that the present invention contributed jointly.For succinct consideration, omit the cabling of global synchronization clock Clock and two signals of Global reset Rst among Fig. 1, they all can use in synchronous logic Calc_Disparities (calculating of distance of swimming balanced deflection) module.
Fig. 2 is the logical construction schematic diagram of Fore-Coder inside.Wherein AO-6 (AO:And-Or, with or logic) and AO-3 are combinational logic circuits, and its function is low 5 (adding the Key signal) and high 3 coding characteristic separately according to data to be encoded, and calculating them will be to the influence of distance of swimming skew generation.For example, if 8 bit data Z=(100 11011)
B, then its 10b is encoded to Y=(0100011011)
B, perhaps Y=(1,011 100100)
BAnd if Z=(001 10001)
B, then its 10b coding can only be Y=(1,001 110001)
B. why being all the equal 10b coding of ' 0 ' and ' 1 ' number has this difference, is to be divided into 3b/4b coding and the concurrent working of 5b/6b coding two parts because the 8b/10b encoder is actually.In the 3b/4b coding (100)
BBe encoded to (0100)
BOr (1011)
B, two kinds of 01 numbers in may encoding are all unequal, specifically take which selection decide on the situation of the skew of the distance of swimming on the current transmission line, so that the distance of swimming skew in time on the balanced circuit: if RD=0, then selection (1011)
BIf RD=1 then selects (0100)
B. it can change the distance of swimming deviant of this part (4b) coding.This situation is equally applicable to (11011) in the 5b/6b coding
B, same the existence zero superfluous and one superfluous two kinds of selections of its 6b coding.And for (001) in encoding as 3b/4b
BWith (10001) in the 5b/6b coding
B, their coding all only provides a kind of selection, and wherein 01 numbers equate, thereby can not change local distance of swimming deviant.Modules A O-6 and AO-3 can distinguish 5b part or the 3b local code characteristic partly among the 8b, if can change current distance of swimming skew, then Tog5b (tog:toggle, upset) or Tog3b put ' 1 ', otherwise put ' 0 '.
The VHDL language of modules A O-6 is as follows with reference to logical code:--VHDL Codes for AO-6PROCESS (Key, Z (4 downto 0)) variable comb:STD_LOGIC_VECTOR (5 downto 0); Begin comb:=Key ﹠amp; Z (4 downto 0); CASE comb is
when″000000″＝＞Tog5b＜＝’1’；
when″000001″＝＞Tog5b＜＝’1’；
when″000010″＝＞Tog5b＜＝’1’；
when″000100″＝＞Tog5b＜＝’1’；
when″001000″＝＞Tog5b＜＝’1’；
when″001111″＝＞Tog5b＜＝’1’；
when″010000″＝＞Tog5b＜＝’1’；
when″010111″＝＞Tog5b＜＝’1’；
when″011000″＝＞Tog5b＜＝’1’；
when″011011″＝＞Tog5b＜＝’1’；
when″011101″＝＞Tog5b＜＝’1’；
when″011110″＝＞Tog5b＜＝’1’；
when″011111″＝＞Tog5b＜＝’1’；
when″111100″＝＞Tog5b＜＝’1’；
When others=＞Tog5b＜=' 0 '; End CASE; End PROCESS; The Verilog HDL language reference logical code of modules A O-6 is as follows: // VerilogHDL Codes for AO-6always @ (Key or Z[4:0]) case (Key, Z[4:0] })
6’B0_00000：Tog5b＝1；
6’B0_00001：Tog5b＝1；
6’B0_00010：Tog5b＝1；
6’B0_00100：Tog5b＝1；
6’B0_01000：Tog5b＝1；
6’B0_01111：Tog5b＝1；
6’B0_10000：Tog5b＝1；
6’B0_10111：Tog5b＝1；
6’B0_11000：Tog5b＝1；
6’B0_11011：Tog5b＝1；
6’B0_11101：Tog5b＝1；
6’B0_11110：Tog5b＝1；
6’B0_11111：Tog5b＝1；
6’B1_11100：Tog5b＝1；
Default:Tog5b=0; The VHDL language of endcase modules A O-3 provides below with reference to logical code:--VHDL Codes for AO-3PROCESS (Z (7 downto 5)) begin CASE (Z (7 downto 5)) is
when″000″＝＞Tog3b＜＝’1’；
when″100″＝＞Tog3b＜＝’1’；
when″111″＝＞Tog3b＜＝’1’；
When others=＞Tog3b＜=' 0 '; END CASE; END PROCESS; The Verilog HDL language reference logical code of modules A O-3 provides below: //VerilogHDL Codes for AO-3always @ (Z[7:5]) case (Z[7:5])
3’B000：Tog3b＝1；
3’B100：Tog3b＝1；
3’B111：Tog3b＝1；
default：Tog3b＝0； endcase
Calc_Disparities module among Fig. 2 adopts sequential logic, and it is set according to the word preface and sends last legal 16b/20b coding.This encoder inside is except the mode bit register of necessity, also be provided with a register RD (runing disparity, distance of swimming skew) being used to store each group 20b data distance of swimming deviant afterwards, is current ' 1 ' of one expression number surplus, is current ' 0 ' of null representation number surplus.Its input is exactly above-mentioned Tog5b and Tog3b, and word preface control Endian and RD, output is exactly to be used to control the function of this module of disp_in. of the pressure distance of swimming of two 8b/10b encoders skew input to be coding polar character according to the current distance of swimming deviant and the data self that are encoded, the desirable distance of swimming skew input of two 8b/10b encoders of prediction except RD.For example, if current RD=1, represent present circuit distance of swimming positively biased, so, send non-positively biased (' 1 of encoding by the coding (first preface coding) of the output skew that should inherit RD=1 earlier of word preface ' number be not dominant); If there is the coding (' 0 of negative bias really ' number be dominant), the coding of non-negative bias is sent in then postorder coding (by the coding of exporting after the word preface) skew that should inherit RD=0, put RD=1 simultaneously, otherwise inherit the skew of RD=1, send the coding of non-positively biased, put RD=0. simultaneously
Be the VHDL language identifying code of module Calc_Disparities below:--VHDL Codes for Module Calc_DisparitiesCalc_Disparities:PROCESS (Clock) BEGIN IF RISING_EDGE (Clock) THEN
IF(Rst＝’1’)THEN
RD＜＝’0’；
disp_in＜＝″00″；
ELSE
RD＜＝Tog5b(1)xor?Tog3b(1)xor?Tog5b(0)xor?Tog3b(0)xor?RD；
disp_in(1)＜＝(RD?and?Endian)or((Tog5b(0)xor?Tog3b(0)xorRD)and?not?Endian)；
disp_in(0)＜＝(RD?and?not?Endian)or((Tog5b(1)xor?Tog3b(1)xor?RD)and?Endian)；
END IF; END IF; END PROCESS Calc_Disparities; Be the Verilog HDL language reference code of module Calc_Disparities below: //VerilogHDL Codes for Module Calc_Disparitiesalways @ (posedge Clock) if (Rst) begin
RD＜＝0；
disp_in＜＝2′b00； end else?begin
RD＜＝Tog5b[1]^Tog3b[1]^Tog5b[0]^Tog3b[0]^RD；
disp_in(1)＜＝(RD?&?Endian)|((Tog5b[0]^Tog3b[0]^RD)&?！Endian)；
disp_in(0)＜＝(RD?&?！Endian)|((Tog5b[1]^Tog3b[1]^RD)&?Endian)；
end
Fig. 3 has provided the workflow diagram of general 16b/20b encoder, comprises 5 links altogether, S0 ~ S4; Wherein S1 and S2 two steps are fully concurrent, do not have causality or precedence.With reference to Fig. 3, to being described in detail as follows of these 5 steps:
Data arrive (S0), data latching and distance of swimming balanced deflection prediction (S1+S2), controlled encoding (S3), and coding and line output (S4);
Step S0: initial link, corresponding each clap effective timer time (upper edge of clock or lower edge) of clock, the data that are encoded that two-way is legal (all being 9 respectively) are at this inlet that arrives the 16b/20b encoder constantly, carry out and accept the preparation handled;
Step S1: to latching of the pending data of two-way, in order that make clock cycle of data delay, the distance of swimming balanced deflection signal that generates with corresponding prediction arrives corresponding 8b/10b encoder inlet simultaneously, prepares to accept local 8b/10b coding;
Step S2: this step and S1 are parallel fully.In this step, each circuit-switched data when coding reversional distance of swimming balanced deflection with predicted, the function that this step is finished is by the 4th part (Fore-Coder among Fig. 1, precoding unit) realizes, two paths of data is the effect of intercoupling in this link, that is to say that must consider the 8b/10b encoding characteristics of an other circuit-switched data to the prediction of the distance of swimming balanced deflection of each circuit-switched data, the word preface control (Endian) of 16b/20b coding is also worked in this link;
Step S3: two 8b/10b encoders are encoded with the 8b/10b that forces distance of swimming skew control to the data of respective branch, be called controlled encoding, because reversional distance of swimming balanced deflection is finished prediction in link S2, and become the input of S3 link, so can think that two 8b/10b encoders in this link work fully independently, two paths of data not coupling in this link;
Step S4: the output of two-way 8b/10b encoder is merged into one road coding output, settles out before next efficient clock edge, finishes the 16b/20b coding.
These 5 links (step S0-S4) need 3 to clap the clock cycle in timing altogether, as shown in Figure 4.
To be example along the clock work situation just, the 1st clock upper edge, the data that are encoded arrive the encoder inlet, corresponding to the step S0. among Fig. 3
The 2nd clock upper edge, execution in step S1 and S2 finish latching and distance of swimming skew prediction the data that are encoded.
The 3rd clock upper edge, execution in step S3, the controlled 8b/10b that finishes two paths of data encodes.
(concrete time location depends on the performance index of device) sometime between the 3rd clock upper edge and the 3rd clock lower edge, the result of the 8b/10b coding of two paths of data exports effectively, be merged into the 16b/20b coding on the circuit, give the next stage circuit, guarantee that the 16b/20b coding is stable before the 4th clock upper edge.
As mentioned above, coding output is stablized from the data due in to 16b/20b, needs 3 clock cycle altogether, as shown in Figure 4.
Good effect of the present invention is embodied in:
1. meet general specification. The output data serializing that guarantees encoder strictly observes 8b/10b rule afterwards The distance of swimming balance requirement of model.
2. expense is low. Compare with the 16b/20b encoder that directly consists of with two 8b/10b encoders, only Increase the one-level synchronised clock and postpone and a small amount of logic, can realize complete 16b/20b coding staff Case.
3. speed is fast. The logic of the level encoder pre-treatment/predicting unit that increases is very simple, can structure Become the sequential key path, thereby do not affect the speed of service of chip integral body.
4. be easy to promote. The distance of swimming skew look-ahead method that the present invention proposes can be used very easily In the realization of the encoders such as 24b/30b, 32b/40b or 64b/80b, the strict guarantee distance of swimming is flat The weighing apparatus standard. This method is applicable to that simultaneously the above-mentioned coding of the logical devices such as FPGA and ASIC patrols Collect design.
English abbreviation is explained
DDR:Double Data Rate, two along data transfer rate
QDR:Quadra-Data Rate, four times of fast data transfer rates
Disparity: distance of swimming balanced deflection
Endian: the tail preface, promptly the high position of long numeric data is gone ahead of the rest or the order that low level is gone ahead of the rest
IP-Core:Intellectual Property Core, the intellectual property core
FPGA:Field Programmable Gate Array, field programmable gate array
ASIC:Application Specific Integrated Circuit, application-specific integrated circuit (ASIC)
Claims (6)
1. general 16b/20b encoder design method, it is characterized in that, 20 codings by given word preface output meet distance of swimming balance principle and 8b/10b coding criterion, adopt the data that data that a pair of general 8b/10b encoder transmits constantly to rising edge clock signal and clock signal trailing edge transmit constantly to encode respectively, coding polar character according to the current distance of swimming deviant and the data self that are encoded, the output encoder polarity of two 8b/10b encoders is controlled in the desirable distance of swimming skew input of two 8b/10b encoders of prediction, and the work clock of described two 8b/10b encoders is synchronous by same clock source.
2. by the described general 16b/20b encoder design method of claim 1, it is characterized in that being input as two group of 9 bit binary data, comprise 1 key control bit respectively, through level encoder pre-treatment predicting unit, be used for generating in advance of the distance of swimming skew input of distance of swimming skew input signal with control 8b/10b encoder, send into 8b/10b encoder separately respectively, make 20 bit data serializations of output meet 8b/10b distance of swimming balance standard afterwards.
3. by the described general 16b/20b encoder design method of claim 1, it is characterized in that: a word preface control end is set, is used for determining two precedences between the output of 8b/10b encoder.
4. general 16b/20b encoder, by two identical 8b/10b encoders of logical construction is a 8b/10b encoder (2) and the 2nd 8b/10b encoder (3), first latch (1), second latch (5) and distance of swimming skew predicting unit (4) are formed, it is characterized in that, Z0 and Z1 are respectively 9 input data to be encoded, comprise 1 key control bit respectively, Z0 and Z1 are input to first latch (1) and second latch (5) and distance of swimming skew predicting unit (4) respectively, coding polar character according to the current distance of swimming deviant and the data self that are encoded, the desirable distance of swimming skew input of two 8b/10b encoders of prediction, first latch (1) and second latch (5) output are connected to a 8b/10b encoder (2) and the 2nd 8b/10b encoder (3), distance of swimming skew predicting unit (4) output is connected in a 8b/10b encoder (2) and the 2nd 8b/10b encoder (3), the Y1 of the one 8b/10b encoder (2) and the output of the 2nd 8b/10b encoder (3), Y0 merges into Y, is coded data output; First latch (1) and second latch (5) postpone a clock cycle, so that the distance of swimming skew of calculating output with distance of swimming skew predicting unit (4) same clock along on arrive a 8b/10b encoder (2) and the 2nd 8b/10b encoder (3), and a 8b/10b encoder (2) and the 2nd 8b/10b encoder (3), first latch (1) and second latch (5) and the distance of swimming to be offset predicting unit (4) synchronous by same clock source.
5. the coding method of a general 16b/20b encoder, its step comprises: data arrive (S0), data latching (S1), distance of swimming balanced deflection prediction (S2), controlled encoding (S3), and coding and line output (S4),
Data arrive: initial link, corresponding each clap effective timer time of clock, the data that are encoded that two-way is legal are at this inlet that arrives the 16b/20b encoder constantly, carry out and accept the preparation handled;
Data latching: to latching of the pending data of two-way, in order that make clock cycle of data delay, the distance of swimming balanced deflection signal that generates with corresponding prediction arrives corresponding 8b/10b encoder inlet simultaneously, prepares to accept local 8b/10b coding;
The prediction of distance of swimming balanced deflection: this step and data latching step are parallel fully, in this step, coding polar character according to the current distance of swimming deviant and the data self that are encoded, the desirable distance of swimming skew input of two 8b/10b encoders of prediction, two paths of data is the effect of intercoupling in this step, that is to say, must consider the 8b/10b encoding characteristics of an other circuit-switched data to the prediction of the distance of swimming balanced deflection of each circuit-switched data, the word preface control of 16b/20b coding is also worked in this step;
Controlled encoding: two 8b/10b encoders are encoded with the 8b/10b that forces distance of swimming skew control to the data of respective branch, be called controlled encoding, because reversional distance of swimming balanced deflection is finished prediction in the prediction of distance of swimming balanced deflection, and become the input of this controlled encoding step, two 8b/10b encoders in this step are worked fully independently, two paths of data not coupling in this step;
Coding and line output: the output of two-way 8b/10b encoder is merged into one road coding output, settles out before next efficient clock edge, finishes the 16b/20b coding;
Wherein: two 8b/10b encoders, finish two latchs of data latching and finish the work clock of distance of swimming skew predicting unit of distance of swimming skew prediction synchronous by same clock source.
6. according to the coding method of the general 16b/20b encoder of claim 5, described 5 steps need 3 to clap the clock cycle in timing altogether.
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663724A (en) * | 1996-03-28 | 1997-09-02 | Seagate Technology, Inc. | 16B/20B encoder |
| US6501396B1 (en) * | 2001-03-30 | 2002-12-31 | Xilinx, Inc. | Scalable physical coding sublayer (PCS) and 8B/10B encoder |
| US6624770B1 (en) * | 2001-12-13 | 2003-09-23 | Cisco Technology, Inc. | Block coding system and method of data aggregation |
| US6614369B1 (en) * | 2002-03-05 | 2003-09-02 | International Business Machines Corporation | DC balanced 7B/8B, 9B/10B, and partitioned DC balanced 12B/14B, 17B/20B, and 16B/18B transmission codes |
| CN1449132A (en) * | 2002-03-28 | 2003-10-15 | 日本电气株式会社 | Multiplex system using common network group to transmit multiple 8B/10B bit stream |
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| CN1558582A (en) | 2004-12-29 |
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