CN113949388B - Coder-decoder and coding-decoding method for serializer/deserializer system - Google Patents

Coder-decoder and coding-decoding method for serializer/deserializer system Download PDF

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CN113949388B
CN113949388B CN202111565744.4A CN202111565744A CN113949388B CN 113949388 B CN113949388 B CN 113949388B CN 202111565744 A CN202111565744 A CN 202111565744A CN 113949388 B CN113949388 B CN 113949388B
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code
code words
code word
bits
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CN113949388A (en
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江新远
崔根强
吕炳赟
方伟
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Zhejiang Xinsheng Electronic Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
    • H04L1/0016—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy involving special memory structures, e.g. look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition

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Abstract

The present invention provides an encoder and an encoding method for a serializer/deserializer (SerDes) system for encoding an (M-1) -bit codeword into an M-bit codeword, wherein M is an even number greater than or equal to 4. The look-up table of the code table is designed to ensure the DC balance of the code and maintain a certain level of effective bandwidth utilization rate, and the maximum run length of the code output code stream is controlled at M-2. By means of a look-up table: if the (M-1) -bit codeword is mapped to a balanced codeword (codeword with D = 0), where D is calculated as D = D-M/2, and D represents the number of 1 in the M-bit codeword, directly outputting the balanced codeword as an output M-bit codeword; if the (M-1) bit code word is mapped to the code word of D = -1, selecting the code word of D =1 or D = -1 as the output M bit code word according to the running difference value RD; if the (M-1) -bit codeword is mapped to the codeword of D = -2, the codeword of D =2 or D = -2 is selected as the output M-bit codeword according to the run difference value RD. Correspondingly, the invention also provides a decoder and a decoding method corresponding to the encoder and the encoding method.

Description

Coder-decoder and coding-decoding method for serializer/deserializer system
Technical Field
The present invention relates to the field of line coding and decoding design, and more particularly, to an encoder, an encoding method, a decoder and a decoding method for a serializer/deserializer (SerDes) system.
Background
In a serializer/deserializer system, line coding and decoding are very important modules. The line coding mechanism converts the incoming raw data into a format that can be received by the receiver and ensures that sufficient bit flips are provided to the clock recovery circuit. The encoded code stream can maintain good DC balance, and the encoder also provides a method for aligning data to words. The main implementation of line coding is a numerical value lookup method, that is, a lookup table of a code table is used to query a code word to be coded to find out a corresponding code word as an output code word. The proposed line codecs include 3B4B, 5B6B, 8B10B and 9B10B, 8B10B codes, which are currently adopted by most high-speed serial bus standards such as universal serial bus 3.0 (USB 3.0), serial advanced technology component (SATA), Peripheral Component Interconnect Express (PCIE), and fast input and output (RapidIO), 9B10B codes are applied to Passive Optical Network (PON) systems, and in some lower-order serializer/deserializer systems, 3B4B and 5B6B are used, where the first number and the second number in the above 3B4B, 5B6B, 8B10B, and 9B10B respectively represent the number of bits of the codeword to be encoded and the number of bits of the output encoded codeword, for example, 9B10B represents that a 9-bit codeword is encoded into a 10-bit codeword.
The U.S. Pat. No. US 6977599B 2 provides an 8B10B codec technical solution, which has the advantages of short run length, good Direct Current (DC) balance, and being suitable for parallel coding and gate circuits to save Read Only Memory (ROM) resources, but its coding efficiency is low, and 25% of coding redundancy in a high-speed serializer/deserializer system will be a bottleneck in improving effective bandwidth.
The paper document "line code for PON system-9B 10B" is published in the optical communication technology 2010, 3 rd, 27-29, and the authors are yangling, zhao flying, cuilijia and zhuangyu, and the paper document mainly provides a coding and decoding technical scheme with short coding run and high bandwidth utilization, but the technical scheme still has the following disadvantages to be further improved: (1) the problem that the K code and the D code are subjected to code string in serial communication is not considered, and the method is not suitable for an application scene of boundary alignment; (2) the RD + code word and the RD-code word are not related, so that the code table optimization is not convenient, wherein the RD + code word and the RD-code word respectively represent a code word with a positive running difference value and a code word with a negative running difference value; and (3) the look-up table for realizing the code table needs to store the RD + code word and the RD-code word at the same time, so that the resource consumption is large, and the method is not suitable for the application scene with the shortage of ROM resources.
The world intellectual property organization published patent application WO 2008/134977 a1 proposes a codec with high bandwidth utilization and simple decoding implementation, but the following disadvantages of the codec still need to be further improved: (1) the designed K code and the D code generate serial codes in serial communication, and the method is not suitable for application scenes with boundary alignment; and (2) the maximum run length of the D code is 10, so that the difficulty of clock recovery of a receiving end is improved.
Disclosure of Invention
The invention provides a coding and decoding technical scheme for a serializer/deserializer system, which is mainly used for solving the following technical problems: (1) the coding overhead is reduced to improve the effective bandwidth utilization rate; (2) the maximum run length is controlled within 8 during transmission, so that the clock recovery of a receiving end is easier; (3) 1 and 0 in the bit stream alternate as much as possible, so that the DC balance of the bit stream is ensured; (4) the D + code word is obtained by inverting the D-code word according to bits, so that a large amount of resources are saved when the code table is stored; (5) the code table mapping rule is optimized, so that the gate circuit is convenient to realize, and the ROM resource is saved; and (6) the technical scheme of coding and decoding can be further used for designing a special boundary detection K code so that the boundary detection K code and the D code cannot generate serial codes.
The present invention provides an encoding method for a serializer/deserializer system and an encoder performing the encoding method, and is characterized in that the encoding method includes: finding out a corresponding M-bit code word as a temporary code word according to an (M-1) -bit code word to be coded and a corresponding 1-bit K code indication signal through a lookup table for realizing a code table, wherein difference values (disparities) of all the M-bit code words in the lookup table are respectively 0, -1 or-2, or 0, +1 or +2, M is an even number greater than or equal to 4, all the M-bit code words in the lookup table comprise a plurality of D code words and a plurality of K code words, and all the D code words with difference values of 0 in the lookup table do not comprise a plurality of M-bit code words with front M/2 bits being all 0 or 1 and rear M/2 bits being all 0 or 1; and determining to use the temporary code word as a code word or use a result of bitwise negation of the temporary code word as the code word according to the difference value of the temporary code word and the operation difference value, and updating the operation difference value according to the result.
In the above coding method, under the design that the difference values of all M-bit codewords in the lookup table are respectively 0, -1 or-2, when the difference value of the temporary codeword is-1 or-2 and the running difference value is negative, a result obtained by inverting the temporary codeword by bit is output as the coded codeword, otherwise, the temporary codeword is used as the coded codeword, where the updated running difference value is the running difference value before plus 2 times the difference value of the coded codeword.
In the above coding method, L is in the lookup table0The M-bit D code words with difference value of 0 are arranged from large to small in decimal value and are equal to the decimal value (2)M-1-L0+1 to (2)M-11) (M-1) bits of code word to be coded, L1The M-bit D code words with the difference value of-1 are arranged from large to small in decimal value and are matched with the decimal value (2)M-1-L0-L1+1 to (2)M-1-L0) A one-to-one correspondence of (M-1) bit-band encoded codewords, and L2The M-bit D code words with the difference value of-2 are arranged from large to small in decimal value and are 0 to (L) with the decimal value2The (M-1) bits of the code word to be coded of-1) have one-to-one correspondence, wherein L0+L1+L2=2M-1。
In the above-mentioned encoding method, x M-bit code words, which have a difference of-2 and are not used as longer hamming distances among the D-code words, among the M-bit code words, are selected as x M-bit common K-code words of the lookup table, and M-bit code words "00 … 011 … 1" in which the first M/2 bits are all 0 and the last M/2 bits are all 1, and M-bit code words "11 … 10100 … 0" in which the first (M/2) -1 bit is all 1, the M/2 th bit is 0, the (M/2) +1 bit is 1, and the other bits are all 0 are selected as two boundary-aligned K-codes of the lookup table.
The present invention provides a decoding method for a serializer/deserializer system and a decoder performing the decoding method, and is characterized in that the decoding method includes: adjusting the M-bit code words to be decoded according to difference values of the M-bit code words to be decoded to generate M-bit adjusted code words, wherein M is an even number greater than or equal to 4, all the M-bit code words in a lookup table comprise a plurality of D code words and a plurality of K code words, and all the D code words with the difference value of 0 in the lookup table do not comprise a plurality of M-bit code words with the first M/2 bits being all 0 or 1 and the last M/2 bits being all 0 or 1; and finding out a corresponding (M-1) -bit code word as a decoding code word according to the M-bit adjusting code word through the lookup table, and outputting a corresponding 1-bit K code indication signal and a corresponding 1-bit decoding error indication signal.
In the above decoding method, when the difference values of all M-bit code words in the lookup table used for implementing the code table are designed to be 0, -1, or-2, if the difference values of all M-bit code words to be decoded are +1 or +2, the result obtained by bit-wise negating the M-bit code words to be decoded is taken as the adjustment code word, otherwise, the M-bit code words to be decoded are taken as the adjustment code word, when the difference values of all M-bit code words in the lookup table used for implementing the code table are designed to be 0, +1, or +2, if the difference values of all M-bit code words to be decoded are-1 or-2, the result obtained by bit-wise negating the M-bit code words to be decoded is taken as the adjustment code word, otherwise, the M-bit code words to be decoded are taken as the adjustment code word.
In the above decoding method, L in the lookup table0The M-bit D code words with difference value of 0 are arranged from large to small in decimal value and are equal to the decimal value (2)M-1-L0+1 to (2)M-1A one-to-one correspondence of (M-1) bit codewords of-1), L1The M-bit D code words with the difference value of-1 are arranged from large to small in decimal value and are matched with the decimal value (2)M-1-L0-L1+1 to (2)M-1-L0) A one-to-one correspondence of (M-1) -bit code words of, and L2The M-bit D code words with the difference value of-2 are arranged from large to small in decimal value and are 0 to (L) with the decimal value2A one-to-one correspondence of (M-1) bit codewords of-1), wherein L0+L1+L2=2M-1。
In the decoding method, x M-bit code words with a difference value of-2 and not used as longer hamming distance of the D-code words are selected as x M-bit common K code words of the lookup table, and M-bit code words "00 … 011 … 1" with front M/2 bits all being 0 and rear M/2 bits all being 1, and M-bit code words "11 … 10100 … 0" with front (M/2) -1 bits all being 1, M/2 bits being 0, (M/2) +1 bits being 1 and other bits all being 0 are selected as two boundary aligned K codes of the lookup table.
In summary, the encoding and decoding technical solution for the serializer/deserializer system provided in the present invention has the following advantages: (1) the code stream DC balance is ensured, and meanwhile, a certain level of coding efficiency and effective bandwidth utilization rate are maintained; (2) because the D + code word is obtained by inverting the D-code word according to the bit, the code table mapping rule is optimized, the realization of a logic gate circuit is facilitated, a large amount of resources can be saved, and the method is suitable for the application scene with the shortage of ROM resources; and (3) if the special design of the boundary detection K code exists, on the premise of no error transmission, the coding and decoding technical scheme does not have the condition that the D code and the common K code are subjected to code string, so that the boundary synchronization accuracy is ensured.
Drawings
FIG. 1 is a functional block diagram of a serializer/deserializer system according to an embodiment of the present invention;
FIG. 2 is a flow chart of an encoding method for a serializer/deserializer system according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a code table used by an encoder, an encoding method, a decoder and a decoding method for a serializer/deserializer system according to an embodiment of the invention;
FIG. 4 is a diagram illustrating state transitions of run disparity values for an encoding method for a serializer/deserializer system according to an embodiment of the present invention;
fig. 5 is a flowchart of a decoding method for a serializer/deserializer system according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. In addition, the exemplary embodiments are only one implementation of the design concept of the present invention, and the following examples are not intended to limit the present invention.
In the present invention, the serializer/deserializer system is a Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology. That is, at the transmitting end, the multi-path low-speed parallel signals are converted into high-speed serial signals, and the high-speed serial signals are converted into low-speed parallel signals again at the receiving end through a transmission medium (an optical cable or a copper wire). The serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and improves the transmission rate of signals, thereby greatly reducing the communication cost. That is, the codec scheme of the present invention can be used in a system employing Time Division Multiplexing (TDM) or point-to-point (P2P) serial communication techniques.
In the present invention, run length refers to the number of consecutive 0 or 1 in the code stream, and the maximum run length refers to the maximum run length of all the encoded code words in the code table. When the run length is smaller, it means that 0 and 1 are distributed more uniformly, and the receiving end clock recovery is easier. DC balance means that 1 and 0 in the bit stream appear alternately, so the encoded code word can be regarded as an alternating current signal and passes through the capacitor smoothly. The DC imbalance refers to the occurrence of a plurality of consecutive 1 s or 0 s in the bit stream, and the signal in the time period can be considered as a direct current, and when passing through the capacitor, the coding error after transmission can be caused due to the relationship of voltage level. The purpose of the high speed serial bus using line coding techniques is to balance 1's and 0's in the bit stream, thereby achieving DC balance.
In the present invention, the data is separated by an aligned K-code sequence, the receiver scans the data stream for a particular bit sequence (i.e., aligned K-code), and if a sequence is found, the deserializer adjusts the word boundaries to match the detected aligned K-code word sequence. The scanning is continued and once the alignment is determined, all subsequent K-code and D-code characters find that the alignment has been determined. Of course, in any sequence combination, the aligned K-code sequence must be unique, and any other character sequence does not contain the character.
In the invention, an operation difference value (Running Disparity) is abbreviated as RD value, which represents the degree of unbalance in the encoding process, and when 0 in the encoding code word is more than 1, the RD value is negative; when 1 is more than 0 in the code word, the RD value is positive; when the number of 0 and 1 in the code word is equal, the value of RD is 0. The difference value (Disparity) is expressed as D = D-M/2, where D is the number of 1's in the M-bit encoded codeword, D is the difference case of 0/1's in the M-bit encoded codeword, D + represents more 1 than 0, D-represents more 0 than 1, and D =0 represents that the encoded codeword is a balanced codeword, i.e. 0 is as much as 1.
Referring to fig. 1, fig. 1 is a functional block diagram of a serializer/deserializer system according to an embodiment of the invention. The serializer/deserializer system includes an encoder 11, a serializer 12, a channel 13, a deserializer 14, a boundary alignment module 15, and a decoder 16. The encoder 11 is electrically connected with the serializer 12, the serializer 12 transmits serial data to the channel 13 through the channel 13, the deserializer 14 acquires the serial data through the channel 13, the deserializer 14 is electrically connected with the boundary alignment module 15, and the boundary alignment module 15 is electrically connected with the decoder 16.
The encoder 11 receives N ･ (M-1) -bit parallel data input to the serializer/deserializer system and divides into N (M-1) -bit codewords to be encoded from high to low. The encoder 11 then encodes N (M-1) bit codewords to generate N M bit codewords, where N is equal to or greater than 2, and M is an even number equal to or greater than 4, e.g., N =8, and M =4, 6, or 10. In addition, the encoder 11 also receives N-bit K code indication signals, wherein the (M-1) -bit code word to be encoded of each channel corresponds to the 1-bit K code indication signal, and the (M-1) -bit code word to be encoded of each channel is to be encoded into a D code or a K code according to the corresponding 1-bit K code indication signal. The K codes are further classified into general K codes and boundary-aligned K codes, wherein the boundary-aligned K codes are designed as specific bit sequences. The encoder 11 comprises a plurality of hardware circuits including look-up tables for implementing code tables.
The serializer 12 receives parallel data of N-way M-bit code words and sequentially outputs the parallel data from high to low to the channel 13. In this embodiment, the channel 13 may be a wired channel for transmission or an optical fiber with an electrical-to-optical conversion function, and the invention is not limited thereto. The deserializer 14 receives the serial data of the N M-bit codewords and combines the N M-bit codewords from high to low into N ･ M-bit parallel data that is output to the boundary alignment module 15. The boundary alignment module 15 is configured to find a boundary aligned K code in the N ･ M-bit parallel data to align the K code and the D code in the N ･ M-bit parallel data, so as to output the aligned N ･ M-bit parallel data. It should be noted that in other embodiments, the positions of the boundary alignment module 15 and the deserializer 14 may be interchanged, i.e., the boundary alignment is performed before the deserialization is performed, and the invention is not limited thereto.
The decoder 16 receives the parallel data of N ･ M bits after alignment adjustment, and divides the parallel data from high to low into N paths of M-bit code words to be decoded. The decoder 16 then decodes the N-way M-bit codeword to produce N-way (M-1) codewords as parallel data output by the serializer/deserializer system. Further, the decoder 16 may additionally output an N-bit K-code indication signal and an N-bit decoding error indication signal, wherein each (M-1) -bit code word corresponds to a 1-bit K-code indication signal and a 1-bit decoding error indication signal. The decoder 16 includes a plurality of hardware circuits including look-up tables for implementing code tables.
Referring to fig. 1 and fig. 2, fig. 2 is a flowchart illustrating an encoding method for a serializer/deserializer system according to an embodiment of the invention. First, in step S21, the encoder 11 receives N ･ (M-1) -bit parallel data input to the serializer/deserializer system, and divides into N-way (M-1) -bit codewords to be encoded from high to low. Then, in step S22, the encoder 11 receives the N-bit K code indication signal and obtains N (M-1) bits of code words to be encoded. Then, in step S23, for each (M-1) -bit codeword to be coded, the encoder 11 finds the corresponding M-bit codeword as the corresponding temporary codeword according to the (M-1) -bit codeword to be coded and the corresponding 1-bit K code indication signal through the lookup table of the code table, where the temporary codeword can be designed to be D ≦ 0 (in other embodiments, the temporary codeword can also be designed to be D ≧ 0). Next, in step S24, the encoder 11 determines, according to the difference between the running difference and the temporary codeword, whether to use the result of inverting the temporary codeword by bit as the output M-bit codeword or to directly use the temporary codeword as the output M-bit codeword, and updates the running difference accordingly. In step S25, the encoder 11 combines the N M-bit code words from high to low into N ･ M-bit data that is output to the channel.
In step S23, the code table is implemented as a value lookup table and is obtained through special design, and the design concept is as follows: (1) in order to ensure the DC balance of the coding, codewords with equal or comparable numbers of 0 and 1 in M-bit codewords need to be selected as possible as candidate codewords; (2) in order to control the run length of the coded bit stream to be as short as possible, deleting the code words with longer continuous 0 or 1 of the front (M/2) high bits or the rear (M/2) low bits in the alternative code words; (3) in order to reduce the resource occupation of the coding lookup table, the code words with D not equal to 0 appear in the form of pairing codes, the code words with D >0 in the pairing codes can be obtained by bit-wise negation of the code words with D <0, and only the code words with D less than or equal to 0 or D more than or equal to 0 need to be stored during realization; (4) for the convenience of logic gate implementation, the more concentrated 0/1 distribution in the code table, the simpler the most simplified and-or formula obtained by simplifying the carnot diagram, so that when the mapping rule of the code table is designed, the M-bit code words are arranged from large to small; (5) the principle of designing the K code is that the K code and the D code cannot be repeated, and the average Hamming distance of the set of the K code and the D code is as large as possible, so that the probability that the D code is changed into the K code by mistake in the transmission process is reduced; and (6) in order to ensure the correctness of the alignment of the receiver in the data stream, an alignment K code needs to be designed, the alignment K code sequence needs to be unique, and any other D code and K code combination does not contain the sequence.
Further, according to the above idea, taking the temporary codeword D ≤ 0 as an example, the code table is designed by first designing a D code table and then designing a K code table, and the D code table is designed by the following steps: step (1) in this 2MInitially selecting balanced code words (D = 0), all D = +/-1 code words and at least one part of D = +/-2 code words from the code words as a code word set; step (2), in order to control the maximum run length of the code output code stream, deleting the code words of which the front (M/2) high bits are all 0 or all 1 and the rear (M/2) low bits are all 0 or all 1 in the code word set so as to ensure that the front (M/2) high bits or the rear (M/2) low bits only have (M/2-1) bit all 0 or all 1 code words at most in the code word set, and the code stream only has (M-2) bit continuous 0 or 1 at most; step (3), selecting L from the code word set0The M balanced code words are represented by decimal values, arranged from large to small, and then are compared with the input data value (2)M-1-L0+1 to (2)M-1-1) of (M-1) code words to be coded correspond one to one, wherein according to the Karno graph simplification rule, the more concentrated the distribution of 0 and 1 is, the easier the simplification is, the simpler the obtained simplest AND-OR formula is, and the simpler the gate circuit is realized; step (4), selecting L from code word set1D = +1 codeword and L1D = -1 code words forming L1The method comprises the following steps of assembling pairing codes, wherein any one of the assembling pairing codes needs to meet the following condition that each bit of a D = +1 code word and a D = -1 code word is different, namely the D = +1 code word can be obtained by bit negation of the D = -1 code word; step (5), adding L1D = -1 code word in group pairing code is expressed by decimal number, arranged from large to small and then is matched with input data value (2)M-1-L0-L1+1 to (2)M-1-L0) The (M-1) bits of the code word to be coded are in one-to-one correspondence; step (6), selecting L2D = +2 codewords and L2D = -2 code words forming L2The method comprises the following steps of assembling pairing codes, wherein any one of the assembling pairing codes needs to meet the following condition that each bit of a D = +2 code word and a D = -2 code word is different, namely the D = +2 code word can be obtained by bit negation of the D = -2 code word; and a step (7) of converting L2D = -2 code words in the group pairing code are represented by decimal numbers, are arranged from large to small and are matched with input data values from 0 to (L)2The (M-1) bits of the code word to be coded of-1) have one-to-one correspondence, wherein L0+L1+L2=2M-1. 2 can be completed by the above steps (1) to (7)M-1And coding the (M-1) -bit code word to be coded into a lookup table of the D code. Take M =10 as an example, L0May be 247, L1May be 191, and L2May be 74.
And then, designing a K code lookup table in the rest code words after screening. The design steps of the K code table are as follows: step (8), selectingyForming a pairing code by using the D = +2 code words and the D = -2 code words, wherein the pairing code needs to meet the following condition, each bit of the D = +2 code words and each bit of the D = -2 code words are different, namely the D = +2 code words can be obtained by bit-wise negation of the D = -2 code words; step (9) fromyIn the group pairing code, the average Hamming distance from all D codes is selected as large as possiblexGroup of asxGroup of common K codes, whereinx≤y(ii) a Step (10) of subjectingxIn the group pairing code D<The 0 code word is represented by decimal number, arranged from large to small and arranged from large to smallxThe (M-1) bit code words to be coded of each specific input data value are in one-to-one correspondence; and (11) forming a pairing code of an M-bit code word "00 … 011 … 1" in which the first M/2 bits are all 0 and the last M/2 bits are all 1, and "11 … 10100 … 0" in which the first (M/2) -1 bits are all 1, the M/2 th bit is 0, the (M/2) +1 bits are 1, and the other bits are all 0, as a special K code for boundary alignment. And (2) splicing two special K codes to construct a 2M bit sequence with the run length of (M-1). Because the maximum run length of any combination of other K codes and D codes is (M-2), the aligned K codes cannot be in serial codes with other K codes and D codes during boundary detection, and therefore a receiving end detects the sequence and can finish boundary alignment. Through the above steps (8) to (11), the process is completedxThe (M-1) -bit code words to be encoded of a particular input data value are organized into a look-up table of general K codes and the (M-1) -bit code words to be encoded of a particular two input data values are organized into aligned K codes. Taking the example of M =10, the method,xmay be 13 and the two boundary K codes are "0000011111" and "1111010000", respectively.
Referring to fig. 3, fig. 3 is a diagram illustrating a code table used by an encoder, an encoding method, a decoder and a decoding method for a serializer/deserializer system according to an embodiment of the invention. Fig. 3 is a code table generated by taking M =10 as an example according to the above steps, wherein in the D code table, each 9-bit code word to be coded corresponds to a group of 10-bit code words of RD + and RD-, 247-bit code words to be coded with decimal data of 265 to 511 have RD + identical to that of the code word of RD-, and 247-bit code words to be coded with decimal data of 0 to 264 have RD + different from that of the code word of RD-, but the code word of RD + is the result of bit-wise negation of the code word of RD-. Similarly, in the K code table, except for the coded code word of the aligned K code with only RD-, the coded code words of RD + and RD-of the K code are different in decimal data, but the coded code word of RD + is the result of bit-wise inversion of the coded code word of RD-. Accordingly, to reduce ROM resources, the look-up table of the code table only has code words that store RD-.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a state transition of a running disparity value in an encoding method for a serializer/deserializer system according to an embodiment of the invention. Further, in embodiments designed with the temporary codeword D ≦ 0: when the temporary codeword is D =0, step S24 directly takes the temporary codeword as a coded codeword as an output, and the updated running disparity value is unchanged, next _ RD = pre _ RD, where next _ RD represents the updated running disparity value, and pre _ RD represents the current running disparity value; when the temporary codeword is D <0 and the running difference value is negative, step S24 outputs the result of bitwise negating the temporary codeword as a code word, and the updated running difference value is next _ RD = pre _ RD +2D ', where D' is the difference value of the code word; when the temporary codeword is D <0 and the run disparity value is positive, step S24 directly takes the temporary codeword as the encoded codeword as output, and the updated run disparity value is next _ RD = pre _ RD + 2D'. For example, when the current running disparity value RD = -1 and the temporary codeword is D = -1, the result of inverting the temporary codeword by bit is taken as a code word, and the code word is D' =1, so that the updated running disparity value is RD = + 1; and when the current operation difference value RD = -3 and the temporary code word is D = -2, the result of inverting the temporary code word by bit is taken as a code word, and the code word is D' =2, so that the updated operation difference value is RD = -1.
Conversely, in embodiments designed with the temporary codeword D ≧ 0: when the temporary codeword is D =0, step S24 directly takes the temporary codeword as a coded codeword as an output, and the updated running disparity value is unchanged, next _ RD = pre _ RD, where next _ RD represents the updated running disparity value, and pre _ RD represents the current running disparity value; when the temporary codeword is D >0 and the running difference value is positive, step S24 outputs the result of bitwise negating the temporary codeword as a code word, and the updated running difference value is next _ RD = pre _ RD +2D ', where D' is the difference value of the code word; when the temporary codeword is D >0 and the run disparity value is negative, step S24 directly takes the temporary codeword as the encoded codeword as output, and the updated run disparity value is next _ RD = pre _ RD + 2D'. As can be seen from the transition diagram of fig. 4, the running difference value is continuously updated with the encoding, and it is ensured that the number difference between 0 and 1 is always controlled between-3 and +3 in the whole bitstream, thereby ensuring the DC balance.
Referring to fig. 1 and 5, fig. 5 is a flowchart illustrating a decoding method for a serializer/deserializer system according to an embodiment of the invention. First, in step S51, the decoder 16 divides N ･ M-bit parallel data into N-way M-bit codewords to be decoded, from high to low. Then, in step S52, the decoder 16 acquires N ways of M-bit codewords to be decoded. In step S53, for each M-bit codeword to be decoded, the decoder 16 obtains an M-bit adjustment codeword according to the M-bit codeword to be decoded. Further, under the condition that the temporary code word is designed to be D less than or equal to 0, if the code word D to be decoded is greater than 0, the code word D is inverted according to bits to obtain an adjusting code word with D <0, otherwise, the adjusting code word is not processed. Through the part of the operation, the adjusting code word D is less than or equal to 0. This has the advantage that only the part of the code table with D ≦ 0 is needed to be used as the lookup table during decoding (i.e. only the code table with D ≦ 0 is implemented by logic gates), thereby saving a lot of hardware resources. Then, in step S24, for each path of M-bit adjusted code word through the lookup table of the code table, the decoder 16 finds out a corresponding (M-1) -bit code word, a 1-bit K-code indication signal and a 1-bit decoding error indication signal according to the M-bit adjusted code word, where the 1-bit K-code indication signal is associated with whether the decoded codeword is a K code or a D code, and the 1-bit decoding error indication signal corresponds to whether the M-bit adjusted code word exists in the lookup table of the code table, and if the lookup table of the code table does not exist, the 1-bit decoding error indication signal is high, and the 1-bit decoding error indication signal is low.
In summary, the encoding and decoding technical solution provided in the embodiments of the present invention has the following advantages: (1) the coding efficiency is high ((M-1)/M)%, and the bandwidth utilization rate of a serializer/deserializer system is improved; (2) the maximum run length of the D code and the common K code is (M-2), and the method is suitable for clock recovery of a receiving end; (3) special K codes for boundary synchronization can be designed, and the codes can not be concatenated with D codes and common K codes on the premise of error-free transmission, so that the correctness of boundary synchronization is ensured; (4) the code table mapping rule is optimized, 0 and 1 are distributed as intensively as possible, the simplest AND/OR formula obtained by simplifying the Carnot graph is simple, the realization of a logic gate is convenient, and the method is particularly suitable for application scenes with insufficient ROM resources; and (5) in the process of designing the D code and the common K code, any D >0 code word corresponding to the (M-1) bit input can be obtained by inverting the D <0 code word according to the bit, and by utilizing the characteristic, only the code word with the D less than or equal to 0 needs to be stored in the implementation process, so that a large amount of resources are saved.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (6)

1. An encoding method for a serializer/deserializer system, and characterized in that the encoding method comprises:
finding out a corresponding M-bit code word as a temporary code word according to an (M-1) -bit code word to be coded and a corresponding 1-bit K code indication signal through a lookup table for realizing a code table, wherein difference values of all M-bit code words in the lookup table are respectively 0, -1 or-2, or respectively 0, +1 or +2, M is an even number greater than or equal to 4, all M-bit code words in the lookup table comprise a plurality of D code words and a plurality of K code words, and all D code words with difference values of 0 in the lookup table do not comprise a plurality of M-bit code words with front M/2 bits being all 0 or 1 and rear M/2 bits being all 0 or 1; and
determining to use the temporary code word as a code word or use a result obtained by bitwise negation of the temporary code word as the code word according to the difference value of the temporary code word and the operation difference value, and updating the operation difference value according to the result; wherein the difference of the temporary codeword is given by a design in which the difference values of all M-bit codewords in the lookup table are 0, -1 or-2, respectivelyUnder the condition that the value is-1 or-2 and the operation difference value is negative, outputting the result of inverting the temporary code word according to the bit as the coding code word, otherwise, taking the temporary code word as the coding code word, wherein the updated operation difference value is the difference value of the previous operation difference value plus 2 times of the coding code word; in the look-up table, L0The M-bit D code words with difference value of 0 are arranged from large to small in decimal value and are equal to the decimal value (2)M-1-L0+1 to (2)M-1L of-1)0One-to-one correspondence of (M-1) -bit code words to be coded, L1The M-bit D code words with the difference value of-1 are arranged from large to small in decimal value and are matched with the decimal value (2)M-1-L0-L1+1 to (2)M-1-L0) L of1One-to-one correspondence of (M-1) -bit codewords to be encoded, and L2The M-bit D code words with the difference value of-2 are arranged from large to small in decimal value and are 0 to (L) with the decimal value2L of-1)2One-to-one correspondence of (M-1) -bit code words to be coded, wherein L0+L1+L2=2M-1。
2. The encoding method of claim 1, wherein x M-bit code words of the plurality of M-bit code words that differ by a value of-2 and are not selected as the longest Hamming distance of the plurality of D-code words are selected as x M-bit normal K code words of the lookup table, wherein 10 ≦ x ≦ 20; and an M-bit codeword "00 … 011 … 1" with first M/2 bits all 0 and last M/2 bits all 1 and "11 … 10100 … 0" with first (M/2) -1 bits all 1, M/2 th bit 0, and (M/2) +1 th bit 1 and other bits all 0 are selected as two boundary-aligned K codes of the lookup table.
3. An encoder for a serializer/deserializer system, and characterized by being configured to perform the encoding method of any one of claims 1-2.
4. A decoding method for a serializer/deserializer system, and characterized in that the decoding method comprises:
adjusting the M-bit code words to be decoded according to difference values of the M-bit code words to be decoded to generate M-bit adjusted code words, wherein M is an even number greater than or equal to 4, all the M-bit code words in a lookup table comprise a plurality of D code words and a plurality of K code words, and all the D code words with the difference value of 0 in the lookup table do not comprise a plurality of M-bit code words with the first M/2 bits being all 0 or 1 and the last M/2 bits being all 0 or 1; and
finding out a corresponding (M-1) -bit code word as a decoding code word according to the M-bit adjusting code word through the lookup table, and outputting a corresponding 1-bit K code indication signal and a corresponding 1-bit decoding error indication signal; when the difference values of all M-bit code words in the lookup table for realizing the code table are designed to be 0, -1 or-2 respectively, if the difference values of all M-bit code words to be decoded are +1 or +2, the result of bitwise negation of the M-bit code words to be decoded is taken as the adjustment code word, otherwise, the M-bit code words to be decoded are taken as the adjustment code word, when the difference values of all M-bit code words in the lookup table for realizing the code table are designed to be 0, +1 or +2 respectively, if the difference values of all M-bit code words to be decoded are-1 or-2, the result of bitwise negation of the M-bit code words to be decoded is taken as the adjustment code word, otherwise, the M-bit code words to be decoded are taken as the adjustment code word; in the look-up table, L0The M-bit D code words with the difference value of 0 are arranged from large to small in decimal value and are matched with the decimal value L0A (2)M-1-L0+1 to (2)M-1A one-to-one correspondence of (M-1) bit codewords of-1), L1The M-bit D code words with the difference value of-1 are arranged from large to small in decimal value and are matched with the decimal value (2)M-1-L0-L1+1 to (2)M-1-L0) L of1One-to-one correspondence of individual (M-1) -bit code words, and L2The M-bit D code words with the difference value of-2 are arranged from large to small in decimal value and are 0 to (L) with the decimal value2L of-1)2One-to-one correspondence of (M-1) -bit code words, where L0+L1+L2=2M-1。
5. The decoding method of claim 4, wherein the x M-bit code words of the plurality of M-bit code words that have a difference value of-2 and are not selected as the longest Hamming distance of the plurality of D-code words are selected as x M-bit normal K-code words of the lookup table, wherein 10 ≦ x ≦ 20; and an M-bit codeword "00 … 011 … 1" with first M/2 bits all 0 and last M/2 bits all 1 and "11 … 10100 … 0" with first (M/2) -1 bits all 1, M/2 th bit 0, and (M/2) +1 th bit 1 and other bits all 0 are selected as two boundary-aligned K codes of the lookup table.
6. A decoder for a serializer/deserializer system, and characterized by being configured to perform the decoding method of any one of claims 4-5.
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