WO2018040824A1

WO2018040824A1 - Data encoding method, data decoding method, devices, and data storage medium

Info

Publication number: WO2018040824A1
Application number: PCT/CN2017/095344
Authority: WO
Inventors: 吴雪松
Original assignee: 深圳市中兴微电子技术有限公司
Priority date: 2016-08-31
Filing date: 2017-07-31
Publication date: 2018-03-08
Also published as: CN107783922A

Abstract

A data encoding method, data decoding method, data encoding device, data codec device, and data storage medium. The encoding method comprises: receiving data to be encoded and from 4 QSGMII interfaces (S101); determining disparities of the 4 interfaces, respectively (S102); encoding, according to disparities of the respective interfaces, data to be encoded of the respective interfaces, and converting, from parallel to serial, the encoded data of the respective interfaces (S103).

Description

Data encoding method, data decoding method and device, and storage medium

Cross-reference to related applications

The present application is filed on the basis of the Chinese Patent Application No. PCT Application No.

Technical field

The present invention relates to communication technologies, and in particular, to a data encoding method, a data decoding method and apparatus, and a storage medium.

Background technique

4 Serial Gigabit Media Independent Interface (QSGMII), which is 4 serial Gigabit Media Independent Interfaces (GMII), using 4 channels of fewer pins. The physical layer (PHY, Physical Layer) with a port rate of 10/100/1000 is interconnected with the Media Access Contronl (MAC), and the QSGMII interface is a Gigabit (Gigabit) serial high-speed serializer/solution. Serializer (SERDES, SERializer/DESerializer) interface.

The traditional QSGMII scheme takes the transmitting end as an example. The transmitting end has 4 (one) channels, and each channel uses QSGMII to transmit 8 bits of data (that is, 8 bits of bit width data), and the 8 bit width data to be transmitted of each channel GMII is to be transmitted. , 8 bytes/10 bytes (B, Byte)/10B encoding in the order of channels 0, 1, 2, 3, that is, encoding 8 bit width data into 10 bit width data for transmission, wherein the input port The raw data per 8 bits can be divided into two parts: the lower 5 bits of data: EDCBA (set its decimal value is X) and the upper 3 bits of data: HGF (set its decimal value to Y), then the 8 bit data can be recorded as DXY. In addition, 8B/10B encoding is also used Up to 12 control characters can be used as the status indicator of the start of the frame in the transmission, the end of the frame, the idleness of the transmission, etc. Similar to the notation of the data characters, the control characters are generally recorded as K.X.Y. In the 8B/10B encoding, K28.1, K28.5, and K28.7 are used as control codes.

However, when each channel of the 4 channels needs to transmit 32-bit bit width data (also referred to as 32-bit data in this paper) through the GMII, it is necessary to press the 32-bit data to 0, 1, 2 for the 4 ports of each channel GMII. The order of the port numbers of 3 implements the 8B/10B encoding method for the 8-bit bit width data to be sent by each port, which results in a high processing frequency of each port, which affects the stability and reliability of the system.

Summary of the invention

In view of this, embodiments of the present invention are directed to providing a data encoding method, a data decoding method and apparatus, and a storage medium, which reduce the processing frequency of each port when the 8-bit GMII 32-bit data is 8B/10B encoded.

To achieve the above objective, the technical solution of the embodiment of the present invention is implemented as follows:

In a first aspect, an embodiment of the present invention provides a data encoding method, including: receiving 4-port data to be encoded from a QSGMII; determining a disparity value of each port in the 4-port; and determining, according to a disparity value of each port, respectively The data to be encoded of each port is encoded, and the encoded data of each port is subjected to parallel-to-serial conversion processing.

In the above solution, the determining the disparity value of each port in the four ports includes: determining a disparity value of each port according to a disparity value of a previous port corresponding to each port; The disparity value of the port is output to the next port of each port.

In the above solution, after receiving the 4-port to-be-coded data from the QSGMII, before determining the disparity value of each port in the 4-port, the method further includes: setting the control code of the port 0 in the 4-port by K28 Replace .5 with K28.1.

In a second aspect, an embodiment of the present invention provides a data decoding method, including: receiving encoded data, performing serial-to-parallel conversion on the encoded data, and converting the parallel-converted 4-way parallel Data, corresponding to the four ports sent to the QSGMII; determining the disparity value of each port in the four ports; decoding the encoded data according to the disparity value of each port, and obtaining the decoded of each port data.

In the above solution, after the encoded data is received, the encoded data is serial-to-parallel converted, and the four parallel data obtained after the serial-to-parallel conversion are respectively sent to the four ports of the QSGMII, and the four ports are determined. Before the disparity value of each port, the method further includes: when at least one of the encoded data of each port does not exist in the preset encoding table, the encoded data of each port is preset The direction is shifted by one bit until the encoded data of each port exists in the preset coding table.

In the above solution, after determining the disparity value of each port in the four ports, decoding the encoded data sent to the ports according to the disparity value of each port to obtain decoding of each port. Before the data, the method further includes:

When at least one of the disparity values of the ports does not exist in the preset value, the coded data of each port is shifted to a preset direction until the disparity values of the ports exist in the In the preset value.

In the above solution, after the encoded data sent to the ports is decoded according to the disparity value of each port, and the decoded data of each port is obtained, the method further includes:

The control code of the port 0 is replaced by K28.1 to K28.5;

If at least one of the control codes of the ports 1, 2, and 3 in the 4-port is not K28.1, or if at least one of the decoded data of each port does not exist in the preset coding table, return Performing a step of shifting the encoded data of each port to a preset direction.

In a third aspect, the embodiment of the present invention provides a data encoding apparatus, including: a first receiving module configured to receive 4-port to-be-coded data from the QSGMII; and a first determining module configured to determine each port in the 4-port The encoding module is configured to encode the data to be encoded of each port according to the disparity value of each port, and perform parallel-to-serial conversion processing on the encoded data of each port.

In the foregoing solution, the first determining module is configured to determine a disparity value of each port according to a disparity value of a previous port corresponding to each port, and output the disparity value of each port to The next port of each port.

In the above solution, the apparatus further includes: a first replacement module configured to: after receiving the 4-port to-be-coded data from the QSGMII, before determining the disparity value of each port in the 4-port, in the 4-port The control code for port 0 is replaced by K28.5 to K28.1.

In a fourth aspect, an embodiment of the present invention provides a data decoding apparatus, including: a second receiving module, configured to receive encoded data, perform serial-to-parallel conversion on the encoded data, and convert the serialized and converted data. The parallel data is corresponding to the four ports sent to the QSGMII; the second determining module is configured to determine the disparity value of each port in the four ports; and the decoding module is configured to send to the disparity value of each port according to the disparity value of each port The encoded data of each port is decoded to obtain the decoded data of each port.

In the above solution, the second determining module is configured to determine a disparity value of each port according to a disparity value of a previous port corresponding to each port, and output the disparity value of each port to The next port of each port.

In the above solution, the device further includes: a first mobile module configured to receive the encoded data, perform serial-to-parallel conversion on the encoded data, and send the four parallel data obtained by the serial-to-parallel conversion to the After determining the disparity value of each port in the 4 port, the port is encoded when at least one of the encoded data of each port does not exist in the preset encoding table before the 4 ports of the QSGMII are determined. After the data is shifted to the preset direction until the Each port encoded data is present in the preset encoding table.

In the above solution, the device further includes: a second mobility module, configured to send to each port according to the disparity value of each port after determining a disparity value of each port in the four ports After the encoded data is decoded, before the decoded data of each port is obtained, when at least one of the disparity values of the ports does not exist in the preset value, the encoded data of each port is forwarded to a preset direction. A shift operation is performed until the disparity values of the respective ports are present in the preset value.

In the above solution, the device further includes: a second replacement module, configured to perform decoding on the encoded data respectively sent to the ports according to the disparity value of each port, to obtain the decoded data of each port After that, the control code of the port 0 is replaced by K28.1 to K28.5, and the synchronization detection module is triggered; the synchronization detection module is configured to be the port 1 and 2 in the 4 port after being triggered. When at least one of the control codes of 3 is not K28.1, or when at least one of the decoded data of each port does not exist in the preset coding table, triggering the first mobile module to execute After each port is encoded, the data is shifted to a preset direction.

In a fifth aspect, an embodiment of the present invention provides a data encoding apparatus, including:

a memory for storing an executable program;

The data encoding method provided by the embodiment of the present invention is implemented when the processor is configured to execute the executable program stored in the memory.

In a sixth aspect, an embodiment of the present invention provides a data encoding apparatus, including:

a memory for storing an executable program;

The data decoding method provided by the embodiment of the present invention is implemented when the processor is configured to execute the executable program stored in the memory.

In a seventh aspect, an embodiment of the present invention provides a storage medium, where an executable program is stored, and when the executable program is executed by a processor, the data encoding method provided by the embodiment of the present invention is implemented.

An eighth aspect of the present invention provides a storage medium storing an executable program. The data decoding method provided by the embodiment of the present invention is implemented when the executable program is executed by the processor.

In the embodiment of the present invention, after receiving the 4-port to-be-coded data of the QSGMII, first, determine the disparity value of each port in the 4-port. After determining the disparity value of each port, each port is respectively determined according to the disparity value of each port. The coded data is encoded to obtain the encoded data of each port. That is, the received port 4 to be encoded data first calculates the disparity value of each port, so that, in the case where the disparity value of each port is known, By using the disparity value of each port, the data to be encoded of each port can be encoded at the same time, thereby realizing the process of parallel encoding of the data to be encoded by the 4-port, and improving the encoding speed of the data to be encoded, thereby reducing the 32-bit of the 4-channel GMII. The processing frequency of 8B/10B encoding is performed on each port of the data, which improves the coding efficiency, thereby improving the stability and reliability of the system.

DRAWINGS

1 is a schematic flowchart of a data encoding method according to an embodiment of the present invention;

2 is an optional flow chart of encoding 40-bit data in an embodiment of the present invention;

3 is a schematic flowchart of a data decoding method according to an embodiment of the present invention;

4 is an optional flow chart of decoding 40-bit data in an embodiment of the present invention;

5 is an optional flow chart of encoding and decoding 40-bit data according to an embodiment of the present invention;

6-1 is a schematic flowchart of an optional 40-bit data encoding according to an embodiment of the present invention;

FIG. 6-2 is an optional schematic flowchart of decoding 40-bit data according to an embodiment of the present invention;

7-1 is a schematic structural diagram of an optional data encoding apparatus according to an embodiment of the present invention;

7-2 is a schematic structural diagram of an optional data encoding apparatus according to an embodiment of the present invention;

8-1 is a schematic structural diagram of an optional data decoding apparatus according to an embodiment of the present invention;

FIG. 8-2 is a schematic structural diagram of a data decoding apparatus according to another embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings.

The embodiment of the invention provides a data encoding method, which can be applied to logic devices such as Field Programmable Gate Array (FPGA) and logic circuit (IC), and can also be applied to a central processing unit. (CPU, Central Processing Unit) and digital signal processing (DSP, Digital Signal Processing) are implemented, and the present invention is not specifically limited herein.

FIG. 1 is a schematic flowchart of a data encoding method according to an embodiment of the present invention. The traffic of the channel shown in FIG. 1 is 125 megabytes (M) bytes, that is, an octets of 125 M, and data is input to the channel. In the process of encoding processing, when the control character of channel 0 is K28.5, the exchange is K28.1; for every 8 bits of data, the encoded data of 10 bits is output after 8B/10B encoding, physical medium access (PMA, Physical) The Media) service interface outputs 10 bits of data per channel, and a total of 500 megabytes of code combination (each code combination is a 10-bit block). The data is sent from low to high. The order is sent, that is, bit 0 is sent first.

The 0-channel 10 bit control code K28.5 is replaced with K28.1, so that the receiving end can determine the data position of port 0 according to K28.1 on the serial stream, and then convert the 10-bit encoded data into serial. The code stream is sent to the receiving end, the decoding process of the receiving end and the inverse process of the encoding process of the transmitting end.

As shown in Figure 1, the method includes:

S101: Receive 4-port to-be-coded data from the QSGMII.

Wherein, taking the FPGA as an example, the transmitting end located in the FPGA sends a configuration code when the power is restarted, and sends an idle (idle) code or a low power idle lpidle code when idle, and sends the data to be encoded when the GMII has data; The encoded data includes a data code and a control code, wherein when the data code is transmitted The key signal is 0; when the control code is sent, the key signal is 1. It should be noted that, among the above four ports, the control codes of the ports 0-3 are all K28.5.

For example, FIG. 2 is an optional flow chart of encoding 40-bit data according to an embodiment of the present invention; as shown in FIG. 2, port 0 receives 8-bit data TXD<7:0> of GMII, and Port1 receives GMII's 8-bit data TXD<7:0>, Port2 receives GMII's 8-bit data TXD<7:0>, and Port3 receives GMII's 8-bit data TXD<7:0>.

In order to locate the coded data, in an optional embodiment, after S101, before S102, the method may include:

Change the control code of port 0 in port 4 from K28.5 to K28.1.

In FIG. 2, after receiving the 8 bits of data to be encoded, each port of the transmitting end inputs an encoding process, and marks the 7th to the 0th bits of the 8-bit data to be encoded of each port as HGFEDCBA in turn, and then ports the port. The control code K28.5 of 0 is replaced by K28.1. Thus, in the 4-port, the control code of port 0 is K28.1, and the control code of port 1-3 is K28.5. Then, the receiving end passes the control code K28. .5 can find the data corresponding to port 0.

S102: Determine a disparity value of each port in the four ports.

The disparity value of each port may include: +2, -2, 0; each disparity value corresponds to a 10-bit encoded data. Therefore, in order to obtain 10-bit encoded data, the disparity value of each port must be determined first;

In order to determine the disparity value of each port, in an optional embodiment, S102 may include:

The disparity value of the previous port corresponding to each port of the four ports is output to each port; the disparity value of each port is determined according to the disparity value of the previous port corresponding to each port.

Here, the previous port of each port is: a port adjacent to the serial number of the port and having a serial number before the port.

For example, in the 4-port, when the 32-bit data to be encoded of the input port 0 is the first-encoded data (that is, the 32-bit data input to the 4-port for the first time in the data to be encoded), the disparity value of the port 0 may be +2 or 0, output the disparity value of port 0 to port 1.

When the 32-bit data to be encoded of port 0 is not the first-encoded data, the corresponding previous port of port 0 is port 3, and the disparity value of the previous group of data to be encoded in port 3 is output to port 0; according to port 3 The disparity value is used to determine the disparity value of port 0, and the disparity value of port 0 is output to port 1;

According to the disparity value of port 0, determine the disparity value of port 1, output the disparity value of port 1 to port 2, determine the disparity value of port 2 according to the disparity value of port 1, and output the disparity value of port 2 to the port. 3. Determine the disparity value of port 3 according to the disparity value of port 2. For example, if port 1 is used as the example and the disparity value of port 0 is -2, the disparity value of port 1 is corresponding to the purpose of DC balance. In the case of +2, -2, 0, it is determined that the disparity value of port 1 is +2, and the disparity value of port 1 is output to port 2.

In this way, the disparity value of each port is determined.

S103: Code the data to be encoded of each port according to the disparity value of each port, and perform parallel-to-serial conversion processing on the data encoded by each port.

In the foregoing FIG. 2, in the process of performing 8B/10B encoding, according to the disparity value of each port, 8 bit of data to be encoded is searched from a preset encoding table, and a 10-bit encoding corresponding to the disparity value of the port is obtained. The post data is represented as abcdeifghj in Figure 2, thus obtaining the encoded data of each port, outputting 10 bits of encoded data, and the serial/deserializer (SERDES, SERializer/DESerializer) will encode 40 bits of parallel encoded data. The data is converted into serial data, and 5G bits of data are transmitted to the receiving end through the PMA (Physical Medium Attachment) service interface in the order of ports 0, 1, 2, and 3. Thus, the data encoding is completed.

In the data encoding method provided by the embodiment of the present invention, after receiving the 4-port to-be-coded data of the QSGMII, the data encoding apparatus first determines the disparity value of each port in the 4-port, and after determining the disparity value of each port, according to each The disparity value of the port encodes the data to be encoded of each port to obtain the encoded data of each port. That is, the data encoding device calculates the disparity value of each port for the received 4-port data to be encoded, so that Knowing the disparity value of each port, the disparity value of each port can be used to encode the data to be encoded of each port at the same time, thereby implementing the process of parallel encoding of the 4-port data to be encoded, and reducing the coding of the data to be encoded for each port. The speed, then, reduces the processing frequency of 8B/10B encoding for each port of the 4-channel GMII 32-bit data, which improves the coding efficiency and thus improves the stability and reliability of the system.

Based on the same inventive concept, the embodiment of the present invention further provides a data decoding method, and FIG. 3 is a schematic flowchart of a data decoding method according to an embodiment of the present invention. As shown in FIG. 3, the method includes:

S301: Receive encoded data, perform serial-to-parallel conversion on the encoded data, and send 4-way parallel data obtained by serial-to-parallel conversion to 4 ports of QSGMII;

The receiving end receives the encoded data of the transmitting end, serially converts the serial 40-bit encoded data, and obtains 4 parallel data to be sent to 4 ports of the QSGMII, wherein each port receives 10 bits of encoded data;

For example, FIG. 4 is an optional flow chart of decoding 40-bit data in the embodiment of the present invention. As shown in FIG. 4, the PMA interface receives the encoded data at a speed of 5 Gbps and sends the data to the 4-port, each port. Receive the encoded 10bit data, where Port0 is port 0, receive 10bit data of GMII 0 1 2 3 4 5 6 7 8 9, Port1 is port 1, receive 10bit data of GMII 10 11 12 13 14 15 16 17 18 19 Port2 is port 2, receives 10 bits of data of GMII 20 21 22 23 24 25 26 27 28 29, Port 3 is port 3, receives 10 bits of data of GMII 30 31 32 33 34 35 36 37 38 39;

In order to align the 40-bit encoded data with the ports, in an alternative embodiment, S301 Then, before S302, the method may include: when at least one of the encoded data of each port does not exist in the preset encoding table, the data encoded by each port is shifted to a preset direction until each port is encoded. The data is stored in the preset encoding table.

In FIG. 4, after each port receives 10 bits of encoded data, the comma sequence is aligned at a possible position. Here, it is detected whether the 10-bit encoded data of each port exists in the preset coding table, if all exist. The position of the 40-bit encoded data has been aligned with each port. If at least one 10-bit encoded data does not exist in the preset encoding table, the position of the encoded data after 40 bits is not aligned with each port. The 40-bit encoded data is shifted to the preset direction, and then continues to detect whether the 10-bit encoded data of each port exists in the preset encoding table until the data of each port is encoded in the preset In the coding table; in the case where it is determined that the position of the 40-bit encoded data has been aligned with each port, the 10-bit data 0 1 2 3 4 5 6 7 8 9 is aligned with the port 0, and the 10-bit data is 10 11 12 13 14 15 16 17 18 19 Align with port 1, align 10bit data 20 21 22 23 24 25 26 27 28 29 with port 2, and 10 bit data 30 31 32 33 34 35 36 37 38 39 with Port 3 is aligned.

Wherein, the preset direction may be leftward or rightward.

S302: Determine a disparity value of each port in the four ports.

In order to determine the disparity value of each port, in an optional embodiment, S302 may include:

For example, in the 4-port, when the 40-bit encoded data is the first data to be decoded (that is, the first received 40-bit data), the disparity value of port 0 can be +2 or 0, and the disparity value of port 0 is output to the port. 1; When the 40-bit data to be encoded is not the first data to be decoded, the corresponding previous port of port 0 is port 3, and the disparity of the decoded data of the previous group in port 3 is The value is output to port 0. According to the disparity value of port 3, the disparity value of port 0 is determined, and the disparity value of port 0 is output to port 1. According to the disparity value of port 0, the disparity value of port 1 is determined, and port 1 is determined. The disparity value is output to port 2. According to the disparity value of port 1, the disparity value of port 2 is determined, the disparity value of port 2 is output to port 3, and the disparity value of port 3 is determined according to the disparity value of port 2; for example For example, port 1 is used as the example, and the disparity value of port 0 is -2. Therefore, for the purpose of DC balance, the disparity value of port 1 is determined to be port 1 in the case of +2, -2, 0. The disparity value is +2, and the disparity value of port 1 is output to port 2.

In this way, the disparity value of each port is determined.

After determining the disparity value of each port, in order to further determine whether the position of the 40-bit encoded data is aligned with each port, in an optional embodiment, after S302, before S303, the method may include: If at least one of the disparity values does not exist in the preset value, the data encoded by each port is shifted to a preset direction until the disparity value of each port exists in the preset value.

The preset value may include: +2, -2, 0; determining whether the determined disparity value of each port is in a preset value, and when the disparity value of each port exists in the preset value, the 40 bit is specified. The position of the encoded data has been aligned with each port. If the disparity value of at least one port does not exist in the preset encoding table, it indicates that the position of the encoded data after 40 bits is not aligned with each port, then The 40-bit encoded data is shifted in the preset direction, and then continues to detect whether the disparity values of the ports exist in the preset values until the disparity values of the ports exist in the preset values;

After determining that the position of the 40-bit encoded data has been aligned with each port, the 10-bit data 0 1 2 3 4 5 6 7 8 9 is aligned with the port 0, and the 10-bit data is 10 11 12 13 14 15 16 17 18 19 Align with port 1, align 10bit data 20 21 22 23 24 25 26 27 28 29 with port 2, and align 10 bit data 30 31 32 33 34 35 36 37 38 39 with port 3.

S303: Decode the encoded data according to the disparity value of each port, and obtain the decoded data of each port.

In the above FIG. 4, the physical decoding sublayer (PCS, Physical Coding Sublayer) of the receiving end performs the 8B/10B decoding process, and searches for the 10-bit encoding from the preset encoding table according to the disparity value of each port. Data, the 8-bit decoded data corresponding to the disparity value of the port is represented by HGFEDCBA in FIG. 4, so that the decoded data of each port is obtained, and the 8-bit decoded data is subjected to carrier detection processing. 8bit decoded data + control word + carrier detection, and the obtained decoded data (7 6 5 4 3 2 1 0 in Figure 4) is sent to Port0, Port1, Port2, Port3 of the GMII interface, so that the GMII interface can receive Up to 4 RXD<7:0>.

Before the decoded data is formed into a frame format, it is necessary to determine the correctness of the decoded 8-bit data. In order to determine the correctness of the decoded 8-bit data, the decoded data is continuously detected synchronously. In an optional embodiment, After S303, the method may include:

Replace the control code of port 0 with K28.1 to K28.5;

When at least one of the control codes of the ports 1, 2, and 3 in the 4-port is not K28.1, or when at least one of the decoded data of each port does not exist in the preset coding table, the execution returns each port. The step of shifting the encoded data to a preset direction.

In the above data encoding method, after determining the disparity value of each port, in order to determine the data of port 0, the control code of port 0 is replaced by K28.1 to K28.5, then in the process of decoding, the control code can be After finding the 10-bit encoded data corresponding to port 0, the four 10-bit encoded data are decoded separately. After the decoding is completed, the control code of port 0 is replaced by K28.5 to K28.1, and then the port 1-3 is detected. If it is detected that at least one of the control codes of the ports 1, 2, and 3 is not K28.1, or if at least one of the decoded data of each port is not present in the preset coding table, the decoding is performed. In case of error, it is necessary to return to the step of performing the shift operation of the data encoded by each port in the preset direction, and re-input the data bits of each port. The lines are aligned and then decoded to ensure the correctness of the data decoding.

In the data decoding method provided by the embodiment of the present invention, after receiving the 4-port encoded data of the QSGMII, the data decoding device first determines the disparity value of each port in the 4-port, and after determining the disparity value of each port, according to each The disparity value of the port decodes the encoded data of each port to obtain the decoded data of each port. That is, the data decoding device calculates the disparity value of each port for the received 4-port data to be encoded, so that Knowing the disparity value of each port, the disparity value of each port can be used to decode the encoded data of each port at the same time, thereby realizing the process of parallel decoding of the data after 4-port encoding, and then reducing the 32-bit data of the 4-channel GMII. The processing frequency of 8B/10B decoding is performed on each port, which improves the decoding efficiency, thereby improving the stability and reliability of the system.

The following examples are provided to illustrate one or more embodiments of the above data encoding and decoding methods;

FIG. 5 is an optional flow chart of encoding and decoding 40-bit data according to an embodiment of the present invention; as shown in FIG. 5, at the transmitting end (recorded as send), four parallel ports Port0 are received from GMII. The 8bit data to be encoded is distributed to Port0, Port1, Port2, and Port3 in the encoder, and the encoded data is encoded into four 10-bit data and serially converted by SERDES to obtain 40-bit encoded data. Before being sent to the receiving end, the SERDES is passed. The serial-to-parallel conversion is performed to obtain four 10-bit encoded data, which are distributed to Port0, Port1, Port2, and Port3 in the decoder.

6-1 is an optional flowchart of encoding 40-bit data in the embodiment of the present invention. As shown in FIG. 6-1, the data encoding method may include:

S601: Send a control code or data according to the GMII receiving and link status.

When the sender is powered on and restarts, the configuration code is sent. When idle, the idle code or lpidle code is sent. When the GMII has data, the data code is sent. When the data code is sent, the key signal is 0. When the control code is sent, the key signal is 1.

S602: The sending end determines whether the current port is Port0, and if it is Port0, it processes to S603. If it is another port, it is processed to S604;

S603: The sender replaces the control code K28.5 with K28.1;

S604: The transmitting end calculates the disparity value of the local port according to the disparity value of the previous port, and outputs the disparity value of the local port to the next port to perform 8B/10B encoding.

S605: The transmitting end combines the 4-bit 10-bit encoded data into 40-bit encoded data.

S606: The transmitting end transmits the 40-bit code to the receiving end by parallel-to-serial conversion into a 5G SERDES differential signal.

FIG. 6-2 is an optional flowchart of decoding 40-bit data according to an embodiment of the present invention. As shown in FIG. 6-2, the data decoding method may include:

S607: The receiving end receives the differential signal from the 5G SERDES line, and converts the serial to 40-bit data.

S608: The receiving end judges whether the encoded data is an illegal code stream (the encoded data does not exist in the preset code table, that is, the illegal code stream), and if yes, performs a 1-bit shift operation, if not, Then go to S610;

S609: The receiving end moves the 40-bit encoded data (right shift) by one bit.

S610: The receiving end distributes 10 bits of data to 4 ports in order.

S611: The receiving end calculates the disparity value of the port according to the disparity value of the previous port. The calculated disparity value is sent to the next port; the disparity value calculated by Port0 is sent to Port1, the disparity value calculated by Port1 is sent to Port2, the disparity value calculated by Port2 is sent to Port3, and the disparity value calculated by Port3 is sent to Port0. 8B/10B decoding;

S612: The receiving end interprets whether the 8-bit code stream is illegal, or whether the disparity value is wrong. If the code stream is illegal or the disparity value is wrong, go to S608, otherwise, execute S613;

S613: The receiving end determines the current port. If it is Port0, it goes to S614 for processing. If the current port is another port, it goes to S615 for processing.

S614: The receiving end replaces the control code K28.1 with K28.5;

S615: The receiving end performs synchronization state detection, and forms the received data into a frame format.

S616: The receiving end determines that if it is not synchronized with the transmitting end, or detects the control code K28.1, it proceeds to S612; otherwise, S617 is executed.

S617: Send the received data frame to the GMII interface.

Based on the same inventive concept, an embodiment of the present invention provides a data encoding apparatus, and FIG. 7-1 is an optional structural diagram of a data encoding apparatus according to an embodiment of the present invention. As shown in FIG. 7-1, the apparatus includes : a first receiving module 71, a first determining module 72 and an encoding module 73;

The first receiving module 71 is configured to receive the 4-port to-be-coded data from the 4QSGMII. The first determining module 72 is configured to determine the disparity value of each port in the 4-port. The encoding module 73 is configured to be based on the disparity value of each port. And encoding the data to be encoded of each port separately, and performing parallel-to-serial conversion processing on the encoded data of each port.

In order to determine the disparity value of each port, in an optional embodiment, the first determining module 71 is configured to output the disparity value of the previous port corresponding to each port of the four ports to each port. Determine the disparity value of each port based on the disparity value of the previous port corresponding to each port.

In order to locate the data to be encoded, in an optional embodiment, the apparatus further includes: a first replacement module configured to determine each port of the 4 port after receiving the 4-port to-be-coded data from the QSGMII Before the disparity value, replace the control code of port 0 in port 4 from K28.5 to K28.1.

In a practical application, the first receiving module 71, the first determining module 72, and the encoding module 73 can be configured by a central processing unit (CPU), a microprocessor (MPU, a microprocessor unit), and a dedicated integrated device located at the transmitting end device. ASIC (Application Specific Integrated Circuit) or FPGA implementation.

For example, FIG. 7-2 is an optional structural diagram of a data encoding apparatus according to an embodiment of the present invention. The intent, as shown in Figure 7-2, includes at least one processor 74, memory 76, at least one memory 76, and a network interface 77. The various components in the data encoding device are coupled together by a bus system 75. It will be appreciated that the bus system 75 is used to implement connection communication between these components. In addition to the data bus, the bus system 75 includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 75 in Figure 7-2.

It will be appreciated that memory 76 can be either volatile memory or non-volatile memory, and can include both volatile and nonvolatile memory. The non-volatile memory may be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), or an Erasable Programmable Read (EPROM). Only Memory), Electrically Erasable Programmable Read-Only Memory (EEPROM). The memory 76 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

The memory 76 in the embodiment of the present invention is used to store various types of data to support the operation of the data encoding apparatus. A program implementing the data encoding method of the embodiment of the present invention may be included in the application 761.

The method disclosed in the above embodiments of the present invention may be applied to the processor 74 or implemented by the processor 74. Processor 74 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method may be completed by an integrated logic circuit of hardware in the processor 74 or an instruction in the form of software. The processor 74 described above can be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like. The processor 74 can implement or perform the various methods, steps, and logic blocks disclosed in the embodiments of the present invention. A general purpose processor can be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiment of the present invention may be directly implemented as a hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium located in memory 76, and processor 74 reads the letter in memory 76. And complete the steps of the foregoing method in combination with its hardware.

In an exemplary embodiment, the data encoding device may be an ASIC (Application Specific Integrated Circuit), a DSP, a Programmable Logic Device (PLD), or a Complex Programmable Logic Device (CPLD). ), an FPGA, a general purpose processor, a controller, a microcontroller (Micro Controller Unit), a microprocessor, or other electronic component implementation for performing the aforementioned data encoding method.

Based on the same inventive concept, an embodiment of the present invention provides a data decoding apparatus, and FIG. 8-1 is an optional structural diagram of a data decoding apparatus according to an embodiment of the present invention. As shown in FIG. 8-1, the apparatus includes : a second receiving module 81, a second determining module 82 and a decoding module 83;

The second receiving module 81 is configured to receive the encoded data, perform serial-to-parallel conversion on the encoded data, and send the four parallel data obtained by the serial-to-parallel conversion to the four ports of the 4QSGMII, respectively; the second determining module 82 The decoding module 83 is configured to decode the encoded data according to the disparity value of each port to obtain the decoded data of each port.

In an optional embodiment, the second determining module 82 is configured to output the disparity value of the previous port corresponding to each port of the four ports to each of the ports. Ports; determine the disparity value of each port based on the disparity value of the previous port corresponding to each port.

In an optional embodiment, the apparatus further includes: a first mobile module configured to receive the encoded data and perform serial-to-parallel conversion on the encoded data, After the four parallel data obtained by the serial-to-parallel conversion are respectively sent to the four ports of the QSGMII, before determining the disparity value of each port in the four ports, at least one of the encoded data of each port does not exist in the preset encoding. In the table, the data encoded by each port is shifted to a preset direction until the data encoded by each port exists in the preset coding table.

After determining the disparity value of each port, in order to further determine whether the position of the 40-bit encoded data is aligned with each port, in an optional embodiment, the apparatus further includes: a second mobile module configured to determine After the disparity value of each port in the four ports, the encoded data is decoded according to the disparity value of each port, and at least one of the disparity values of each port does not exist in the preset value before the decoded data of each port is obtained. In the middle, the data encoded by each port is shifted to a preset direction until the disparity value of each port exists in the preset value.

Before the decoded data is formed into a frame format, it is necessary to determine the correctness of the decoded 8-bit data. In order to determine the correctness of the decoded 8-bit data, the decoded data is continuously detected synchronously. In an optional embodiment, The device further includes: a second replacement module and a synchronization detection module;

The second replacement module is configured to decode the encoded data according to the disparity value of each port, and obtain the decoded data of each port, and then replace the control code of port 0 with K28.5 to K28.1, and The synchronization detection module is triggered, and the synchronization detection module is configured to: at least one of the control codes of the ports 1, 2, and 3 in the 4-port is not K28.1 after being triggered, or at least one of the decoded data of each port When it does not exist in the preset coding table, the first mobile module is triggered to perform a shift operation of the data encoded by each port in a preset direction.

In practical applications, the second receiving module 81, the second determining module 82, and the decoding module 83 can all be implemented by a CPU, an MPU, an ASIC, or an FPGA located at the receiving end.

For example, referring to FIG. 8-2, FIG. 8-2 is a schematic structural diagram of a data decoding apparatus according to another embodiment of the present invention, and a data decoding apparatus. The data decoding apparatus shown in FIG. 8-2 includes at least one processor 84, a memory 86, and a network interface 87. The various components in the data decoding device are coupled together by a bus system 85. As can be appreciated, bus system 85 is used to implement connection communication between these components. The bus system 85 includes a power bus, a control bus, and a status signal bus in addition to the data bus. However, for the sake of clarity, the various buses are labeled as the bus system in Figure 8-2. System 85.

The memory 86 in the embodiment of the present invention is used to store various types of data to support the operation of the data decoding apparatus. A program for implementing the data decoding method of the embodiment of the present invention may be included in the application 861.

The method disclosed in the above embodiments of the present invention may be applied to the processor 84 or implemented by the processor 84. Processor 84 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method may be completed by an integrated logic circuit of hardware in the processor 84 or an instruction in the form of software. The processor 84 described above can be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like.

This embodiment describes a computer readable medium, which may be a ROM (eg, a read only memory, a FLASH memory, a transfer device, etc.), a magnetic storage medium (eg, a magnetic tape, a disk drive, etc.), an optical storage medium (eg, a CD- ROM, DVD-ROM, paper card, paper tape, etc.) and other well-known types of program memory; computer-readable medium storing computer-executable instructions that, when executed, cause at least one processor to perform the foregoing as shown in FIG. The data encoding method or the data decoding method shown in FIG.

In the embodiment of the present invention, after receiving the 4-port to-be-coded data of the QSGMII, first, determine the disparity value of each port in the 4-port. After determining the disparity value of each port, each port is respectively determined according to the disparity value of each port. The data to be encoded is encoded to obtain the encoded data of each port. That is to say, the data encoding device first calculates the disparity value of each port for the received 4-port data to be encoded, so that the discardity value of each port is known. Then, the disparity value of each port can be used to encode the data to be encoded of each port at the same time, thereby implementing the process of parallel encoding of the 4-port data to be encoded, and reducing the encoding speed of the data to be encoded by each port, then reducing the speed of 4 The 32-bit data of the channel GMII performs the processing frequency of 8B/10B encoding for each port, which improves the coding efficiency, thereby improving the stability and reliability of the system.

The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not It is to be understood that those skilled in the art are susceptible to variations and substitutions within the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Industrial applicability

The embodiment of the present invention discloses a data encoding and decoding method, including: receiving 4-port to-be-coded data from the QSGMII; determining a disparity value of each port in the 4-port; and respectively performing the port according to the disparity value of each port. The data to be encoded is encoded, and the data encoded by each port is subjected to parallel-to-serial conversion processing. The embodiment of the invention also discloses a data encoding and decoding device and a storage medium. The embodiment of the invention can reduce the processing frequency of each port when the 32-bit data of the 4-channel GMII is 8B/10B, and provides stability and reliability of the system.

Claims

A data encoding method comprising:

Receiving data to be encoded corresponding to 4 ports of the 4 serial Gigabit media independent interface QSGMII;

Determining an inequality disparity value of each port in the four ports;

The data to be encoded of each port is encoded according to the disparity value of each port, and the encoded data of each port is subjected to parallel-to-serial conversion processing.
The method of claim 1, wherein the determining a disparity value of each of the four ports comprises:

Determining a disparity value of each port according to a disparity value of a previous port corresponding to each port;

And outputting the disparity value of each port to the next port of each port.
The method of claim 1, wherein after receiving the 4-port to-be-encoded data from the QSGMII, before determining the disparity value of each of the four ports, the method comprises:

The control code of port 0 in the 4-port is replaced by K28.5 to K28.1.
A data decoding method includes:

Receiving the encoded data, performing serial-to-parallel conversion on the encoded data, and converting the 4-way parallel data obtained by serial-to-parallel conversion to four ports of the 4 serial Gigabit media independent interface QSGMII;

Determining an inequality disparity value of each port in the four ports;

Decoding the encoded data sent to each port according to the disparity value of each port to obtain decoded data of each port.
The method of claim 4, wherein the determining a disparity value of each of the four ports comprises:

Determining a disparity value of each port according to a disparity value of a previous port corresponding to each port;

And outputting the disparity value of each port to the next port of each port.
The method of claim 4, wherein before determining the disparity value of each of the four ports, the method further comprises:

When at least one of the encoded data of each port does not exist in the preset encoding table, the encoded data of each port is moved by one bit in a preset direction until the encoded data of each port Both exist in the preset coding table.
The method according to claim 4, after determining the disparity value of each port in the four ports, decoding the encoded data sent to the ports according to the disparity value of each port, and obtaining Before the decoded data of each port, the method further includes:

When at least one of the disparity values of the ports does not exist in the preset value, the coded data of each port is shifted to a preset direction until the disparity values of the ports exist in the In the preset value.
The method according to claim 6, wherein the method further comprises: after decoding the encoded data sent to the ports according to the disparity value of each port, and obtaining the decoded data of each port, the method further include:

The control code of the port 0 is replaced by K28.1 to K28.5;

If at least one of the control codes of the ports 1, 2, and 3 in the 4-port is not K28.1, or if at least one of the decoded data of each port does not exist in the preset coding table, return Performing a step of shifting the encoded data of each port to a preset direction.
A data encoding device comprising:

a first receiving module configured to receive 4-port data to be encoded from a 4-serial Gigabit Media Independent Interface QSGMII;

a first determining module, configured to determine an inequality disparity value of each port in the four ports;

The encoding module is configured to encode the data to be encoded of each port according to the disparity value of each port, and perform parallel-to-serial conversion processing on the encoded data of each port.
The apparatus according to claim 9, wherein

The first determining module is configured to determine a disparity value of each port according to a disparity value of a previous port corresponding to each port, and output a disparity value of each port to the port Next port.
The apparatus of claim 9 wherein said apparatus further comprises:

a first replacement module, configured to: after receiving the 4-port to-be-coded data from the QSGMII, replace the control code of the port 0 in the 4-port by K28.5 before determining the disparity value of each port in the 4-port K28.1.
A data decoding device comprising:

The second receiving module is configured to receive the encoded data, perform serial-to-parallel conversion on the encoded data, and convert the 4-way parallel data obtained by serial-to-parallel conversion to the 4 serial Gigabit media independent interface QSGMII 4 Port

a second determining module, configured to determine an inequality disparity value of each port in the four ports;

The decoding module is configured to decode the encoded data sent to each port according to the disparity value of each port, and obtain the decoded data of each port.
The device according to claim 12, wherein the second determining module is configured to determine a disparity value of each port according to a disparity value of a previous port corresponding to each port; The disparity value of the port is output to the next port of each port.
The device of claim 12, wherein the device further comprises:

a first mobile module configured to receive encoded data and perform stringing on the encoded data And converting, after the four parallel data obtained by the serial-to-parallel conversion are respectively sent to the four ports of the QSGMII, before determining the disparity value of each port in the four ports, at least the encoded data of each port is When not existing in the preset coding table, the data encoded by each port is shifted to a preset direction until the data encoded by each port exists in the preset coding table.
The device of claim 12, wherein the device further comprises:

a second mobile module, configured to: after determining the disparity value of each port, decoding the encoded data sent to each port according to the disparity value of each port, and obtaining the decoded by each port Before the data, when at least one of the disparity values of the ports does not exist in the preset value, the encoded data of each port is shifted to a preset direction until the disparity value of each port is Both exist in the preset value.
The apparatus of claim 14 wherein said apparatus further comprises:

The second replacement module is configured to decode the encoded data according to the disparity value of each port, and obtain the control code of the port 0 by using the K28.1 after obtaining the decoded data of each port. K28.5, and trigger the synchronization detection module;

The synchronization detecting module is configured to, when triggered, when at least one of the control codes of the ports 1, 2, and 3 in the 4-port is not K28.1, or at least the decoded data of each port When there is a code table that does not exist in the preset, the first mobile module is triggered to perform the shift operation on the encoded data of each port in a preset direction.
A data encoding device comprising:

a memory for storing an executable program;

The processor, configured to execute the executable program stored in the memory, implements the data encoding method of any one of claims 1 to 3.
A data encoding device comprising:

a memory for storing an executable program;

The data decoding method according to any one of claims 4 to 8 is implemented when the processor is configured to execute the executable program stored in the memory.
A storage medium storing an executable program, the executable program being executed by a processor to implement the data encoding method according to any one of claims 1 to 3.
A storage medium storing an executable program, the executable program being executed by a processor to implement the data decoding method according to any one of claims 4 to 8.