WO2007036128A1

WO2007036128A1 - A bts-bsc interface and a method for detecting the interface

Info

Publication number: WO2007036128A1
Application number: PCT/CN2006/002263
Authority: WO
Inventors: Kai Wen
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2005-09-29
Filing date: 2006-09-01
Publication date: 2007-04-05
Also published as: CN1852510A; CN100539492C

Abstract

A base station(BTS)-base station controller(BSC) interface includes: BTS-side interface module, including a BTS-side high level data link control(HDLC) unit connected with a BTS-side E1 transceiver, the BTS-side HDLC unit used for encapsulating and de-encapsulating the HDLC frame data, the BTS-side E1 transceiver used for transmitting and receiving the HDLC frame data; the BSC-side interface module, including a BSC-side HDLC unit connected with a BSC-side E1 transceiver, the BSC-side HDLC unit used for encapsulating and de-encapsulating the HDLC frame data, the BSC-side E1 transceiver used for transmitting and receiving the HDLC frame data; and a transmission module connected between the BTS-side E1 transceiver and the BSC-side E1 transceiver, used for transmitting HDLC frame data between the BTS-side and the BSC-side, wherein one of the BTS-side HDLC unit and the BSC-side HDLC unit could generate any frame. A method for detecting the BTS-BSC interface is disclosed in the invention. The BTS-BSC interface provided by the invention has a better testability.

Description

Base station - base station controller interface and method for detecting the same

The present invention relates to a base station subsystem (BSS), and more particularly to an interface between a base station (BTS) and a base station controller (BSC) in a BSS and a method for detecting the interface. Background of the invention

BSS usually includes BTS and BSC. Commonly, BTS side equipment and BSC side equipment can be divided into central processing unit (CPU) direct processing equipment and CPU external equipment. Generally, CPU direct processing equipment is directly controlled by CPU and can be compared. Flexible processing, suitable for extended functions, and CPU external devices can only perform predetermined processing, and it is not convenient to flexibly expand functions.

The current BSS often implements high-level data link control (HDLC) frame format data transmission between the BTS and the BSC through the BTS-BSC interface. A typical HDLC frame includes six fields from front to back: at least 8 The start flag ( OF ) of the bit, contains an octal number with a value of 0x7E; an 8-bit or 16-bit destination address (DA); an 8-bit or 16-bit control field; an optional information field, if the information exists, The length of the information field must be an integer multiple of 8; a 16-bit or 32-bit check field (CRC); an 8-bit end flag (CF).

The role of the CRC field is to detect error retransmission. After receiving the HDLC frame, the receiver can use the CRC-CCITT algorithm to calculate the data in the address field, the control field and the information field. If the result is equal to the value in the CRC field, Then the frame has no CRC error, otherwise the frame has a CRC error. If the receiver detects that a certain HDLC frame has a CRC error, the cause of the CRC error may include one or more of the following: the sender error, for example, the sender calculates the CRC field incorrectly, or does not fill in the CRC field; This may involve the HDLC frame being transmitted during transmission All devices and connections between devices; Receiver error, for example, the CRC field is incorrect when the receiver detects the CRC field.

There may be a frame loss error in the HDLC frame received by the receiver. That is, there is an OF field in the HDLC frame and no CF field, or the OF field has 7 or more "0bl" in front of the CF field. If the receiver detects a frame loss error in an HDLC frame, the cause of the frame loss error may include one or more of the following: a sender error, such as the sender does not fill in the CF domain; a transmission error, which may involve the HDLC. The connection between all devices and devices that the frame passes during transmission; the receiver error, such as the receiver detection error.

1 is a structural diagram of a prior art BTS-BSC interface. The prior art BTS-BSC interface 100 includes: a BTS side interface module 101 including an HDLC unit 131 and an E1 transceiver 141; and an HDLC unit 132 and an E1. The BSC side interface module 102 of the transceiver 142; the transmission module 103 for communication between the BTS side interface module 101 and the BSC side interface module 102.

The HDLC unit 131 and the E1 transceiver 141 of the BTS side interface module 101 are implemented by the BTS side CPU external device, and the HDLC unit 132 and the E1 transceiver 142 of the BSC side interface module 102 are implemented by the BSC side CPU external device.

The BTS side HDLC unit 131 is configured to receive data from the upper layer of the BTS side interface module 101. The data occupies an address field, a control domain, and an information field in the HDLC frame, and the HDLC unit 131 encapsulates the data into HDLC frames and performs pulse modulation coding ( PCM), the encoded PCM code is transmitted to the E1 transceiver 141; the HDLC unit 131 is further configured to receive the PCM code from the E1 transceiver 141, and extract the address domain, the control domain, and the information domain from the decoded HDLC frame. The data is sent to the upper layer of the BTS side interface module 101. The HDLC unit 131 further has a test function, for example, detecting and counting whether the received HDLC frame has a CRC error and whether there is a frame loss error.

The BTS side E1 transceiver 141 is configured to receive the PCM code from the HDLC unit 131. The code is encoded as an HDB3 code and transmitted to the E1 transceiver 142 through the transmission module 103. The E1 transceiver 141 is further configured to receive the HDB3 code from the E1 transceiver 142 transmitted through the transmission module 103, decode it into a PCM code, and transmit it to the PCM code. HDLC unit 131.

The BSC-side HDLC unit 132 is configured to receive data from an upper layer of the BSC-side interface module 102. The data occupies an address field, a control domain, and an information domain in an HDLC frame, and the HDLC unit 132 encapsulates the data into an HDLC frame and performs pulse modulation coding. Transmitting the encoded PCM code to the E1 transceiver 142; the HDLC unit 132 is further configured to receive the PCM code from the E1 transceiver 142, and extract the address domain, the control domain, and the information domain data from the decoded HDLC frame to The upper layer of the BSC side interface module 102; the HDLC unit 132 also has a test function, for example, detecting and counting whether the received HDLC frame has a CRC error and whether there is a frame loss error.

The E1 transceiver 142 is configured to receive the PCM code from the HDLC unit 132, encode it into the HDB3 code, and transmit it to the E1 transceiver 141 through the transmission module 103. The E1 transceiver 142 is further configured to receive the E1 transceiver transmitted through the transmission module 103. The HDB3 code of the device 141 is decoded into a PCM code and transmitted to the HDLC unit 132.

In common, the communication link supported by the E1 transceiver using time division multiplexing (TDM) is divided into 32 time slots, and the data sent and received by the HDLC unit may occupy only part of the time slot of the E1 transceiver. In this case, HDLC When the unit receives data from the E1 transceiver, it only extracts the data on the part of the time slot it occupies.

In current practical applications, the HDLC units on the BTS side and the BSC side are usually implemented by a communication controller as a CPU external device, such as a serial communication controller (SCC) of Motorola MPC860, etc., of these communication controllers. The common feature is that it can only provide fixed transmission and reception and test functions. It is difficult to flexibly expand. For example, the current HDLC unit can only detect and count whether there are CRC errors or frame loss errors in the received HDLC frames, but these problems are formed. The reason is difficult to locate. In fact, the production of these errors It may be related to the following three aspects: The sender HDLC unit is incorrect. For example, the sending HDLC unit calculates the CRC field incorrectly, or does not fill in the CF field. The transmission process is incorrect, that is, the device connected between the sending HDLC unit and the receiving HDLC unit. And the connection error between the devices; the HDLC unit of the receiving party is wrong, for example, the HDLC unit of the receiving party calculates the CRC domain error. The prior art BTS-BSC interface must separately detect the above three aspects by means of a dedicated detecting device to locate the problem, which results in poor testability and high detection cost of the existing BTS-BSC interface. Summary of the invention

In view of this, it is an object of the present invention to provide a BTS-BSC interface which has better testability.

It is still another object of the present invention to provide a method of detecting a BTS-BSC interface capable of detecting a BTS-BSC interface.

According to an aspect of the above object, the present invention provides a base station (BTS)-base station controller (BSC) interface, comprising:

The BTS side interface module includes an interconnected BTS side high layer data link control (HDLC) unit and a BTS side E1 transceiver, and the BTS side HDLC unit is configured to encapsulate and decapsulate HDLC frame data, and the BTS side E1 transceiver is used for transmitting and receiving HDLC frame data;

The BSC side interface module includes an interconnected BSC side HDLC unit and a BSC side E1 transceiver, and the BSC side HDLC unit is configured to encapsulate and decapsulate HDLC frame data, and the BSC side E1 transceiver is configured to send and receive HDLC frame data;

a transmission module connected between the BTS side E1 transceiver and the BSC side E1 transceiver, the transmission module is configured to transmit HDLC frame data between the BTS side and the BSC side,

among them

One can generate arbitrary frames, The BTS side HDLC unit is a direct processing device of its side CPU and can generate an arbitrary frame.

The BTS side interface module further includes a transparent transmission unit connected between the BTS side HDLC unit and the BTS side E1 transceiver, the transparent transmission unit is configured to be on the BTS side HDLC unit and the BTS side E1 HDLC frame data is transparently transmitted between transceivers.

The HDC unit on the BSC side is a direct processing device of the side CPU and can generate an arbitrary frame.

The BSC side interface module further includes a transparent transmission unit connected between the BSC side HDLC unit and the BSC side E1 transceiver, the transparent transmission unit is configured to be on the BSC side HDLC unit and the BSC side E1 HDLC frame data is transparently transmitted between transceivers.

According to another aspect of the above object, the present invention also provides a method of detecting a BTS-BSC interface, comprising:

A. The HDLC unit on the BTS side sequentially transmits the HDLC test frame X to the BSC side HDLC unit through the BTS side E1 transceiver, the transmission module, and the BSC side E1 transceiver, and the BSC side HDLC unit detects whether the received HDLC test frame X' has an error. If yes, go to step B, otherwise confirm that the interface is correct.

B. The HDC unit on the BSC side stores the received HDLC test frame X', and the HDLC unit on the BTS side generates the same HDLC check frame X' as the HDLC test frame X', and sequentially passes through the BTS side E1 transceiver, the transmission module, and the BSC side. The E1 transceiver transmits the HDLC check frame X' to the BSC side HDLC unit, and the BSC side HDLC unit compares the received HDLC check frame X" Whether it is the same as the saved HDLC test frame X', if yes, it is confirmed that the BTS side HDLC unit is incorrect, otherwise it is confirmed that the other parts of the interface other than the BTS side HDLC unit are incorrect.

The HDLC test frame X is transparently transmitted to the BTS side E1 transceiver by the BTS side HDLC unit through the BTS side transparent transmission unit.

The HDC check frame X' is transparently transmitted to the BTS side E1 transceiver by the BTS side HDLC unit through the BTS side transparent transmission unit.

The error is a check field CRC error or a frame loss error.

The invention further provides a method for detecting a BTS-BSC interface, comprising:

A. The HDC unit on the BSC side sequentially transmits the HDLC test frame Y to the HDLC unit on the BTS side through the B1 side E1 transceiver, the transmission module, and the BTS side E1 transceiver, and the HDLC unit on the BTS side detects whether the received HDLC test frame Y' has an error. If yes, go to step B, otherwise confirm that the interface is correct.

B. The HDLC unit on the BTS side stores the received HDLC test frame Y', and the HDLC unit on the BSC side generates the same HDLC check frame Υ' as the HDLC test frame Y', and sequentially passes through the BSC side E1 transceiver, the transmission module, and the BTS side. The E1 transceiver transmits the HDLC check frame Υ' to the BTS side HDLC unit, and the BTS side HDLC unit compares whether the received HDLC check frame Y" is the same as the saved HDLC test frame Y', and if yes, confirms the BSC side. The HDLC unit is incorrect, otherwise it is confirmed that the interface other than the BSC side HDLC unit is incorrect.

The HDC test frame Y is transparently transmitted to the BSC side E1 transceiver by the BSC side HDLC unit through the BSC side transparent transmission unit.

The HDSC check frame Y' is transparently transmitted to the BSC side E1 transceiver by the BSC side HDLC unit through the BSC side transparent transmission unit.

It can be seen that in the BTS-BSC interface provided by the present invention, due to the BTS side and the BSC side At least one of the HDLC units can generate an arbitrary frame. Therefore, when the receiving party detects an erroneous HDLC frame, the sending HDLC unit can generate and send the same check frame to the receiving HDLC unit, and the receiving HDLC unit. The specific device that caused the HDLC frame error can be determined by comparing the erroneous HDLC frame with the received check frame. Since the entire test flow of the method of detecting the interface can be performed without using a dedicated detection device, the detection cost is low. ' Brief description of the drawing

1 is a structural diagram of a prior art BTS-BSC interface.

2 is a structural diagram of a BTS-BSC interface according to Embodiment 1 of the present invention.

FIG. 3 is a structural diagram of a BTS-BSC interface according to Embodiment 2 of the present invention.

4 is a structural diagram of a BTS-BSC interface according to Embodiment 3 of the present invention. Mode for carrying out the invention

The core idea of the present invention is to replace the HDLC unit in the prior art with an HDLC unit capable of generating an arbitrary frame on either or both sides of the BTS side or the BSC side of the BTS-BSC interface.

The present invention will be further described in detail below with reference to the accompanying drawings.

The first embodiment: On the BTS side of the present embodiment, the HDLC unit that implements the device directly by the current CPU and can generate any HDLC frame is used instead of the HDLC unit in the prior art.

2 is a structural diagram of a BTS-BSC interface according to an embodiment of the present invention. The BTS-BSC interface 200 of the first embodiment of the present invention includes: a BTS side interface module 201 including an E1 transceiver 141 and an HDLC unit 261; HDLC unit 132 and BSC of E1 transceiver 142 The side interface module 102; a transmission module 103 for communication between the BTS side interface module 201 and the BSC side interface module 102.

The E1 transceiver 141 of the BTS side interface module 201 is implemented by a BTS side CPU external device, and the HDLC unit 261 is implemented by a BTS side CPU direct processing device. The BTS side interface module 201 may further include a transparent transmission unit 251 implemented by the CPU external device for transparently transmitting data. It may also be said that the transparent transmission unit 251 can be implemented as an HDLC unit 261 implemented by the CPU direct processing device and externally by the CPU. The device implements a transmission channel between the E1 transceivers 141, which can function to communicate with the BTS side CPU and external devices. For the BSC side, the HDLC unit 132 and the E1 transceiver 142 of the BSC side interface module 102 are still implemented by the BSC side CPU external devices as compared with the prior art, and their functions and connections are not changed.

The HDLC unit 261 is configured to receive data from an upper layer of the BTS side interface module 201. The data occupies an address field, a control field, and an information field in an HDLC frame, and the HDLC unit 261 encapsulates the data into an HDLC frame and performs pulse modulation coding. The obtained PCM code is transmitted to the transparent transmission unit 251. The HDLC unit 261 is further configured to receive the PCM code from the transparent transmission unit 251, and extract the address domain, the control domain, and the information domain data from the decoded HDLC frame and send the data to the BTS side interface. The upper layer of the module 201; the HDLC unit further has a flexible test function, and can generate an arbitrary frame in addition to performing detection, counting whether the received HDLC frame has a CRC error, or whether there is a frame loss error.

The transparent transmission unit 251 is configured to receive the PCM code from the HDLC unit 261 and send it to the E1 transceiver 141. The transparent transmission unit 251 is further configured to receive the PCM code from the E1 transceiver 141 and send it to the HDLC unit 261 for transmission and reception in the HDLC unit 261. In the case where the data only occupies part of the time slot of the E1 transceiver 141, when the transparent transmission module 251 receives data from the E1 transceiver, only the data on the partial time slots occupied by the HDLC unit 261 is extracted.

The E1 transceiver 141 is configured to receive the PCM code from the transparent transmission unit 251 and encode it as The HDB3 code is transmitted to the El transceiver 142 through the transmission module 103. The E1 transceiver 141 is further configured to receive the HDB3 code from the E1 transceiver 142 transmitted through the transmission module 103, decode it into a PCM code, and transmit it to the transparent transmission unit 251. .

The detection of the BTS-BSC interface of the present embodiment by using the HDLC frame includes the CRC error detection and the frame loss error detection. The following is the specific process of the two detections. The case where the BTS side interface module 201 includes the transparent transmission module 251 is taken as an example.

The CRC error detection of the BTS-BSC interface of this embodiment by using the HDLC frame includes steps 11 to 14:

11. The HDLC unit 261 on the BTS side receives the data from the upper layer of the local interface module 201 and encapsulates it into the HDLC test frame A, and sequentially transmits it to the HDLC through the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, and the E1 transceiver 142. Unit 132;

12. The HDLC unit 132 on the BSC side detects whether the received HDLC test frame A is an HDLC test frame Α with a CRC error, and if yes, performs step 13 and subsequent steps; otherwise, the interface is confirmed to be correct, and the process ends;

13. The HDLC unit 132 saves the CRC error HDLC test frame A', and the BTS side HDLC unit 261 acquires and generates the same HDLC check frame Α' as the HDLC test frame A', and sequentially passes through the transparent transmission units 251, E1. The transceiver 141, the transmission module 103 and the E1 transceiver 142 transmit it to the HDLC unit 132;

14. The BSC-side HDLC unit 132 compares whether the received HDLC check frame A" is the same as the HDLC test frame A' it holds. If the two are the same, the BTS side HDLC unit 261 is confirmed to be erroneous, and the transparent transmission unit 251 and the E1 transceiver are confirmed. 141. The transmission module 103, the E1 transceiver 142, and the HDLC unit 132 and the connection between them are correct; if the two are different, the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, the E1 transceiver 142, and the HDLC are confirmed. One or more of the units 132 or a connection between them is incorrect.

The frame loss error detection is performed on the BTS-BSC interface of the embodiment by using the HDLC frame. Including steps 21 ~ 24:

The HDLC unit 261 on the BTS side receives the data from the upper layer of the interface module 201 of the present side and encapsulates it into the HDLC test frame B, and sequentially transmits it to the HDLC through the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, and the E1 transceiver 142. Unit 132;

22. The HDLC unit 132 on the BSC side detects whether the received HDLC test frame B is an HDLC test frame with frame loss error Β', and if yes, performs step 23 and subsequent steps. Otherwise, the interface is confirmed to be correct, and the process ends. ;

The HDLC unit 132 saves the HDLC test frame Β with the frame loss error, and the BTS side HDLC unit 261 acquires and generates the same HDLC check frame Β' as the HDLC test frame B', and sequentially passes through the transparent transmission units 251 and E1. The transceiver 141, the transmission module 103 and the E1 transceiver 142 transmit it to the HDLC unit 132;

24. The HDLC unit 132 on the BSC side compares whether the HDLC check frame B received by the HDLC check frame B is the same as the HDLC test frame B that is saved. If the two are the same, the BTS side HDLC unit 261 is confirmed to be erroneous, and the transparent transmission unit 251 and E1 are confirmed to transmit and receive. The 141, the transmission module 103, the E1 transceiver 142 and the HDLC unit 132 and the connection between them are correct; if they are different, the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, the E1 transceiver 142 and One or more of the HDLC units 132 or a connection between them is erroneous.

Although in this embodiment, the BTS side HDLC unit is implemented by the BTS side CPU direct processing device, it should be noted that the implementation of the BTS side HDLC unit is not limited thereto, but should include a more diverse implementation. For example, the BTS side HDLC unit can be implemented by a CPU external processing device capable of generating an arbitrary frame, such as an integrated circuit having this function.

The second embodiment of the present invention is to replace the HDLC unit in the prior art with the HDLC unit that is implemented by the direct processing device of the current CPU and can generate any HDLC frame.

3 is a structural diagram of a BTS-BSC interface according to Embodiment 2 of the present invention, which is an embodiment of the present invention. The BTS-BSC interface 300 includes a BTS side interface module 101 including an HDLC unit 131 and an El transceiver 141, a BSC side interface module 302 including an E1 transceiver 142 and an HDLC unit 362, and a BTS side interface module 101. A transmission module 103 that communicates with the BSC side interface module 302.

The E1 transceiver 142 of the BSC side interface module 302 is implemented by the BSC side CPU external device, and the HDLC unit 362 is implemented by the BSC side CPU direct processing device. The BSC side interface module 302 may further include a transparent transmission unit 352 implemented by the CPU external device for transparently transmitting data. It may also be said that the transparent transmission unit 352 can be implemented as an HDLC unit 362 implemented by the CPU direct processing device and externally by the CPU. The device implements a transmission channel between the E1 transceivers 142, which can function to communicate with the CPU and external devices. For the BTS side, the HDLC unit 131 and the E1 transceiver 141 of the BTS side interface module 101 are still implemented by the BTS side CPU external devices, and their functions and connection relationships are not changed as compared with the prior art.

The HDLC unit 362 is configured to receive data from the upper layer of the BSC side interface module 302. The data occupies an address field, a control field, and an information field in the HDLC frame, and the HDLC unit 362 encapsulates the data into an HDLC frame and performs pulse modulation coding. The obtained PCM code is transmitted to the transparent transmission unit 352. The HDLC unit 362 is further configured to receive the PCM code from the transparent transmission unit 352, and extract the address domain, the control domain, and the information domain data from the decoded HDLC frame and send the data to the BSC side interface. The upper layer of the module 302; the HDLC unit further has a flexible test function, and can generate an arbitrary frame in addition to performing detection, counting whether the received HDLC frame has a CRC error, whether it is a frame loss or not.

The transparent transmission unit 352 is configured to receive the PCM code from the HDLC unit 362 and transmit it to the E1 transceiver 142; the transparent transmission unit 352 is further configured to receive the PCM code from the E1 transceiver 142 and send it to the HDLC unit 362, in the HDLC unit 362. When the transmitted and received data only occupies part of the time slot of the E1 transceiver 142, when the transparent transmission module 251 receives data from the E1 transceiver, Only the data on the partial time slots occupied by the HDLC unit 362 is extracted.

The E1 transceiver 142 is configured to receive the PCM code from the transparent transmission unit 352, encode it into the HDB3 code, and send it to the E1 transceiver 141 through the transmission module 103. The E1 transceiver 142 is further configured to receive the transmission from the E1 through the transmission module 103. The HDB3 code of the transceiver 141 is decoded into a PCM code and transmitted to the transparent transmission unit 352.

The detection of the BTS-BSC interface of the present embodiment by using the HDLC frame includes the CRC error detection and the frame loss error detection. The following is the specific process of the two detections. The case where the BSC side interface module 302 includes the transparent transmission module 352 is taken as an example.

The CRC error detection of the BTS-BSC interface of the present embodiment by using the HDLC frame includes steps 31 - 34:

The HDLC unit 362 on the BSC side receives the data from the upper layer of the interface module 302 of the present side and encapsulates it into an HDLC test frame C, and sequentially transmits it to the HDLC through the transparent transmission unit 352, the E1 transceiver 142, the transmission module 103, and the E1 transceiver 141. Unit 131;

32. The HDLC unit 131 on the BTS side detects whether the received HDLC test frame C is an HDLC test frame C′ with a CRC error. If yes, step 33 and subsequent steps are performed to confirm that the interface is correct, and the process ends.

The HDLC unit 131 stores the HDLC test frame C' with the CRC error, and the HDLC unit 362 of the BSC side acquires and generates the same HDLC check frame C as the HDLC test frame C, and sequentially passes through the transparent transmission unit 352 and the E1 transceiver 142. , the transmission module 103 and the E1 transceiver 141 transmit it to the HDLC unit 131;

34. The BTS side HDLC unit 131 compares whether the received HDLC check frame C" is the same as the HDLC test frame C' it holds. If the two are the same, the BSC side HDLC unit 362 is confirmed to be erroneous, and the transparent transmission unit 352 and the E1 transceiver are confirmed. 142. The transmission module 103, the E1 transceiver 141, and the HDLC unit 131 and the connection between them are correct; if the two are different, the transparent transmission unit 352, the E1 transceiver 142, the transmission module 103, the E1 transceiver 141, and One or more of the HDLC units 131 or a connection between them is erroneous.

Performing frame loss error detection on the BTS-BSC interface of this embodiment by using the HDLC frame includes the following steps 41 - 44:

41. The HDLC unit 362 on the BSC side receives the data from the upper layer of the local interface module 302 and encapsulates it into an HDLC test frame D, and sequentially transmits it to the HDLC through the transparent transmission unit 352, the E1 transceiver 142, the transmission module 103, and the E1 transceiver 141. Unit 131;

42. The HDLC unit 131 on the BTS side detects whether the received HDLC test frame D is an HDLC test frame D′ with a frame loss error. If yes, step 43 and subsequent steps are performed. Otherwise, the interface is confirmed to be correct, and the process ends. ;

43. The HDLC unit 131 saves the HDLC test frame D′ with the frame loss error, and the BSC side HDLC unit 362 acquires and generates the same HDLC check frame D′ as the HDLC test frame D′, and sequentially passes through the transparent transmission units 352 and E1. The transceiver 142, the transmission module 103 and the E1 transceiver 141 transmit it to the HDLC unit 131;

44. The BTS side HDLC unit 131 compares whether the received HDLC check frame D" is the same as the HDLC test frame D' it holds. If the two are the same, the BSC side HDLC unit 362 is confirmed to be erroneous, and the transparent transmission unit 352 and the E1 transceiver are confirmed. 142. The transmission module 103, the E1 transceiver 141, and the HDLC unit 131 and the connection between them are correct; if they are different, the transparent transmission unit 352, the E1 transceiver 142, the transmission module 103, the E1 transceiver 141, and the HDLC are confirmed. One or more of the units 131 or a connection between them is erroneous.

Although in this embodiment, the BSC-side HDLC unit is implemented by the BSC-side CPU direct processing device, it should be noted that the implementation manner of the BSC-side HDLC unit is not limited thereto, but should include a more diverse implementation manner. For example, the BSC side HDLC unit can be implemented by a CPU external processing device capable of generating an arbitrary frame, such as an integrated circuit having this function.

Embodiment 3: On the BTS side of the present embodiment, the HDLC unit implemented by the direct processing device of the current CPU and capable of generating an arbitrary frame is substituted for the HDLC unit in the prior art; On the BSC side, the HDLC unit implemented in the direct processing device of the CPU is used to replace the HDLC unit in the prior art.

4 is a structural diagram of a BTS-BSC interface according to Embodiment 3 of the present invention. The BTS-BSC interface 400 of the third embodiment of the present invention includes: a BTS side interface module 201 including an E1 transceiver 141 and an HDLC unit 261; The BSC side interface module 302 of the transceiver 142 and the HDLC unit 362; and the transmission module 103 for communication between the BTS side interface module 201 and the BSC side interface module 302.

The E1 transceiver 141 of the BTS side interface module 201 is implemented by a BTS side CPU external device, and the HDLC unit 261 is implemented by a BTS side CPU direct processing device. The BTS side interface module 201 may further include a transparent transmission unit 251 implemented by the CPU external device for transparently transmitting data. It may also be said that the transparent transmission unit 251 can be implemented as an HDLC unit 261 implemented by the CPU direct processing device and externally by the CPU. The device implements a transmission channel between the E1 transceivers 141, which can function to communicate with the CPU and external devices.

The HDLC unit 261 is configured to receive data from an upper layer of the BTS side interface module 201. The data occupies an address field, a control field, and an information field in an HDLC frame, and the HDLC unit 261 encapsulates the data into an HDLC frame and performs pulse modulation coding. The obtained PCM code is transmitted to the transparent transmission unit 251. The HDLC unit 261 is further configured to receive the PCM code from the transparent transmission unit 251, and extract the address domain, the control domain, and the information domain data from the decoded HDLC frame and send the data to the BTS side interface. The upper layer of the module 201; the HDLC unit further has a flexible test function, and can generate an arbitrary frame in addition to performing detection, counting whether the received HDLC frame has a CRC error, whether it is a frame loss or not.

The transparent transmission unit 251 is configured to receive the PCM code from the HDLC unit 261 and send it to the E1 transceiver 141. The transparent transmission unit 251 is further configured to receive the PCM code from the E1 transceiver 141 and send it to the HDLC unit 261 for transmission and reception in the HDLC unit 261. When the data only occupies part of the time slot of the E1 transceiver 141, when the transparent transmission module 251 receives data from the E1 transceiver, only The data on a portion of the time slot occupied by the HDLC unit 261 is extracted.

The E1 transceiver 141 is configured to receive the PCM code from the transparent transmission unit 251, encode it into the HDB3 code, and send it to the E1 transceiver 142 through the transmission module 103. The E1 transceiver 141 is further configured to receive the transmission from the E1 through the transmission module 103. The HDB3 code of the transceiver 142 is decoded into a PCM code and transmitted to the transparent transmission unit 251.

Correspondingly, the E1 transceiver 142 of the BSC side interface module 302 is implemented by the BSC side CPU external device, and the HDLC unit 362 is implemented by the BSC side CPU direct processing device. The BSC-side interface module 302 may further include a transparent transmission unit 352 implemented by the CPU external device for transparently transmitting data, in the case that the data sent and received by the HDLC unit 362 is only occupied by the E1 transceiver 142. The transparent transmission unit 352 can exist as a transmission channel between the HDLC unit 362 implemented by the CPU direct processing device and the E1 transceiver 142 implemented by the CPU external device, and can function to communicate with the CPU and the external device.

The transparent transmission unit 352 is configured to receive the PCM code from the HDLC unit 362 and transmit it to the E1 transceiver 142; the transparent transmission unit 352 is further configured to receive the PCM code from the E1 transceiver 142 and send it to the HDLC unit 362, in the HDLC unit 362. When the transmitted and received data only occupies part of the time slot of the E1 transceiver 142, when the transparent transmission module 251 receives data from the E1 transceiver, only the data on the partial time slots occupied by the HDLC unit 362 is extracted. The El transceiver 142 is configured to receive the PCM code from the transparent transmission unit 352, encode it into the HDB3 code, and send it to the E1 transceiver 141 through the transmission module 103. The E1 transceiver 142 is further configured to receive the transmission from the E1 through the transmission module 103. The HDB3 code of the transceiver 141 is decoded into a PCM code and transmitted to the transparent transmission unit 352.

In this embodiment, the BTS side interface module 201 and the BSC side interface module 302

- The BSC interface 400 performs detection. The following is an example in which the BTS side is used as the sender, and the case where the BSC side is the sender is similar.

The detection of the BTS-BSC interface of the present embodiment by using the HDLC frame includes the CRC error detection and the frame loss error detection. The following is the specific process of the two detections. The BTS side interface module 201 includes the transparent transmission module 251 and the BSC side interface module. 302 includes the case of the transparent transmission module 352 as an example.

The CRC error detection of the BTS-BSC interface of this embodiment by using the HDLC frame includes steps 51-54:

The HDLC unit 261 on the BTS side receives the data from the upper layer of the interface module 201 of the present side and encapsulates it into the HDLC test frame E, and sequentially passes through the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, the E1 transceiver 142, and the transparent transmission module. 352 transmits it to the HDLC unit 362;

52. The HDLC unit 362 on the BSC side detects whether the received HDLC test frame E is an HDLC test frame E′ with a CRC error. If yes, step 53 and subsequent steps are performed. Otherwise, the interface is confirmed to be correct, and the process ends.

The HDLC unit 362 saves the CRC error HDLC test frame Ε', and the BTS side HDLC unit 261 acquires and generates the same HDLC check frame Ε' as the HDLC test frame E', and sequentially passes through the transparent transmission unit 251 and the E1 transceiver. 141, the transmission module 103, the E1 transceiver 142 and the transparent transmission unit 352 transfer it to the HDLC unit 362;

54. The BSC side HDLC unit 362 compares the received HDLC check frame E" with its guarantee Whether the stored HDLC test frames E' are the same, if the two are the same, the BTS side HDLC unit 261 is confirmed to be erroneous, and the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, the E1 transceiver 142, the transparent transmission unit 352, and the HDLC are confirmed. The unit 362 and the connection between them are correct; if the two are different, one or more of the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, the E1 transceiver 142, the transparent transmission unit 352, and the HDLC unit 362 are confirmed. Or the connection between them is wrong.

Performing frame loss error detection on the BTS-BSC interface of this embodiment by using the HDLC frame includes steps 61-64:

61. The HDLC unit 261 on the BTS side receives the data from the upper layer of the local interface module 201 and encapsulates it into an HDLC test frame F, and sequentially passes through the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, the E1 transceiver 142, and the transparent transmission unit. 352 transmits it to the HDLC unit 362;

62. The HDLC unit 362 on the BSC side detects whether the received HDLC test frame F is an HDLC test frame F with a frame loss error. If yes, step 63 and subsequent steps are performed. Otherwise, the interface is confirmed to be correct, and the process ends.

63. The HDLC unit 362 saves the HDLC test frame F with the frame loss error, and the HDLC unit 261 of the BTS side acquires and generates the same HDLC check frame F as the HDLC test frame F′, and sequentially passes through the transparent transmission unit 251 and the E1 transceiver. 141, the transmission module 103, the E1 transceiver 142 and the transparent transmission unit 352 transfer it to the HDLC unit 362;

64. The HDLC unit 362 on the BSC side compares whether the received HDLC face detection frame F" is the same as the HDLC test frame F stored therein. If the two are the same, the BTS side HDLC unit 261 is confirmed to be erroneous, and the transparent transmission unit 251 and E1 are confirmed to transmit and receive. 141, the transmission module 103, the E1 transceiver 142, the transparent transmission unit 352, and the HDLC unit 362 and the connection between them are correct; if the two are different, the transparent transmission unit 251, the E1 transceiver 141, the transmission module 103, One or more of the E1 transceiver 142 and the HDLC unit 132 or a connection between them is erroneous. Although in this embodiment, the BTS side HDLC unit and the BSC side HDLC unit are respectively implemented by their side CPU direct processing devices, it should be noted that the implementation manners of the BTS side HDLC unit and the BSC side HDLC unit are not limited thereto, but A more diverse implementation should be included, such as the BTS side HDLC unit and the BSC side HDLC unit can be implemented by a CPU external processing device capable of generating an arbitrary frame, such as an integrated circuit having this function.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims

Claim

1. A base station BTS - base station controller BSC interface, including:

The BTS side interface module includes an interconnected BTS side high layer data link control HDLC unit and a BTS side E1 transceiver, and the BTS side HDLC unit is configured to encapsulate and decapsulate HDLC frame data, and the BTS side E1 transceiver is configured to send and receive HDLC frames. data;

A transmission module connected between the BTS side E1 transceiver and the BSC side E1 transceiver, the transmission module is configured to transmit HDLC frame data between the BTS side and the BSC side, and one can generate an arbitrary frame.

2. The BTS-BSC interface according to claim 1, wherein the BTS side HDLC unit is a direct CPU processing device of the side CPU and is capable of generating an arbitrary frame.

The BTS-BSC interface according to claim 1, wherein the BSC-side HDLC unit is a direct CPU processing device of the side CPU and is capable of generating an arbitrary frame.

The BTS-BSC interface according to claim 2, wherein the BSC-side HDLC unit is a side CPU directly processing device and is capable of generating an arbitrary frame. The BSC side interface module further includes a transparent transmission unit connected between the BSC side HDLC unit and the BSC side E1 transceiver, the transparent transmission unit is configured to be on the BSC side HDLC unit and the BSC side E1 HDLC frame data is transparently transmitted between transceivers.

5. A method of detecting a BTS-BSC interface, comprising:

B. The HDLC unit on the BSC side stores the received HDLC test frame X', and the HDLC unit on the BTS side generates the same HDLC check frame X' as the HDLC test frame X', and sequentially passes through the BTS side E1 transceiver, the transmission module, and the BSC side. The E1 transceiver transmits the HDLC check frame X' to the BSC side HDLC unit, and the BSC side HDLC unit compares whether the received HDLC check frame X" is the same as the saved HDLC test frame X', and if so, confirms the BTS side. The HDLC unit is incorrect, otherwise it is confirmed that the interface other than the BTS side HDLC unit is incorrect.

The method of claim 5, wherein the BTS side HDLC unit transparently transmits the HDLC test frame X to the BTS side E1 transceiver through a BTS side transparent transmission unit.

The method according to claim 5 or 6, wherein the error is a check field CRC error or a frame loss error.

8. A method of detecting a BTS-BSC interface, comprising:

A. The HDC unit on the BSC side sequentially transmits the HDLC test frame Y to the BTS side HDLC unit through the BSC side E1 transceiver, the transmission module, and the BTS side E1 transceiver, and the BTS side HDLC. The unit detects whether there is an error in the received HDLC test frame Y', and if yes, performs step B, otherwise confirm that the interface is correct;

B. The HDLC unit of the BTS side stores the received HDLC test frame Υ', and the HDLC unit of the BSC side generates the same HDLC check frame Υ' as the HDLC test frame Y', and sequentially passes through the BSC side E1 transceiver, the transmission module, and the BTS side. The E1 transceiver transmits the HDLC check frame Υ' to the BTS side HDLC unit, and the BTS side HDLC unit compares whether the received HDLC check frame Y" is the same as the saved HDLC test frame Y', and if yes, confirms the BSC side. The HDLC unit is incorrect, otherwise it is confirmed that the interface other than the BSC side HDLC unit is incorrect.

The method of claim 8, wherein the BSC-side HDLC unit transparently transmits the HDLC test frame Y to the BSC-side E1 transceiver through a BSC-side transparent transmission unit.

10. The method of claim 8 or 9, wherein the error is a CRC error or a frame loss error.