CN109390397A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN109390397A
CN109390397A CN201710655459.9A CN201710655459A CN109390397A CN 109390397 A CN109390397 A CN 109390397A CN 201710655459 A CN201710655459 A CN 201710655459A CN 109390397 A CN109390397 A CN 109390397A
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China
Prior art keywords
fin structure
area
semiconductor element
layer
fin
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CN201710655459.9A
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CN109390397B (zh
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林俊豪
陈信宇
谢守伟
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202310116294.3A priority Critical patent/CN116190238A/zh
Priority to CN201710655459.9A priority patent/CN109390397B/zh
Priority to US15/691,703 priority patent/US10566327B2/en
Publication of CN109390397A publication Critical patent/CN109390397A/zh
Priority to US16/724,404 priority patent/US11088137B2/en
Priority to US17/367,447 priority patent/US11876095B2/en
Application granted granted Critical
Publication of CN109390397B publication Critical patent/CN109390397B/zh
Priority to US18/525,909 priority patent/US20240105720A1/en
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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

本发公开一种半导体元件及其制作方法。制作半导体元件的方法为，首先提供一基底，该基底具有一第一区域以及一第二区域，然后形成一第一鳍状结构于第一区域以及一第二鳍状结构于第二区域，形成一图案化掩模于第二区域，之后再进行一处理制作工艺扩大第一鳍状结构，由此使第一鳍状结构的上表面不同于第二鳍状结构的上表面。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种扩大鳍状结构顶部的方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
一般而言，半导体制作工艺在进入10纳米世代后鳍状结构的临界尺寸(criticaldimension,CD)对整个元件的效能扮演了一重要脚色。以现今制备鳍状场效晶体管的制作流程而言，设于核心区(core region)的鳍状结构与输入/输出区(input/output region)的鳍状结构最终均具有约略相同的临界尺寸。然而，由于核心区的元件通常需较大的临界尺寸来提升通道区的容量而输入/输出区则反而需要较小的临界尺寸来改善短通道效应(short channel effect,SCE)，现行设计明显无法同时满足上述两个区域的需求。因此如何在现今场效晶体管的架构下改良此问题即为现今一重要课题。
发明内容
本发明一实施例公开一种制作半导体元件的方法。首先提供一基底，该基底具有一第一区域以及一第二区域，然后形成一第一鳍状结构于第一区域以及一第二鳍状结构于第二区域，形成一图案化掩模于第二区域，之后再进行一处理制作工艺扩大第一鳍状结构，由此使第一鳍状结构的上表面不同于第二鳍状结构的上表面。
本发明又一实施例公开一种半导体元件，其主要包含一基底具有一第一区域以及一第二区域、一第一鳍状结构设于第一区域以及一第二鳍状结构设于第二区域，其中第一鳍状结构的下表面等于第二鳍状结构的下表面且第一鳍状结构的上表面不同于第二鳍状结构的上表面。
附图说明
图1至图6为本发明一实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 第一区域
16 第二区域 18 第一鳍状结构
20 第二鳍状结构 22 浅沟隔离
24 上半部 26 下半部
28 第一栅极结构 30 第二栅极结构
32 介质层 34 栅极材料层
36 间隙壁 38 源极/漏极区域
40 接触洞蚀刻停止层 42 层间介电层
44 图案化掩模 46 半导体层
48 介质层 50 高介电常数介电层
52 功函数金属层 54 低阻抗金属层
56 第一金属栅极 58 第二金属栅极
60 凹槽
具体实施方式
请参照图1至图3，其中图1为本发明一实施例制作一半导体元件的上视图，图2左半部为图1中沿着切线AA'的剖面示意图，图2右半部为图1中沿着切线BB'的剖面示意图，图3左半部为图1中沿着切线CC'的剖面示意图，图3右半部则为图1中沿着切线DD'的剖面示意图。如图1至图3所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，并于基底上定义一第一区域14与第二区域16，其中第一区域14较佳为一后续用来制备主动元件的核心区而第二区域16则较佳为一用来连结主动元件与周边元件的输入/输出区。
然后形成多个鳍状结构于基底12上，例如形成第一鳍状结构18于第一区域14以及第二鳍状结构20于第二区域16，再形成一浅沟隔离(shallow trench isolation,STI)22环绕第一鳍状结构18及第二鳍状结构20。在本实施例中，形成浅沟隔离22的方式可先利用一可流动式化学气相沉积(flowable chemical vapor deposition,FCVD)制作工艺形成一氧化硅层于基底12上并完全覆盖各鳍状结构。接着利用化学机械研磨(chemical mechanicalpolishing,CMP)制作工艺并搭配蚀刻制作工艺去除部分氧化硅层，使剩余的氧化硅层低于鳍状结构表面以形成浅沟隔离22。
值得注意的是，如图3所示，部分第一鳍状结构18与第二鳍状结构20在形成介质层32的过程中可能被消耗形成二氧化硅而呈现上下不同宽度，因此形成介质层32后各第一鳍状结构18与第二鳍状结构20较佳分别定义出一上半部24以及一下半部26，其中第一区域14与第二区域16中上半部24与下半部26的交界处(如图中虚线处)较佳切齐浅沟隔离26上表面，且第一区域14与第二区域16的上半部24下表面均分别小于第一区域14与第二区域16的下半部26上表面。
依据本发明的优选实施例，各鳍状结构较佳通过侧壁图案转移(sidewall imagetransfer,SIT)等技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构。另外，鳍状结构的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构。这些形成鳍状结构的实施例均属本发明所涵盖的范围。
接着于各鳍状结构上形成至少一栅极结构或虚置栅极，例如第一栅极结构28与第二栅极结构30。在本实施例中，第一栅极结构28与第二栅极结构30的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-klast)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，可先依序形成一栅极介电层或介质层、一由多晶硅所构成的栅极材料层以及一选择性硬掩模于基底12上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分栅极材料层与部分栅极介电层，然后剥除图案化光致抗蚀剂，以于第一鳍状结构18与第二鳍状结构20上形成由图案化的介质层32与图案化的栅极材料层34所构成的第一栅极结构28与第二栅极结构30。
然后在第一栅极结构28与第二栅极结构30侧壁分别形成至少一间隙壁36，接着于间隙壁36两侧的鳍状结构以及/或基底12中形成一源极/漏极区域38及/或外延层(图未示)，并选择性于源极/漏极区域38及/或外延层的表面形成一金属硅化物(图未示)。在本实施例中，间隙壁36可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁以及一主间隙壁。其中偏位间隙壁与主间隙壁可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。源极/漏极区域38可依据所置备晶体管的导电型式而包含不同掺质，例如可包含P型掺质或N型掺质。
接着形成一接触洞蚀刻停止层40于鳍状结构表面与第一栅极结构28及第二栅极结构30上，再形成一层间介电层42于接触洞蚀刻停止层40上。然后进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)去除部分层间介电层42与部分接触洞蚀刻停止层40并暴露出由多晶硅材料所构成的栅极材料层34，使各栅极材料层34上表面与层间介电层42上表面齐平。
随后进行一金属栅极置换制作工艺将第一栅极结构18以及第二栅极结构20转换为金属栅极。举例来说，可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(Tetramethylammonium Hydroxide,TMAH)等蚀刻溶液来去除第一栅极结构18与第二栅极结构20中的栅极材料层34甚至介质层32，以于层间介电层42中形成凹槽60。
请接着参照图4至图6，图4至图6为本发明一实施例接续图3制作半导体元件的方法示意图。如图4所示，随后形成一图案化掩模44于第二区域16上，包括覆盖第二区域16的层间介电层42与第一介质层32并暴露出第一区域14的第一鳍状结构18以及浅沟隔离22。然后以图案化掩模44为掩模进行一蚀刻制作工艺，去除第一区域14的介质层32并暴露出第一鳍状结构18的上半部24。
接着如图5所示，先完全去除第二区域16的图案化掩模44，然后在不形成图案化掩模的情况下进行一处理制作工艺扩大第一鳍状结构18顶部，由此使第一鳍状结构18的上半部24上表面不同于第二鳍状结构20的上半部24上表面。更具体而言，此阶段所进行的处理制作工艺较佳包含进行一外延成长制作工艺以形成一半导体层46于第一鳍状结构18上，其中半导体层46与第一鳍状结构18较佳包含相同材料，因此所形成的半导体层46与原本的第一鳍状结构18较佳融为一体成为新的第一鳍状结构18上半部24。在本实施例中，半导体层46与第一鳍状结构18均较佳由硅所构成，但不局限于此，半导体层46与第一鳍状结构18又可依据制作工艺需求选用不同材料，且半导体层46与第一鳍状结构18均可选自由例如硅、锗、锗化硅以及磷化硅所构成的群组。
需注意的是，由于第二区域16的第二鳍状结构20上半部24在进行处理制作工艺之前已被介质层32所覆盖，因此半导体层46只会形成于第一区域14的第一鳍状结构18上半部24而不会形成于第二区域16的第二鳍状结构20上半部24。相较于原本图3的第一鳍状结构18上半部24与第二鳍状结构20上半部24具有相同高度与宽度，图5新形成的第一鳍状结构18上半部24较佳与第二鳍状结构20上半部24具有不同高度与宽度。
从细部来看，例如图6所示，新的第一区域14的上半部24下表面较佳大于第一区域14的下半部26上表面，第二区域16的上半部24下表面较佳小于第二区域16的下半部26上表面，第一区域14的上半部24上表面与下表面均较佳大于第二区域16的上半部24上表面与下表面，以及第一区域14的下半部26上表面较佳等于第二区域16的下半部26上表面。换言之，只有第一区域14中第一鳍状结构18被栅极跨过的通道区域表面积增加，由此提高通道宽度，第二区域16中第二鳍状结构20被栅极跨过的通道区域表面积及通道宽度则未改变。
如图6所示，随后形成另一介质层48于第一鳍状结构18以及第二鳍状结构20上，再依序形成一高介电常数介电层50、一功函数金属层52以及一低阻抗金属层54于凹槽60内，然后进行一平坦化制作工艺，例如利用CMP去除部分低阻抗金属层54、部分功函数金属层52以及部分高介电常数介电层50以形成第一金属栅极56以及第二金属栅极58。以本实施例利用后高介电常数介电层制作工艺所制作的栅极结构为例，第一金属栅极56较佳包含一介质层48或栅极介电层、一U型高介电常数介电层50、一U型功函数金属层52以及一低阻抗金属层54。第二金属栅极58则包含一介质层32、另一介质层48、一U型高介电常数介电层50、一U型功函数金属层52以及一低阻抗金属层54。
在本实施例中，高介电常数介电层50包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层52较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层52可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层52可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层52与低阻抗金属层54之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层54则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
综上所述，本发明主要先于半导体基底上的核心区与输入/输出区分别形成鳍状结构，然后形成一图案化掩模并覆盖输入/输出区，再进行一处理制作工艺，例如利用外延成长方式于核心区的鳍状结构上形成一半导体层，由此提升核心区整个鳍状结构的临界尺寸并增加通道宽度。由于输入/输出区的鳍状结构在形成半导体层的过程中已被图案化掩模所遮蔽，因此在核心区的鳍状结构临界尺寸扩大后输入/输出区的鳍状结构临界尺寸并不会有任何改变。
一般而言，由于核心区的元件通常需较大的临界尺寸来提升通道区的容量而输入/输出区则反而需要较小的临界尺寸来改善短通道效应(short channel effect,SCE)，本发明依据此制作方式本发明可在维持输入/输出区的鳍状结构临界尺寸的情况下扩大核心区的鳍状结构临界尺寸，由此同时满足上述两个区域的需求并提升元件的整体效能。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底具有第一区域以及第二区域；
形成一第一鳍状结构于该第一区域以及一第二鳍状结构于该第二区域；
形成一图案化掩模于该第二区域；以及
进行一处理制作工艺扩大该第一鳍状结构，由此使该第一鳍状结构的上表面不同于该第二鳍状结构的上表面。
2.如权利要求1所述的方法，还包含：
形成一第一介质层于该第一鳍状结构及该第二鳍状结构上；
形成该图案化掩模于该第二区域的该第一介质层上；
去除该第一区域的该第一介质层；
去除该第二区域的该图案化掩模；以及
形成一第二介质层于该第一鳍状结构及该第二鳍状结构上。
3.如权利要求1所述的方法，还包含：
形成一第一栅极结构于该第一鳍状结构上，以及一第二栅极结构于该第二鳍状结构上；
形成一层间介电层，环绕该第一栅极结构及该第二栅极结构；
去除该第一栅极结构以及该第二栅极结构以形成一第一凹槽及第二凹槽；以及
在形成该第一凹槽及该第二凹槽之后，形成该图案化掩模于该第二区域的该第一介质层上。
4.如权利要求1所述的方法，其中各该第一鳍状结构及该第二鳍状结构包含一上半部以及一下半部，该方法包含：
形成一浅沟隔离，环绕该第一鳍状结构以及该第二鳍状结构的该下半部。
5.如权利要求4所述的方法，其中该第一区域的该上半部的下表面以及该第二区域的该下半部的上表面切齐该浅沟隔离的上表面。
6.如权利要求4所述的方法，其中该第一区域的该上半部的下表面大于该第一区域的该下半部的上表面。
7.如权利要求4所述的方法，其中该第二区域的该上半部的下表面小于该第二区域的该下半部的上表面。
8.如权利要求1所述的方法，其中该第一鳍状结构的下表面等于该第二鳍状结构的下表面。
9.如权利要求1所述的方法，其中该处理制作工艺包含进行一外延成长制作工艺，以形成一半导体层于该第一鳍状结构上。
10.如权利要求9所述的方法，其中该半导体层以及该第一鳍状结构包含相同材料。
11.一种半导体元件，包含：
基底，具有第一区域以及第二区域；
第一鳍状结构，设于该第一区域；以及
第二鳍状结构，设于该第二区域，其中该第一鳍状结构的下表面等于该第二鳍状结构的下表面且该第一鳍状结构的上表面不同于该第二鳍状结构的上表面。
12.如权利要求11所述的半导体元件，其中各该第一鳍状结构以及该第二鳍状结构包含一上半部以及一下半部，该半导体元件包含：
浅沟隔离，环绕该第一鳍状结构以及该第二鳍状结构的该下半部。
13.如权利要求12所述的半导体元件，其中该第一区域的该上半部的下表面以及该第二区域的该下半部的上表面切齐该浅沟隔离的上表面。
14.如权利要求12所述的半导体元件，其中该第一区域的该上半部的下表面大于该第一区域的该下半部的上表面。
15.如权利要求12所述的半导体元件，其中该第二区域的该上半部的下表面小于该第二区域的该下半部的上表面。
16.如权利要求12所述的半导体元件，其中该第一区域的该上半部的下表面大于该第二区域的该上半部的上表面。
17.如权利要求12所述的半导体元件，其中该第一区域的该下半部的上表面等于该第二区域的该下半部的上表面。
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