CN109362013B - Combined sensor - Google Patents

Combined sensor Download PDF

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Publication number
CN109362013B
CN109362013B CN201811496462.1A CN201811496462A CN109362013B CN 109362013 B CN109362013 B CN 109362013B CN 201811496462 A CN201811496462 A CN 201811496462A CN 109362013 B CN109362013 B CN 109362013B
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Prior art keywords
chip
mems
asic
mems chip
asic chip
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CN201811496462.1A
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CN109362013A (en
Inventor
王德信
杨军伟
潘新超
端木鲁玉
邱文瑞
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Weifang Goertek Microelectronics Co Ltd
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Weifang Goertek Microelectronics Co Ltd
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Priority to CN201811496462.1A priority Critical patent/CN109362013B/en
Priority to PCT/CN2018/122918 priority patent/WO2020113696A1/en
Publication of CN109362013A publication Critical patent/CN109362013A/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04RLOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R19/00Electrostatic transducers
    • H04R19/04Microphones

Abstract

The invention discloses a combination sensor, which comprises: a substrate having an upper surface and a lower surface; the first MEMS chip and the first ASIC chip are mounted on the upper surface of the substrate, the first MEMS chip and the first ASIC chip are electrically connected, and the first MEMS chip is of a capacitive structure; the second MEMS chip and the second ASIC chip are mounted on the upper surface of the substrate, the second MEMS chip and the second ASIC chip are electrically connected, and the working voltage of the second MEMS chip is alternating voltage; the shortest distance between the first MEMS chip and the second ASIC chip is d1, d1 is more than or equal to 0.3mm, the shortest distance between the first ASIC chip and the second ASIC chip is d2, and d2 is more than or equal to 1.2mm. According to the technical scheme, the parasitic capacitance effect is weakened, so that electromagnetic induction is reduced, the noise floor of the first MEMS chip is greatly reduced when the combined sensor works, and the overall performance of the combined sensor is improved.

Description

Combined sensor
Technical Field
The invention relates to the technical field of sensors, in particular to a combined sensor.
Background
The two MEMS chips and the two ASIC chips are packaged to form the combined sensor, specifically, the first MEMS chip is electrically connected with the first ASIC chip, the second MEMS chip is electrically connected with the second ASIC chip, the first MEMS chip is of a capacitive structure, the working voltage of the second MEMS chip is alternating voltage, and due to the fact that the packaging space is compact, when the combined sensor works, the background noise of the first MEMS chip is large due to the parasitic capacitance effect, and therefore the overall performance of the combined sensor is affected.
Disclosure of Invention
The invention mainly aims to provide a combined sensor, which aims to improve the performance of the combined sensor.
To achieve the above object, the present invention discloses a combination sensor including:
a substrate having an upper surface and a lower surface;
a first MEMS chip and a first ASIC chip mounted to an upper surface of the substrate, the first MEMS chip and the first ASIC chip being electrically connected, the first MEMS chip being of a capacitive structure; and
a second MEMS chip and a second ASIC chip mounted to an upper surface of the substrate, the second MEMS chip and the second ASIC chip being electrically connected, an operating voltage of the second MEMS chip being an alternating voltage;
the shortest distance between the first MEMS chip and the second ASIC chip is d1, d1 is more than or equal to 0.3mm, and the shortest distance between the first ASIC chip and the second ASIC chip is d2, and d2 is more than or equal to 1.2mm.
In an embodiment of the invention, the shortest distance d1 is formed between a side of the first MEMS chip and a side of the second ASIC chip;
the shortest distance d2 is formed between a side of the first ASIC chip and a side of the second ASIC chip.
In an embodiment of the present invention, the first MEMS chip is rectangular, the first ASIC chip is rectangular, and the second ASIC chip is rectangular;
the shortest distance d1 is formed between a side edge of the first MEMS chip and a side edge of the second ASIC chip;
the shortest distance d2 is formed between a side edge of the first ASIC chip and a side edge of the second ASIC chip.
In an embodiment of the present invention, a connection line of the shortest distance between the first MEMS chip and the second MEMS chip is a, and a connection line of the shortest distance between the first ASIC chip and the second ASIC chip is b, where a and b intersect.
In an embodiment of the invention, the first MEMS chip and the second MEMS chip are arranged side by side.
In an embodiment of the present invention, the substrate is rectangular, and the first ASIC chip and the second ASIC chip are distributed in a diagonal direction of the substrate.
In an embodiment of the invention, the volume of the first MEMS chip is smaller than the volume of the second MEMS chip or the second ASIC chip;
and/or, the working voltage of the first MEMS chip is direct-current voltage;
and/or, the substrate is a circuit board.
In an embodiment of the invention, the first MEMS chip is a microphone chip.
In an embodiment of the invention, the substrate is provided with an acoustic hole, and the microphone chip covers the acoustic hole.
In an embodiment of the invention, the combined sensor further includes a housing, the housing is disposed on the upper surface of the substrate, and defines an encapsulation cavity with the substrate;
the first MEMS chip, the first ASIC chip, the second MEMS chip and the second ASIC chip are arranged in the packaging cavity.
According to the technical scheme, the first MEMS chip and the first ASIC chip corresponding to the first MEMS chip are arranged on the substrate, the second MEMS chip and the second ASIC chip corresponding to the second MEMS chip are arranged on the substrate, the shortest distance between the first MEMS chip and the second ASIC chip is set to be more than or equal to 0.3mm, the shortest distance between the first ASIC chip and the second ASIC chip is set to be more than or equal to 1.2mm, and parasitic capacitance effect is weakened in this way, so that electromagnetic induction is reduced, noise floor of the first MEMS chip is greatly reduced when the combined sensor works, and the integral performance of the combined sensor is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a combination sensor according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a combination sensor according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a combination sensor according to an embodiment of the invention.
Reference numerals illustrate:
reference numerals Name of the name Reference numerals Name of the name
100 Substrate board 320 First ASIC chip
110 Upper surface of 410 Second MEMS chip
310 First MEMS chip 420 Second ASIC chip
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
In the present invention, unless specifically stated and limited otherwise, the terms "connected," "affixed," and the like are to be construed broadly, and for example, "affixed" may be a fixed connection, a removable connection, or an integral body; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
In the present invention, two MEMS chips and two ASIC chips are packaged to form a combined sensor, specifically, a first MEMS chip 310 is electrically connected to a first ASIC chip 320, a second MEMS chip 410 is electrically connected to a second ASIC chip 420, the first MEMS chip 310 is in a capacitive structure, and the working voltage of the second MEMS chip 410 is an ac voltage, and because the packaging structure is compact, when the combined sensor works, the noise floor of the first MEMS chip 310 is larger, thereby affecting the overall performance of the combined sensor.
In order to solve the above technical problems, the present invention provides a combination sensor.
In one embodiment of the present invention, as shown in fig. 1, the combination sensor includes:
a substrate 100, the substrate 100 having an upper surface 110 and a lower surface;
a first MEMS chip 310 and a first ASIC chip 320, the first MEMS chip 310 and the first ASIC chip 320 being mounted to the upper surface 110 of the substrate 100, the first MEMS chip 310 and the first ASIC chip 320 being electrically connected, the first MEMS chip 310 being of a capacitive structure; and
a second MEMS chip 410 and a second ASIC chip 420, the second MEMS chip 410 and the second ASIC chip 420 being mounted to the upper surface 110 of the substrate 100, the second MEMS chip 410 and the second ASIC chip 420 being electrically connected, an operating voltage of the second MEMS chip 410 being an alternating voltage;
the shortest distance between the first MEMS chip 310 and the second ASIC chip 420 is d1, d1 is greater than or equal to 0.3mm, and the shortest distance between the first ASIC chip 320 and the second ASIC chip 420 is d2, d2 is greater than or equal to 1.2mm.
In the present embodiment, the substrate 100 of the combination sensor has a rectangular shape, and a circuit board well known to those skilled in the art may be used as the substrate 100.
MEMS (Micro-Electro-Mechanical System) chips are an independent intelligent system, the internal structure of the MEMS chips is generally in the order of micrometers or nanometers, and the MEMS chips have the characteristics of small volume, light weight, low power consumption, good durability, stable performance and the like, and are increasingly widely applied to electronic equipment along with the development of miniaturization and light weight of the equipment. An ASIC (Application Specific Integrated Circuit, integrated circuit) chip is used to process, e.g., amplify, the electrical signals. The MEMS chip and ASIC chip may be attached to the substrate 100 in a manner well known to those skilled in the art.
In this embodiment, a first MEMS chip 310 and a first ASIC chip 320 are provided, and the first MEMS chip 310 and the first ASIC chip 320 are electrically connected. The first MEMS chip 310 is provided with an interface, the first ASIC chip 320 is provided with an interface, and the interface of the first MEMS chip 310 is bonded with the interface of the first ASIC chip 320 through a metal wire, thereby realizing electrical connection. For example, the metal wire is made of gold, and the first MEMS chip 310 and the first ASIC chip 320 are treated by using an adhesive so that the first MEMS chip 310 and the first ASIC chip 320 have good adhesion performance, and the interface of the first MEMS chip 310 and the interface of the first ASIC chip 320 are bonded by using the metal wire made of high-purity gold, so as to realize the electrical connection of the first MEMS chip 310 and the first ASIC chip 320. The same is true for the electrical connection of the second MEMS chip 410 and the second ASIC chip 420.
The first MEMS chip 310 is of a capacitive structure, and the working voltage of the second MEMS chip 410 is an ac voltage, so that the signal in the working of the second ASIC chip 420 electrically connected to the second MEMS chip 410 is an ac signal, and the noise floor of the first MEMS chip 310 is larger due to the compact packaging structure. In order to ensure that the first MEMS chip 310 has good noise floor performance, for example, when the first MEMS chip 310 is a microphone chip, it needs to be ensured that the noise floor is low, and the parasitic capacitance effects between the first MEMS chip 310 and the second ASIC chip 420 and between the first ASIC chip 320 and the second ASIC chip 420 are weakened by the limitation of the distances d1 and d2 in this embodiment, so that electromagnetic induction is reduced, so that the noise floor of the first MEMS chip 310 is greatly reduced when the combined sensor is in operation, and the overall performance of the combined sensor is further improved.
In an embodiment of the present invention, the shortest distance d1 is formed between the side of the first MEMS chip 310 and the side of the second ASIC chip 420;
the shortest distance d2 is formed between the side of the first ASIC chip 320 and the side of the second ASIC chip 420.
In this embodiment, the shortest distance d1 is formed between the side of the first MEMS chip 310 and the side of the second ASIC chip 420, for example, the side of the first MEMS chip 310 has a connection point, the side of the second ASIC chip 420 has a connection point, and the connection distance between the connection point of the first MEMS chip 310 and the connection point of the second ASIC chip 420 is the shortest distance between the first MEMS chip 310 and the second ASIC chip, and so is the shortest distance d 2. The first MEMS chip 310, the first ASIC chip 320, and the second ASIC chip 420 are three-dimensional structures such that d1 and d2 are ensured to achieve maximum values on the limited area substrate 100 to reduce the noise floor of the first MEMS chip 310.
In an embodiment of the present invention, the first MEMS chip 310 is rectangular, the first ASIC chip 320 is rectangular, and the second ASIC chip 420 is rectangular;
the shortest distance d1 is formed between a side edge of the first MEMS chip 310 and a side edge of the second ASIC chip 420;
the shortest distance d2 is formed between the lateral edge of the first ASIC chip 320 and the lateral edge of the second ASIC chip 420.
The cube is a special cuboid, in this embodiment, the shortest distance d1 is formed between the side edge of the first MEMS chip 310 and the side edge of the second ASIC chip 420, for example, the side edge of the first MEMS chip 310 has a connection point, the side edge of the second ASIC chip 420 has a connection point, and the connection distance between the connection point of the first MEMS chip 310 and the connection point of the second ASIC chip 420 is the shortest distance between the first MEMS chip 310 and the second ASIC chip, and the shortest distance d2 is also the same. In this way, the arrangement of the chips is more regular under the premise of limited packaging space and reduced noise floor of the first MEMS chip 310.
In an embodiment of the present invention, as shown in fig. 2, a connection line of the shortest distance between the first MEMS chip 310 and the second MEMS chip 410 is a, and a connection line of the shortest distance between the first ASIC chip 320 and the second ASIC chip 420 is b, where a and b intersect. In this embodiment, a rectangular planar coordinate system XOY is defined, the second MEMS chip 410 and the second ASIC chip 420 are sequentially arranged along the Y direction, and the first MEMS chip 310 and the first ASIC chip 320 are sequentially arranged along the opposite direction of the Y direction, so that a limited package space can be maximally utilized when a and b intersect.
Further, the first MEMS chip 310 and the second MEMS chip 410 are arranged side by side. The second MEMS chip 410 and the first MEMS chip 310 are arranged in parallel along the X direction, for example, as shown in fig. 1, and are arranged in a straight line, so that d1 and d2 are ensured to be large enough to reduce noise floor of the first MEMS chip 310 on the premise of maximally ensuring miniaturization of the product
In an embodiment of the present invention, as shown in fig. 1 and 2, the substrate 100 is rectangular, and the first ASIC chip 320 and the second ASIC chip 420 are distributed in a diagonal direction of the substrate 100. The rectangle includes square and rectangle, as shown in fig. 1 and 2, in this embodiment, the substrate 100 is in a long direction, the first ASIC chip 320 and the first MEMS chip 310 are arranged on the right side of the substrate 100, the first ASIC chip 320 is located at the lower right corner of the substrate 100, the second ASIC chip 420 and the second MEMS chip 410 are arranged on the left side of the substrate 100, and the second ASIC chip 420 is located at the upper left corner of the substrate 100, so that the distance d2 can be effectively increased while the distance d1 is ensured.
In one embodiment of the present invention, as shown in fig. 3, the volume of the first MEMS chip 310 is smaller than the volume of the second MEMS chip 410 or the second ASIC chip 420. In this embodiment, by reducing the volume of the first MEMS chip 310, the value of d1 is increased, and the parasitic capacitance effect can be further reduced and the noise floor of the first MEMS chip 310 can be reduced under the same package area.
In an embodiment of the present invention, the working voltage of the first MEMS chip 310 is a dc voltage.
In an embodiment of the present invention, the first MEMS chip 310 is a microphone chip. In this embodiment, the first MEMS chip 310 is a microphone chip, which can convert a sound signal into an electrical signal, thereby achieving capturing of sound.
Further, the substrate 100 is provided with an acoustic hole (not shown in the figure), and the microphone chip (first MEMS chip 310) covers the acoustic hole.
In the present embodiment, the microphone chip (first MEMS chip 310) covers the sound hole, and external sound can be transmitted to the microphone chip (first MEMS chip 310) through the sound hole, thereby facilitating the acquisition of sound signals by the microphone chip (first MEMS chip 310).
In an embodiment of the present invention, the substrate 100 is a circuit board. The circuit board has circuitry formed thereon and may be fabricated in a manner well known to those skilled in the art.
In one embodiment of the present invention, the combined sensor further includes a housing (not shown in the drawings), where the housing is disposed on the upper surface 110 of the substrate 100, and defines an enclosure with the substrate 100;
the first MEMS chip 310, the first ASIC chip 320, the second MEMS chip 410, and the second ASIC chip 420 are disposed in the package cavity.
In this embodiment, the housing is disposed on the upper surface 110 of the substrate 100, and the housing and the upper surface together define a package cavity. Specifically, the housing includes a cover plate and a surrounding plate formed at an edge of the cover plate, the cover plate and the surrounding plate can be integrally formed, the surrounding plate encloses the cover plate to form an open cavity, and the housing is attached to the base plate 100 through the surrounding plate, thereby forming a closed package cavity. The housing and the substrate 100 may be mounted by a die attach adhesive or soldered to form a package. The packaging structure is used for packaging each chip, and each chip is arranged on the upper surface of the substrate 100 corresponding to the packaging cavity, so that interference of external signals is avoided.
Further, the cover shell is made of metal, namely, the cover shell forms an electromagnetic shielding cover, so that the packaging requirement of each chip is met, and each chip is protected from being interfered by external electromagnetic signals.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the description of the present invention and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the invention.

Claims (9)

1. A combination sensor, the combination sensor comprising:
a substrate having an upper surface and a lower surface;
a first MEMS chip and a first ASIC chip mounted to an upper surface of the substrate, the first MEMS chip and the first ASIC chip being electrically connected, the first MEMS chip being of a capacitive structure; and
a second MEMS chip and a second ASIC chip mounted to an upper surface of the substrate, the second MEMS chip and the second ASIC chip being electrically connected, an operating voltage of the second MEMS chip being an alternating voltage;
the shortest distance between the first MEMS chip and the second ASIC chip is d1, d1 is more than or equal to 0.3mm, the shortest distance between the first ASIC chip and the second ASIC chip is d2, and d2 is more than or equal to 1.2mm;
the shortest distance connecting line of the first MEMS chip and the second MEMS chip is a, the shortest distance connecting line of the first ASIC chip and the second ASIC chip is b, and the a and the b intersect;
the first MEMS chip and the first ASIC chip are respectively provided with an interface, and the interface on the first MEMS chip is bonded with the interface on the first ASIC chip through a metal wire;
the second MEMS chip and the second ASIC chip are respectively provided with an interface, and the interface on the second MEMS chip is bonded with the interface on the second ASIC chip through a metal wire.
2. The combination sensor of claim 1, wherein the shortest distance d1 is formed between a side of the first MEMS chip and a side of the second ASIC chip;
the shortest distance d2 is formed between a side of the first ASIC chip and a side of the second ASIC chip.
3. The combination sensor of claim 1, wherein the first MEMS chip is rectangular, the first ASIC chip is rectangular, and the second ASIC chip is rectangular;
the shortest distance d1 is formed between a side edge of the first MEMS chip and a side edge of the second ASIC chip;
the shortest distance d2 is formed between a side edge of the first ASIC chip and a side edge of the second ASIC chip.
4. A combination sensor according to any one of claims 1 to 3, wherein the first MEMS chip and the second MEMS chip are arranged side by side.
5. The combination sensor of claim 1, wherein the substrate is rectangular, and the first ASIC chip and the second ASIC chip are distributed in a diagonal direction of the substrate.
6. The combination sensor of claim 1, wherein a volume of the first MEMS chip is less than a volume of the second MEMS chip or second ASIC chip;
and/or, the working voltage of the first MEMS chip is direct-current voltage;
and/or, the substrate is a circuit board.
7. The combination sensor of claim 1, wherein the first MEMS chip is a microphone chip.
8. The combination sensor of claim 7, wherein the substrate is provided with an acoustic port, the microphone chip covering the acoustic port.
9. The combination sensor of claim 1, further comprising a housing disposed on an upper surface of the substrate, the housing defining an enclosure with the substrate;
the first MEMS chip, the first ASIC chip, the second MEMS chip and the second ASIC chip are arranged in the packaging cavity.
CN201811496462.1A 2018-12-07 2018-12-07 Combined sensor Active CN109362013B (en)

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CN201811496462.1A CN109362013B (en) 2018-12-07 2018-12-07 Combined sensor
PCT/CN2018/122918 WO2020113696A1 (en) 2018-12-07 2018-12-22 Combined sensor

Applications Claiming Priority (1)

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