CN109243979B - Semiconductor power device and manufacturing method thereof - Google Patents
Semiconductor power device and manufacturing method thereof Download PDFInfo
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- CN109243979B CN109243979B CN201710556890.8A CN201710556890A CN109243979B CN 109243979 B CN109243979 B CN 109243979B CN 201710556890 A CN201710556890 A CN 201710556890A CN 109243979 B CN109243979 B CN 109243979B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
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- 238000000034 method Methods 0.000 claims abstract description 57
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention provides a semiconductor power device and a manufacturing method thereof. The method for manufacturing the semiconductor power device comprises the following steps: sequentially forming an epitaxial layer, a well region, a source region and a body contact region on one side of a substrate; forming a first-order gate insulating sublayer on one side, far away from the substrate, of the epitaxial layer, the well region, the source region and the body contact region; forming a second step gate insulating sub-layer and a first polycrystalline silicon sub-layer on one side, far away from the substrate, of the first step gate insulating sub-layer; forming a second polysilicon sub-layer on one side of the second gate insulating sub-layer and the first polysilicon sub-layer, which is far away from the substrate, and photoetching to form a gate; wherein the second gate insulating sublayer is formed by performing a local high temperature oxidation process on the first polysilicon layer. The manufacturing method provided by the invention can carry out high-temperature oxidation on the polycrystalline silicon sub-layer by layer to obtain the multi-level gate insulating layer structure, so that the surface of the multi-level gate insulating layer structure is smoother, the phenomenon that the surface is uneven or corrosive agent is remained easily caused by an etching method is avoided, and the use reliability of a semiconductor power device is further improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor power device and a manufacturing method thereof.
Background
At present, the silicon carbide material has excellent physical and electrical properties, and has the unique advantages of large forbidden band width, high critical breakdown electric field, high thermal conductivity, high saturation drift velocity and the like, so that the silicon carbide material becomes an ideal material for manufacturing high-voltage, high-power, high-temperature-resistant, high-frequency and anti-radiation devices, and has wide application prospects in military and civil fields. The silicon carbide power device has the advantages of high switching speed and low on-resistance, can realize higher breakdown voltage level by the smaller thickness of the drift layer, reduces the size of a power switch module, reduces energy consumption, and has obvious advantages in the application fields of power switches, converters and the like.
At present, in order to reduce the electric field intensity borne by a gate oxide layer and improve the reliability of a MOSFET device, a multi-stage gate oxide layer structure which is symmetrical in a multi-stage step shape is proposed. However, since the multi-step gate oxide structure is formed by etching the gate oxide, the etching process may damage the gate oxide, which is not favorable for the long-term reliability of the power device.
Therefore, the method for manufacturing the multi-stage gate oxide structure in the semiconductor power device at the present stage still needs to be improved.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
The present invention has been completed based on the following findings of the inventors:
the inventor finds that in the research process, the etching process adopted at the present stage has the defect of different etching rates due to the fact that the etching method has the defect of uneven etching rate, the surface of the etched gate oxide layer is uneven no matter wet etching or dry etching is carried out, particularly, the wet etching is easy to cause residual corrosive liquid on the surface of the gate oxide layer, and therefore the long-term usability and stability of the semiconductor power device are affected.
In order to solve the technical problem that the etching process is easy to damage a multi-level gate oxide layer structure, the application provides a method for manufacturing a metal-oxide semiconductor field effect transistor (MOSFET) device, wherein the multi-level gate oxide layer structure comprises a first gate insulating sublayer and at least one second gate insulating sublayer, and the second gate insulating sublayer is obtained by performing high-temperature oxidation treatment on a partial region of a first polycrystalline silicon layer. The gate insulating layer obtained by the manufacturing method has a smooth surface, the adverse effect that the etching method is easy to cause uneven surface or residual corrosive agent is avoided, and the specific size of the step can be designed by adjusting the size of each gate insulating sublayer, so that the use reliability of the semiconductor power device is improved.
In view of the above, an objective of the present invention is to provide a method for manufacturing a semiconductor power device, which can make the surface of the multi-level gate insulating layer structure smoother and have higher step size precision.
In a first aspect of the invention, a method of fabricating a semiconductor power device is presented.
According to an embodiment of the invention, the method comprises: sequentially forming an epitaxial layer, a well region, a source region and a body contact region on one side of a substrate, wherein the epitaxial layer is arranged on one side of the substrate, the well region is symmetrically arranged on one side, far away from the substrate, of the epitaxial layer by taking the central line of the substrate as an axis, and the source region and the body contact region are respectively and independently arranged on one side, far away from the substrate, of the well region by taking the central line of the substrate as an axis; forming a first step gate insulating sub-layer on one side, far away from the substrate, of the epitaxial layer, the well region, the source region and the body contact region; forming a second sub-gate insulating layer and a first sub-polysilicon layer on the side, far away from the substrate, of the first sub-gate insulating layer; forming a second polysilicon sublayer on one side, far away from the substrate, of the second step gate insulating sublayer and the first polysilicon sublayer, and photoetching the second polysilicon sublayer and the first polysilicon sublayer to form a gate; wherein the step of forming the second sub-layer of gate insulation and the first sub-layer of polysilicon further comprises: sequentially forming a first polysilicon layer and a patterned protective layer on one side of the first gate insulating sublayer away from the substrate; carrying out high-temperature oxidation treatment on the region of the first polycrystalline silicon layer which is not protected by the protective layer so as to obtain a second step gate insulating sublayer and a first polycrystalline silicon sublayer; and removing the protective layer.
The inventors surprisingly found that by using the method for manufacturing a semiconductor power device of the embodiment of the invention, a multi-level gate insulating layer structure can be obtained by performing high-temperature oxidation treatment on the polysilicon sub-layers layer by layer, so that the surface of the multi-level gate insulating layer is smoother, the adverse effect that the etching method is easy to cause uneven surface or residual corrosive is avoided, and the size of the step can be accurately designed by adjusting the size of each gate insulating sub-layer, so that the use reliability of the semiconductor power device is improved.
In a second aspect of the invention, a semiconductor power device is presented.
According to the embodiment of the invention, the semiconductor power device is manufactured by the method.
The inventors have surprisingly found that the surface of the multi-level gate insulating layer of the semiconductor power device of the embodiment of the invention is smoother and has higher dimensional accuracy, so that the long-term reliability of the semiconductor power device is better. It will be appreciated by those skilled in the art that the features and advantages described above with respect to the method of fabricating a semiconductor power device are still applicable to the semiconductor power device and will not be described in detail herein.
In a third aspect of the invention, a semiconductor power device is presented.
According to an embodiment of the present invention, the semiconductor power device includes: a substrate; the epitaxial layer is arranged on one side of the substrate; the well region is arranged on one side, away from the substrate, of the epitaxial layer and takes the central line of the substrate as an axis; the source region is arranged on one side, away from the substrate, of the well region in an axisymmetric manner by taking the central line of the substrate as an axis; the body contact region is arranged on one side of the well region away from the substrate in an axisymmetric manner by taking the central line of the substrate as an axis; the grid insulating layer is arranged on one side, far away from the substrate, of the well region and the source region, is of a multi-stage structure consisting of a plurality of grid insulating sublayers and is formed by silicon dioxide; the grid electrode is arranged on one side, far away from the substrate, of the grid insulation layer and consists of a plurality of polysilicon sublayers.
The inventors have surprisingly found that the surface of the multi-level gate insulating layer of the semiconductor power device of the embodiment of the invention is smoother and has higher dimensional accuracy, so that the long-term reliability of the semiconductor power device is better.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a flow chart of a method of fabricating a semiconductor power device in accordance with one embodiment of the present invention;
FIG. 2 is a schematic diagram of the product structure of step S100 of the manufacturing method according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of the product structure of step S200 of the manufacturing method according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of a semi-finished product in step S310 of the manufacturing method according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a semi-finished product of step S310 of the manufacturing method according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the product structure of step S310 of the manufacturing method according to one embodiment of the present invention;
FIG. 7 is a schematic diagram of the product structure of step S320 of the manufacturing method according to one embodiment of the present invention;
FIG. 8 is a schematic diagram of the product structure of step S330 of the manufacturing method according to one embodiment of the present invention;
FIG. 9 is a schematic diagram of a product structure of step S300 of the manufacturing method according to another embodiment of the present invention;
FIG. 10 is a schematic diagram of a semi-finished structure of step S400 of the fabrication method of one embodiment of the present invention;
FIG. 11 is a schematic diagram of the product structure of step S400 of the manufacturing method of one embodiment of the present invention;
FIG. 12 is a schematic diagram of the product structure of step S500 of the manufacturing method according to one embodiment of the invention;
FIG. 13 is a schematic diagram of a semi-finished structure of step S600 of the manufacturing method according to one embodiment of the present invention;
FIG. 14 is a schematic diagram of a semi-finished structure of step S600 of the manufacturing method according to one embodiment of the present invention;
FIG. 15 is a schematic diagram of the product structure of step S600 of the manufacturing method according to one embodiment of the invention;
fig. 16 is a schematic structural diagram of a semiconductor power device of an embodiment of the present invention;
fig. 17 is a schematic structural view of a semiconductor power device of another embodiment of the present invention;
fig. 18 is a flow chart of a method of fabricating a semiconductor power device in accordance with another embodiment of the present invention;
fig. 19 is a flow chart of a method of fabricating a semiconductor power device in accordance with another embodiment of the present invention.
Reference numerals
100 substrate
110 epitaxial layer
120 well region
130 source region
140 body contact region
200 gate insulating layer
210 first gate insulating sublayer
220 second step gate insulating sublayer
300 grid
310 first polysilicon layer
320 first polysilicon sublayer
330 second polysilicon sublayer
400 protective layer
410 dense layer
500 isolation dielectric layer
600 contact hole
700 drain electrode
800 source electrode
Detailed Description
The following examples of the present invention are described in detail, and it will be understood by those skilled in the art that the following examples are intended to illustrate the present invention, but should not be construed as limiting the present invention. Unless otherwise indicated, specific techniques or conditions are not explicitly described in the following examples, and those skilled in the art may follow techniques or conditions commonly employed in the art or in accordance with the product specifications. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available on the market.
In one aspect of the invention, a method of fabricating a semiconductor power device is presented. The manufacturing method of the present invention will be described in detail with reference to fig. 1 to 15.
According to an embodiment of the present invention, referring to fig. 1, the manufacturing method includes:
s100: an epitaxial layer, a well region, a source region and a body contact region are sequentially formed on one side of the substrate.
In this step, referring to fig. 2, on one side of the substrate 100, an epitaxial layer 110, a well region 120, a source region 130, and a body contact region 140 are sequentially formed; wherein, the epitaxial layer 110 is disposed on one side of the substrate 100, the well region 120 is disposed on one side of the epitaxial layer 110 away from the substrate 100 with the center line AA 'of the substrate 100 as an axis symmetry, and the source region 130 and the body contact region 140 are independently disposed on one side of the well region 120 away from the substrate 100 with the center line AA' of the substrate 100 as an axis symmetry respectively.
The specific materials of the substrate 100, the epitaxial layer 110, the well region 120, the source region 130 and the body contact region 140 are not particularly limited, and can be designed and selected by those skilled in the art according to the requirements of the semiconductor power device. In some embodiments of the present invention, the substrate 100 may be selected to be of a first conductivity type, the epitaxial layer 110 may be selected to be of a first conductivity type, the well region 120 may be selected to be of a second conductivity type, the source region 130 may be selected to be of a first conductivity type, and the body contact region 140 may be selected to be of a second conductivity type; wherein the first conductivity type is selected from one of an N-type and a P-type, and the second conductivity type is selected from the other of the N-type and the P-type. Thus, a person skilled in the art can select the first conductivity type to be N-type or P-type according to specific use requirements of the semiconductor power device, so that the application range of the semiconductor power device is wider. In some specific examples of the invention, the substrate 100 may also be formed of nitrogen-doped N-type silicon carbide. Thus, the substrate 100 made of the above materials has the unique advantages of large forbidden bandwidth, high critical breakdown electric field, high thermal conductivity, high saturation drift velocity and the like, so that the semiconductor power device has the advantages of high switching speed and small on-resistance.
According to the embodiment of the present invention, the specific cross-sectional shapes of the well region 120, the source region 130 and the body contact region 140 are not particularly limited, such as stripe shape, ring shape, etc., and those skilled in the art can design the cross-sectional shapes according to the specific requirements of the semiconductor power device. In some embodiments of the present invention, the cross-sections of the well region 120, the source region 130 and the body contact region 140 may be two strips each independently, which are symmetric about the substrate centerline. In other embodiments of the present invention, the cross-sections of well region 120, source region 130, and body contact region 140 may each independently be annular centered on the substrate centerline.
The specific methods for forming the epitaxial layer 110, the well region 120, the source region 130 and the body contact region 140 according to the embodiments of the present invention are not particularly limited, and those skilled in the art can select the specific materials according to the above structures. In some embodiments of the present invention, a nitrogen-doped N-type epitaxial layer 110 may be formed on a nitrogen-doped silicon carbide substrate 100; then, a mask is formed through photoetching, and aluminum ions are injected into a specific area to form a P-type well region 120; then, forming a mask through photoetching, and selecting a specific area to implant nitrogen ions to form an N-type source area 130; then, a mask is formed through photoetching, and aluminum ions are implanted into a selected specific area to form a P-type body contact area 140; finally, high temperature annealing treatment is carried out to activate the impurities. Thus, a semiconductor functional module of the semiconductor power device can be obtained.
S200: and forming a first-level gate insulating sub-layer on one side of the epitaxial layer, the well region, the source region and the body contact region, which is far away from the substrate.
In this step, referring to fig. 3, a first gate insulating sub-layer 210 is formed on the side of the epitaxial layer 110, the well region 120, the source region 130 and the body contact region 140 remote from the substrate 100.
The specific material of the first gate insulating sublayer 210 is not particularly limited, and may be selected by one skilled in the art according to the specific use requirement of the semiconductor power device according to the embodiment of the present invention. In some embodiments of the present invention, the first gate insulating sub-layer 210 may be formed of silicon dioxide, and thus, the first gate insulating sub-layer 210 and the second gate insulating sub-layer 220 obtained by performing a high temperature oxidation treatment on the polysilicon sub-layer may form a gate insulating layer with a uniform thickness.
The specific method of forming the first gate insulating sublayer 210 according to an embodiment of the present invention is not particularly limited, and may be selected by one skilled in the art according to the specific material of the gate insulating sublayer. In some embodiments of the present invention, the insulating sub-layer 210 may be silicon dioxide generated by a thermal oxidation process. In this way, a gate insulating sub-layer with uniform thickness and a smooth surface can be formed on the side of the epitaxial layer 110, the well region 120, the source region 130 and the body contact region 140 away from the substrate 100.
The specific thickness of the first gate insulating sub-layer 210 is not particularly limited, and may be designed and adjusted by one skilled in the art according to the specific step number of the gate insulating layer of the multi-step structure according to the embodiment of the present invention. In some embodiments of the present invention, taking the second gate insulating layer structure as an example, the thickness of the first gate insulating sub-layer 210 may be 50 nm. Thus, a semiconductor power device with better use reliability can be obtained.
S300: and forming a second step gate insulating sub-layer and a first polycrystalline silicon sub-layer on the side of the first step gate insulating sub-layer far away from the substrate.
In this step, a second sub-gate insulating layer 220 and a first sub-polysilicon layer 320 are formed on the side of the first sub-gate insulating layer 210 away from the substrate 100. The specific method of forming the second sub-gate insulating layer 220 and the first sub-polysilicon layer 320 according to the embodiment of the present invention is not particularly limited, and those skilled in the art may select a specific material according to the second sub-gate insulating layer 220. In some embodiments of the present invention, referring to fig. 18, step S300 may further include S310, S320, and S330, which are described in detail below:
s310: and sequentially forming a first polysilicon layer and a patterned protective layer on the side of the first gate insulating sublayer far away from the substrate.
In this step, the first polysilicon layer 310 and the patterned protection layer 400 are sequentially formed on the side of the first gate insulating sublayer 210 away from the substrate 100. The inventors of the present application have found that the first polysilicon layer 310 can effectively protect the first gate insulating sublayer 210 from the etching, thereby improving the product reliability, and subsequently, the patterned protection layer 400 can be used as a mask to select a specific region for performing a high temperature oxidation process on the first polysilicon layer 310.
The specific thickness of the first polysilicon layer 310 is not particularly limited according to the embodiment of the present invention, and may be adjusted by those skilled in the art according to the use requirements and practical manufacturing conditions of the semiconductor power device. In some embodiments of the present invention, taking the second gate insulating layer structure as an example, the thickness of the first polysilicon layer 310 may be 100 nm. Thus, the first polysilicon layer 310 with the above thickness can more effectively protect the first gate insulating sublayer 210, and can be used as a part of the gate insulating layer to improve the reliability of the semiconductor power device.
According to an embodiment of the present invention, a specific material of the protection layer 400 is not particularly limited as long as the protection layer 400 of the material can effectively protect a portion of the first polysilicon layer 310 from the high temperature oxidation treatment, and a person skilled in the art can select the protection layer according to specific process conditions of the high temperature oxidation treatment. In some embodiments of the present invention, the protective layer 400 may be selected from silicon nitride or aluminum oxide. Thus, the structure of the passivation layer 400 made of the above materials is more compact, so that the oxide gas can be prevented from entering the polysilicon layer, and a portion of the first polysilicon layer 310 can be more effectively protected from the high temperature oxidation process.
The specific thickness of the protection layer 400 is also not particularly limited according to the embodiment of the present invention, as long as the protection layer 400 having the thickness can protect a portion of the first polysilicon layer 310 from the high temperature oxidation treatment, and those skilled in the art can select the specific process conditions according to the high temperature oxidation treatment. In some embodiments of the present invention, the thickness of the protective layer 400 may be not less than 150 nm. Thus, by using the protection layer 400 with the above thickness, a portion of the first polysilicon layer 310 can be more effectively protected from the high temperature oxidation process.
The specific method of forming the first polysilicon layer 310 and the protective layer 400 having the patterning according to the embodiment of the present invention is not particularly limited, and those skilled in the art may select the method according to the specific materials of the first polysilicon layer 310 and the protective layer 400. In some embodiments of the present invention, step S310 may further include: referring to fig. 4, a first polysilicon layer 310 is formed by a chemical vapor deposition process on a side of the first gate insulating sub-layer 210 away from the substrate 100; referring again to fig. 5, a dense layer 410 is formed by a chemical vapor deposition process on a side of the first polysilicon layer 310 away from the substrate 100; referring then to fig. 6, the dense layer 410 is photolithographically processed to form a patterned protective layer 400. In this way, the first polysilicon layer 310 and the protection layer 400 having the patterning can be formed more efficiently and accurately.
S320: and carrying out high-temperature oxidation treatment on the area of the first polycrystalline silicon layer which is not protected by the protective layer.
In this step, a high temperature oxidation process is performed on the region of the first polysilicon layer 310 not protected by the protection layer 400, so as to obtain the second gate insulating sublayer 220 and the first polysilicon sublayer 320, and the product structure obtained in this step is shown in fig. 7. Specifically, the high-temperature oxygen may oxidize the polysilicon of the partially exposed first polysilicon layer 310 into silicon dioxide, so as to directly form the second gate insulating sublayer 220 having a specific pattern in a region not protected by the protection layer 400, and the gate insulating sublayer obtained by the high-temperature oxidation treatment has a uniform thickness and a flat surface, so that the semiconductor power device may have good long-term reliability.
The inventors of the present application have unexpectedly found that although the first polysilicon layer 310 covered by the protective layer 400 is not oxidized by the gas, at the interface between the second gate insulating sublayer 220 and the first polysilicon sublayer 320, since the oxygen gas has the ability of lateral diffusion, a portion of the polysilicon at the interface is oxidized, thereby forming a beveled interface like a "bird's beak" peculiar to local oxidation, and refer to fig. 7 in particular.
According to an embodiment of the present invention, specific conditions of the high temperature oxidation process, such as temperature and atmosphere type, are not particularly limited, and may be selected and adjusted by one skilled in the art according to the specific material and thickness of the first polysilicon layer 310. In some embodiments of the present invention, the temperature of the high temperature oxidation treatment may be 800 to 1200 degrees celsius, and is performed in a pure oxygen gas or a high purity oxygen atmosphere. Thus, by the high temperature oxidation treatment under the above process conditions, the second gate insulating sublayer 220 with a more uniform thickness and a smoother surface can be obtained. It should be noted that "high purity oxygen" as used herein refers to oxygen having a purity of more than 99.995 v/v%, and the impurities are only N which does not affect the oxidation reaction2And Ar, etc.
According to an embodiment of the present invention, the specific cross-sectional shape of the second step gate insulating sublayer 220 is not particularly limited, and specifically, such as a stripe shape, a circular shape, a square shape, or the like, and those skilled in the art can design accordingly according to the specific cross-sectional shapes of the well region 120, the source region 130, and the body contact region 140. In some embodiments of the present invention, the second sub-gate insulating layer 220 may have a strip-shaped cross-sectional shape, so that the strip-shaped cross-sectional gate insulating layer can better insulate the gate electrode from the strip-shaped semiconductor functional modules. In other embodiments of the present invention, the second sub-gate insulating layer 220 may have a circular cross-sectional shape, so that the gate insulating layer with a circular cross-section may better insulate the gate electrode from the annularly distributed semiconductor function modules.
S330: and removing the protective layer.
In this step, the protective layer 400 is removed from the surface of the first polysilicon sub-layer 320, so that the unoxidized first polysilicon sub-layer 320 may remain as a portion of the gate electrode. The specific method for removing the protective layer 400 according to the embodiment of the present invention is not particularly limited, and those skilled in the art may select the method according to the specific materials of the protective layer 400 and the first polysilicon sublayer 320. In some embodiments of the present invention, the method of removing the protection layer 400 may be selected from wet etching. Thus, the protective layer 400 remained on the surface of the first polysilicon sublayer 320 can be effectively removed by the above method, and the etching solution of the wet etching can not damage the first gate insulating sublayer 210 due to the protective effect of the first polysilicon sublayer 320, so that the long-term reliability of the semiconductor power device can be further improved.
In some embodiments of the present invention, a two-step gate insulating layer structure as shown in fig. 8 formed of the first and second gate insulating sub-layers 210 and 220 may be obtained through steps S310 to S330. In other embodiments of the present invention, steps S310 to S330 may be repeated, that is, the deposition of the polysilicon layer, the formation of the patterned protection layer, the local high temperature oxidation treatment and the removal of the protection layer are repeated, so that the plurality of second gate insulating sub-layers 220 and the plurality of first polysilicon sub-layers 320 may be formed on the side of the first gate insulating sub-layers 210 away from the substrate 100, and thus a third-order or more than third-order gate insulating layer structure formed by the first gate insulating sub-layers 210 and the plurality of second gate insulating sub-layers 220 as shown in fig. 9 may be obtained. It should be noted that, as used herein, the term "plurality" specifically means two or more.
S400: and forming a second polysilicon sublayer on one side of the second gate insulating sublayer and the first polysilicon sublayer, which is far away from the substrate, and photoetching the second polysilicon sublayer and the first polysilicon sublayer to form a gate.
In some embodiments of the present invention, taking the structure of the second gate insulating layer as an example, a second polysilicon sublayer 330 is formed on the second gate insulating sublayer 220 and the first polysilicon sublayer 320 on the side away from the substrate 100, and the structure of the semi-finished product of this step is shown in fig. 10; the second polysilicon sub-layer 330 and the first polysilicon sub-layer 320 are subjected to photolithography to form a gate electrode 300, and the structure of the product of this step is shown in fig. 11. In this way, the unoxidized first polysilicon sublayer 320 and the second polysilicon sublayer 330 may be combined together, and then may be subjected to a photolithography process to obtain the gate electrode 300 of the semiconductor power device. In fig. 11, the gate electrode 300 is formed of a first polysilicon sublayer 320 (not shown) and a second polysilicon sublayer 330 (not shown).
According to an embodiment of the present invention, a specific method of forming the second polysilicon layer 330 is not particularly limited, and those skilled in the art may select the second polysilicon layer 330 according to a specific material. In some embodiments of the present invention, the second polysilicon layer 330 may be formed by a chemical vapor deposition process. Thus, the second polysilicon layer 330 can be formed more efficiently and accurately by the above method.
According to the embodiment of the present invention, the specific thickness of the second polysilicon layer 330 is not particularly limited as long as the second polysilicon layer 330 with the thickness can effectively constitute the gate of the semiconductor power device, and those skilled in the art can adjust the thickness according to the use requirements and actual manufacturing conditions of the semiconductor power device. In some embodiments of the present invention, taking the second gate insulating layer structure as an example, the thickness of the second polysilicon layer 330 may be 500 nm. Thus, the second polysilicon layer 330 with the above thickness can be used as a part of the gate insulating layer to improve the reliability of the semiconductor power device.
In some embodiments of the present invention, referring to fig. 19, the manufacturing method may further include steps S500, S600, and S700, so that a semiconductor power device with more complete structure and function may be obtained, and the steps are described in detail below:
s500: and forming an isolation dielectric layer on the first gate insulating sublayer and one side of the gate electrode, which is far away from the substrate.
In this step, an isolation dielectric layer 500 is formed on the first gate insulating sublayer 210 and the side of the gate electrode 300 away from the substrate 100, and the structure of the product obtained in this step is shown in fig. 12.
The specific material of the isolation dielectric layer 500 is not particularly limited, and may be selected by one skilled in the art according to the specific application requirements of the semiconductor power device and the specific material of the gate 200 according to the embodiment of the present invention. In some embodiments of the present invention, the isolation dielectric layer 500 may be a composite structure of a layer of silicon dioxide and a layer of borophosphosilicate glass. In other embodiments of the present invention, the isolation dielectric layer 500 may be a composite structure of a layer of silicon nitride and a layer of borophosphosilicate glass. Thus, by adopting the composite structure composed of different materials, the isolation effect of the isolation dielectric layer 500 can be better, and the reliability of the semiconductor power device is better.
The specific method for forming the isolation dielectric layer 500 according to the embodiment of the present invention is not particularly limited, and those skilled in the art may select the isolation dielectric layer 500 according to the specific material. In some embodiments of the present invention, a layer of silicon dioxide or silicon nitride, a layer of borophosphosilicate glass may be sequentially deposited on the first gate insulating sub-layer 210 and the side of the gate electrode 300 away from the substrate 100. Thus, the isolation dielectric layer 500 having a composite structure can be formed, so that the isolation effect of the isolation dielectric layer 500 is better.
S600: and photoetching the isolation dielectric layer and the first-stage gate insulating sublayer and forming a contact hole, forming a source electrode on one side of the contact hole and the isolation dielectric layer, which is far away from the substrate, and forming a drain electrode on the other side of the substrate.
In this step, the isolation dielectric layer 500 and the first gate insulating sub-layer 210 are subjected to photolithography, and a contact hole 600 and a gate insulating layer 200 are formed, and the structure of the semi-finished product of this step is shown in fig. 13; forming a source 700 on the contact hole 600 and the side of the isolation dielectric layer 500 away from the substrate 100, and referring to fig. 14 for the structure of the product of this step; the drain 800 is formed on the other side of the substrate 100, and the structure of the product of this step is shown in fig. 15. In fig. 13, the gate insulating layer 200 is composed of a first gate insulating sub-layer 210 (not shown) and a second gate insulating sub-layer 220 (not shown).
According to the embodiment of the present invention, the specific cross-sectional shape of the isolation dielectric layer 500 after photolithography is not particularly limited, such as stripe, circle, square, etc., and those skilled in the art can design accordingly according to the specific cross-sectional shape of the second gate insulation sublayer 220. In some embodiments of the present invention, the cross-sectional shape of the isolation dielectric layer 500 may be a stripe. In other embodiments of the present invention, the cross-sectional shape of the isolation dielectric layer 500 may be circular.
According to the embodiment of the present invention, the specific materials of the source 700 and the drain 800 are not particularly limited as long as the source and the drain formed by the materials and the gate can form the switch module of the semiconductor power device, and those skilled in the art can design and select the switch module according to the specific requirements of the semiconductor power device, and are not described herein again. According to the embodiment of the present invention, the specific method for forming the source electrode 700 and the drain electrode 800 is also not particularly limited, and those skilled in the art may select the method according to the specific materials of the source electrode 700 and the drain electrode 800, which will not be described herein again.
In summary, according to the embodiments of the present invention, the present invention provides a method for manufacturing a semiconductor power device, which can obtain a multi-level gate insulating layer structure by performing a high temperature oxidation treatment on a polysilicon sub-layer by layer, thereby making a surface of the multi-level gate insulating layer smoother, avoiding adverse effects of an etching method that is likely to cause surface unevenness or residual etchant, and accurately designing a step size by adjusting a size of each gate insulating sub-layer, thereby improving a reliability of the semiconductor power device.
In another aspect of the invention, a semiconductor power device is provided. According to the embodiment of the invention, the semiconductor power device is manufactured by the method.
In summary, according to the embodiments of the present invention, the present invention provides a semiconductor power device, wherein the surface of the multi-level gate insulating layer is smoother and the dimensional accuracy is higher, so that the long-term reliability of the semiconductor power device is better. It will be appreciated by those skilled in the art that the features and advantages described above with respect to the method of fabricating a semiconductor power device are still applicable to the semiconductor power device and will not be described in detail herein.
In another aspect of the invention, a semiconductor power device is provided. The semiconductor power device of the present invention will be described in detail with reference to fig. 16 to 17.
According to an embodiment of the present invention, referring to fig. 16, the semiconductor power device includes: a substrate 100, an epitaxial layer 110, a well region 120, a source region 130, a body contact region 140, a gate insulating layer 200 and a gate electrode 300; wherein the epitaxial layer 110 is disposed on one side of the substrate 100; the well region 120 is disposed on a side of the epitaxial layer 110 away from the substrate 100, and is axisymmetrical with a central line AA' of the substrate 100; the source region 130 is disposed at a side of the well region 120 away from the substrate 100, and is axisymmetrical with a central line AA' of the substrate 100; the body contact region 140 is disposed on a side of the well region 120 away from the substrate 100, and is axisymmetrical with the center line AA' of the substrate 100; the gate insulating layer 200 is disposed on a side of the well region 120 and the source region 130 away from the substrate 100, and the gate insulating layer 200 is a multi-level structure composed of a plurality of gate insulating sublayers and is formed of silicon dioxide; and the gate electrode 300 is disposed on a side of the gate insulating layer 200 away from the substrate 100, and the gate electrode 300 is composed of a plurality of polysilicon sublayers. It should be noted that fig. 16 is only used for reference and does not limit the gate insulating layer 200 of the semiconductor power device to be a two-step structure; all the "multi-step structure" herein specifically means a symmetrical multi-step structure, including but not limited to two steps, and those skilled in the art can design three or more steps according to actual needs.
The inventor of the application finds that the multi-level gate insulating layer structure of the semiconductor power device can be obtained by carrying out high-temperature oxidation treatment on the polycrystalline silicon sub-layer by layer, so that the surface of the multi-level gate insulating layer is smoother, the adverse effect of uneven surface of the gate insulating layer or residual corrosive agent is avoided, and the use reliability of the semiconductor power device can be improved.
It should be noted that, the semiconductor power device includes other necessary structures or compositions, such as an isolation dielectric layer, a source electrode, a drain electrode, etc., besides the above structures, and those skilled in the art can supplement and design the semiconductor power device according to the specific use requirements of the semiconductor power device. In some embodiments of the present invention, referring to fig. 17, the semiconductor power device may further include: an isolation dielectric layer 500, a source 700 and a drain 800; wherein, the isolation dielectric layer 500 is disposed on the gate electrode 300 and one side of the gate insulating layer 300 far away from the substrate 100; the source electrode 700 is arranged on one side of the isolation dielectric layer 500, the source region 130 and the body contact region 140, which is far away from the substrate 100; and the drain 800 is disposed on the other side of the substrate 100. Thus, the semiconductor power device has more complete structure and function.
In summary, according to the embodiments of the present invention, the present invention provides a semiconductor power device, wherein the surface of the multi-level gate insulating layer is smoother and the dimensional accuracy is higher, so that the long-term reliability of the semiconductor power device is better.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A method of fabricating a semiconductor power device, comprising:
sequentially forming an epitaxial layer, a well region, a source region and a body contact region on one side of a substrate, wherein the epitaxial layer is arranged on one side of the substrate, the well region is symmetrically arranged on one side, far away from the substrate, of the epitaxial layer by taking the central line of the substrate as an axis, and the source region and the body contact region are respectively and independently arranged on one side, far away from the substrate, of the well region by taking the central line of the substrate as an axis;
forming a first step gate insulating sub-layer on one side, far away from the substrate, of the epitaxial layer, the well region, the source region and the body contact region;
forming a second sub-gate insulating layer and a first sub-polysilicon layer on the side, far away from the substrate, of the first sub-gate insulating layer;
forming a second polysilicon sublayer on one side, far away from the substrate, of the second step gate insulating sublayer and the first polysilicon sublayer, and photoetching the second polysilicon sublayer and the first polysilicon sublayer to form a gate;
wherein the step of forming the second sub-layer of gate insulation and the first sub-layer of polysilicon further comprises:
sequentially forming a first polysilicon layer and a patterned protective layer on one side of the first gate insulating sublayer away from the substrate;
performing high-temperature oxidation treatment on the region, which is not protected by the protective layer, of the first polycrystalline silicon layer so as to obtain a second gate insulating sublayer and a first polycrystalline silicon sublayer, wherein the temperature of the high-temperature oxidation treatment is 800-1200 ℃; and
and removing the protective layer.
2. The method of claim 1, wherein a plurality of second sub-layers of gate insulation and a plurality of first sub-layers of polysilicon are formed on a side of the first sub-layers of gate insulation remote from the substrate.
3. The method according to claim 1, wherein said high temperature oxidation treatment is carried out under an atmosphere of high purity oxygen, wherein said high purity oxygen is oxygen having a purity of greater than 99.995 v/v%.
4. The method of claim 1, wherein the protective layer is selected from silicon nitride or aluminum oxide.
5. The method of claim 1, wherein the protective layer has a thickness of not less than 150 nm.
6. The method of claim 1, wherein the step of forming a patterned protective layer comprises:
forming a compact layer on one side of the first polycrystalline silicon layer far away from the substrate;
and carrying out photoetching treatment on the compact layer to form the patterned protective layer.
7. The method of claim 1, wherein the protective layer is removed by wet etching.
8. The method of claim 1, wherein the substrate is formed of silicon carbide.
9. A semiconductor power device manufactured by the method according to any one of claims 1 to 8.
10. A semiconductor power device, comprising:
a substrate;
the epitaxial layer is arranged on one side of the substrate;
the well region is arranged on one side, away from the substrate, of the epitaxial layer and takes the central line of the substrate as an axis;
the source region is arranged on one side, away from the substrate, of the well region in an axisymmetric manner by taking the central line of the substrate as an axis;
the body contact region is arranged on one side of the well region away from the substrate in an axisymmetric manner by taking the central line of the substrate as an axis;
the grid insulating layer is arranged on one side, far away from the substrate, of the well region and the source region, is of a multi-stage structure consisting of a plurality of grid insulating sublayers and is formed by silicon dioxide; and
the grid electrode is arranged on one side, far away from the substrate, of the grid insulation layer and consists of a plurality of polysilicon sublayers;
in the gate insulating sublayer and the polycrystalline silicon sublayer which are arranged on the same layer, a material for forming the gate insulating sublayer is obtained by performing high-temperature oxidation treatment on the material of the polycrystalline silicon sublayer, and the temperature of the high-temperature oxidation treatment is 800-1200 ℃.
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