CN112185817A - LDMOS device and forming method thereof - Google Patents
LDMOS device and forming method thereof Download PDFInfo
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- CN112185817A CN112185817A CN202011038210.1A CN202011038210A CN112185817A CN 112185817 A CN112185817 A CN 112185817A CN 202011038210 A CN202011038210 A CN 202011038210A CN 112185817 A CN112185817 A CN 112185817A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The application discloses a method for forming an LDMOS device and the LDMOS device, wherein the method comprises the following steps: providing a substrate, wherein a surrounding STI structure is formed in the substrate, an active region is arranged in the surrounding STI structure, gate oxide is formed on the active region, a grid electrode is formed on the gate oxide, a well doping region and a drift region are formed in the active region, a source electrode and a channel leading-out electrode are formed in the well doping region, and a drain electrode is formed in the drift region; forming a hard mask layer with tensile stress on the surfaces of the substrate, the grid and the grid oxide; forming an interlayer dielectric layer on the surface of the hard mask layer with tensile stress; forming a first metal connecting wire, a second metal connecting wire and a third metal connecting wire in the interlayer dielectric layer and the hard mask layer of tensile stress, wherein the bottom end of the first metal connecting wire is connected with the source electrode and the channel leading-out electrode, the bottom end of the second metal connecting wire is connected with the grid electrode, and the bottom end of the third metal connecting wire is connected with the drain electrode; a thermal treatment is performed during which dangling bonds at the surface of the gate are neutralized by deuterium gas passing through the tensile-stressed hard mask layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a method for forming a laterally-diffused metal-oxide semiconductor (LDMOS) device and an LDMOS device.
Background
The LDMOS device is easily compatible with a manufacturing process of a Complementary Metal Oxide Semiconductor (CMOS) device, has the characteristics of high voltage resistance, large current driving capability, extremely low power consumption and the like, and is widely applied to the fields of display driving, power management and the like.
The Safe Operating Area (SOA) is a safe operating area, which is usually expressed by a coordinate plane and forms a certain limit to the current, voltage and power consumption of a device in order to ensure the safe operation of the device and to have higher stability and longer service life.
The LDMOS provided in the related art has a Hot Carrier Injection (HCI) SOA problem. The HCI SOA problem refers to the parameter degradation of the device under operating conditions due to hot carrier injection, but it still operates within the SOA corresponding to the safe operating range.
The reliability of the LDMOS device provided in the related art is poor due to the HCI SOA problem.
Disclosure of Invention
The application provides a method for forming an LDMOS device and the LDMOS device, which can solve the problem that the reliability of the LDMOS device provided in the related art is poor due to the fact that the HCI SOA problem exists.
In one aspect, an embodiment of the present application provides a method for forming an LDMOS device, including:
providing a substrate, wherein a surrounding Shallow Trench Isolation (STI) structure is formed in the substrate, an Active Area (AA) of the LDMOS device is arranged in the surrounding STI structure, a gate oxide is formed on the active area, a gate electrode is formed on the gate oxide, a well doped region and a drift region are formed in the active area, a source electrode and a channel extraction electrode are formed in the well doped region, and a drain electrode is formed in the drift region;
forming a tensile hard mask layer on the surfaces of the substrate, the grid and the grid oxide;
forming an interlayer dielectric layer on the surface of the hard mask layer with the tensile stress;
forming a first metal connecting wire, a second metal connecting wire and a third metal connecting wire in the interlayer dielectric layer and the tensile stress hard mask layer, wherein the bottom end of the first metal connecting wire is connected with the source electrode and the channel leading-out electrode, the bottom end of the second metal connecting wire is connected with the grid electrode, and the bottom end of the third metal connecting wire is connected with the drain electrode;
and carrying out heat treatment, wherein during the heat treatment, deuterium gas penetrates through the hard mask layer with tensile stress to neutralize the dangling bond on the surface of the gate.
Optionally, the tensile-stressed hard mask layer comprises a tensile-stressed silicon nitride (SiN) layer.
Optionally, forming a hard mask layer with tensile stress on the surfaces of the substrate, the gate and the gate oxide, includes:
depositing silicon nitride above the substrate, the grid electrode and the grid oxide by at least two Chemical Vapor Deposition (CVD) processes to form the tensile stress silicon nitride layer;
wherein each of said CVD processes is followed by irradiation with Ultraviolet (UV) light.
Optionally, the performing heat treatment includes:
the heat treatment is performed in a furnace tube.
Optionally, the temperature of the heat treatment is 300 degrees celsius (° c) to 600 degrees celsius.
Optionally, the forming a first metal wire and a second metal wire in the interlayer dielectric layer and the hard mask layer with tensile stress includes:
etching is carried out, the hard mask layer and the interlayer dielectric layer of the tensile stress in the first target area, the second target area and the third target area are removed, a first through hole, a second through hole and a third through hole are formed respectively, and the preset areas of the source electrode and the channel leading-out electrode, the preset area of the grid electrode and the preset area of the drain electrode are exposed;
forming a metal layer on the interlayer dielectric layer, wherein the metal layer fills the first through hole, the second through hole and the third through hole;
and flattening the metal layer, and removing the metal layer outside the first through hole, the second through hole and the third through hole, wherein the metal layer in the first through hole forms the first metal connecting line, the metal layer in the second through hole forms the second metal connecting line, and the metal layer in the third through hole forms the third metal connecting line.
In another aspect, an embodiment of the present application provides an LDMOS device, including:
the LDMOS device comprises a substrate, wherein a surrounding STI structure is formed in the substrate, an active region of the LDMOS device is arranged in the surrounding STI structure, a well doping region and a drift region are formed in the active region, a source electrode and a channel leading-out electrode are formed in the well doping region, and a drain electrode is formed in the drift region;
the gate oxide is formed on the substrate of the active region;
the grid electrode is formed on the grid oxide, and dangling bonds on the surface of the grid electrode are neutralized by deuterium gas;
a tensile hard mask layer formed on the surfaces of the substrate, the gate and the gate oxide;
the interlayer dielectric layer is formed on the hard mask layer with the tensile stress;
the first metal connecting wire is formed in the interlayer dielectric layer and the hard mask layer of the tensile stress, and the bottom end of the first metal connecting wire is connected with the source electrode and the channel leading-out electrode;
the second metal connecting wire is formed in the interlayer dielectric layer and the hard mask layer of the tensile stress, and the bottom end of the second metal connecting wire is connected with the grid;
and the third metal connecting wire is formed in the interlayer dielectric layer and the hard mask layer of the tensile stress, and the bottom end of the third metal connecting wire is connected with the drain electrode.
Optionally, the tensile-stressed hard mask layer includes a tensile-stressed silicon nitride layer.
Optionally, the gate oxide and the gate electrode form a step-shaped structure, and the gate oxide forms a bottom step of the step-shaped structure.
Optionally, the gate oxide is a step oxide (step oxide).
The technical scheme at least comprises the following advantages:
after a grid electrode and a grid oxide of the LDMOS device are formed, a hard mask layer with tensile stress is formed on the surfaces of a substrate, the grid electrode and the grid oxide, and after an interlayer dielectric layer and a metal connecting wire in the interlayer dielectric layer are formed, deuterium gas penetrates through the hard mask layer with tensile stress and a dangling bond on the surface of the grid electrode in the heat treatment process, so that the influence of HCI is reduced, the problem of HCI of the LDMOS device is solved to a certain extent, and the reliability of the device is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flow chart of a method for forming an LDMOS device according to an exemplary embodiment of the present application;
fig. 2 to 6 are diagrams illustrating a process of forming an LDMOS device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for forming an LDMOS device provided by an exemplary embodiment of the present application is shown, the method including:
Referring to fig. 2, a schematic cross-sectional view is shown prior to forming a tensile stressed hard mask layer. As shown in fig. 2, a surrounding STI structure 220 is formed in a substrate 210, an active region of an LDMOS device is formed in the surrounding STI structure 220, a gate oxide 230 is formed on the active region, a gate 240 is formed on the gate oxide 230, a well doped region 201 and a drift region 202 are formed in the active region, a source 204 and a channel extractor 205 are formed in the well doped region 201, and a drain 203 is formed in the drift region 202.
Wherein, the drift region 202, the source 204 and the drain 203 are doped with a first type of impurity; the gate electrode 240 and the extraction electrode 205 are doped with the second type impurity. Wherein, if the first type impurity is a p (positive) type impurity (e.g. boron element), the second type impurity is an n (negative) type impurity (e.g. phosphorus element); if the first type of impurity is an N-type impurity, the second type of impurity is a P-type impurity.
Optionally, a sidewall 241 is formed on the peripheral side of the gate electrode 240, and the sidewall 241 includes silicon dioxide (SiO)2)。
And 102, forming a hard mask layer with tensile stress on the surfaces of the substrate, the grid and the grid oxide.
Referring to fig. 3, a schematic cross-sectional view of a hard mask layer forming a tensile stress is shown. Illustratively, as shown in fig. 3, the tensile hard mask layer 250 comprises a tensile silicon nitride layer, which may be formed by depositing silicon nitride over the substrate 210, the gate electrode 240, and the gate oxide 230 by at least two CVD processes. Wherein after each CVD process, UV light irradiation is performed.
The tensile stressed silicon nitride layer 250 may be formed by depositing silicon nitride on the surfaces of the substrate 210, gate electrode 240, and gate oxide 230 by a CVD process.
And 103, forming an interlayer dielectric layer on the surface of the hard mask layer with tensile stress.
Referring to fig. 4, a cross-sectional view of an interlevel dielectric layer formed on the surface of a tensile-stressed hard mask layer is shown. Illustratively, as shown in fig. 4, the interlayer dielectric layer 260 includes a silicon dioxide layer, and the interlayer dielectric layer 260 may be formed by depositing silicon dioxide on the surface of the tensile-stressed hard mask layer 250 through a CVD process.
And 104, forming a first metal connecting wire, a second metal connecting wire and a third metal connecting wire in the interlayer dielectric layer and the tensile stress hard mask layer, wherein the bottom end of the first metal connecting wire is connected with the source electrode and the channel leading-out electrode, the bottom end of the second metal connecting wire is connected with the grid electrode, and the bottom end of the third metal connecting wire is connected with the drain electrode.
Referring to fig. 5, a schematic cross-sectional view of a first metal line, a second metal line and a third metal line formed in an interlayer dielectric layer and a tensile hard mask layer is shown.
Illustratively, as shown in fig. 5, the step 104 of forming the first metal line, the second metal line and the third metal line in the interlayer dielectric layer and the tensile hard mask layer includes, but is not limited to: etching is carried out, the hard mask layer 250 and the interlayer dielectric layer 260 which are in tensile stress of the first target area, the second target area and the third target area are removed, a first through hole, a second through hole and a third through hole (not shown in figure 5) are formed respectively, and the predetermined areas of the source electrode 204 and the channel leading-out electrode 205, the predetermined area of the grid electrode 240 and the predetermined area of the drain electrode 203 are exposed; forming a metal layer on the interlayer dielectric layer 260, wherein the metal layer fills the first through hole, the second through hole and the third through hole; and flattening the metal layer, and removing the metal layers outside the first through hole, the second through hole and the third through hole, wherein the metal layer in the first through hole forms a first metal connecting line 271, the metal layer in the second through hole forms a second metal connecting line 272, and the metal layer in the third through hole forms a third metal connecting line 273.
The first target region is a region corresponding to the first metal wire 271, the second target region is a region corresponding to the second metal wire 272, the third target region is a region corresponding to the third metal wire 273, the bottom end of the first metal wire 271 is connected to the source 204 and the channel extraction electrode 205, the bottom end of the second metal wire 272 is connected to the gate 240, and the bottom end of the third metal wire 273 is connected to the drain 203.
If the first metal wire 271, the second metal wire 272, and the third metal wire 273 include tungsten (W), tungsten may be deposited on the dielectric layer 260 by a CVD process to form a metal layer; if the first metal wire 271, the second metal wire 272, and the third metal wire 273 include aluminum (Al), aluminum may be deposited on the dielectric layer 260 through a Physical Vapor Deposition (PVD) process to form a metal layer; if the first metal line 271, the second metal line 272, and the third metal line 273 include copper (Cu), copper may be grown on the dielectric layer 260 through an electroplating process to form a metal layer.
Optionally, in the above step, the metal layer may be planarized by a Chemical Mechanical Polishing (CMP) process.
Referring to fig. 6, a schematic cross-sectional view of the heat treatment is shown. As shown in fig. 6, since deuterium gas can penetrate through the hard mask layer 250 with tensile stress, during the thermal treatment, the influence of HCI is reduced by the deuterium gas penetrating through the hard mask layer 250 with tensile stress, thereby neutralizing dangling bonds on the surface of the gate 240, and the problem of HCI SOA of the LDMOS device is solved to a certain extent.
Optionally, in step 105, the heat treatment may be performed in a furnace tube; optionally, the temperature of the heat treatment is 300 to 600 degrees celsius (which may be 475 degrees celsius, for example).
In summary, in the embodiment of the present application, after the gate and the gate oxide of the LDMOS device are formed, the hard mask layer with tensile stress is formed on the surfaces of the substrate, the gate and the gate oxide, and after the interlayer dielectric layer and the metal connecting wire in the interlayer dielectric layer are formed, deuterium gas penetrates through the hard mask layer with tensile stress and the dangling bond on the surface of the gate in the heat treatment process, so that the influence of HCI is reduced, the problem of HCI SOA of the LDMOS device is solved to a certain extent, and the reliability of the device is improved.
Referring to fig. 6, a cross-sectional view of an LDMOS device provided by an exemplary embodiment of the present application is shown, which can be fabricated by the above method, and which includes:
the LDMOS device comprises a substrate 210, wherein a surrounding STI structure 220 is formed in the substrate, an active region of the LDMOS device is arranged in the surrounding STI structure 220, a well doped region 201 and a drift region 202 are formed in the active region, a source 204 and a channel extraction electrode 205 are formed in the well doped region 201, and a drain 203 is formed in the drift region 202.
And a gate oxide 230 formed on the substrate 210 of the active region.
And a gate electrode 240 formed on the gate oxide 230, wherein dangling bonds on the surface of the gate electrode 240 are neutralized by deuterium.
A tensile hard mask layer 250 formed on the surfaces of the substrate 210, the gate 240 and the gate oxide 230.
An interlevel dielectric layer 260 is formed on the tensile stressed hard mask layer 250.
A first metal line 271 formed in the interlayer dielectric layer 260 and the tensile hard mask layer 250 has a bottom end connected to the source 204 and the channel drain 205.
A second metal line 272 is formed in the interlayer dielectric layer 260 and the tensile hard mask layer 250, and the bottom end thereof is connected to the gate 240.
A third metal line 273, which is formed in the interlayer dielectric layer 260 and the tensile hard mask layer 250, is connected to the drain 203 at the bottom end thereof.
Wherein, the drift region 202, the source 204 and the drain 203 are doped with a first type of impurity; the gate electrode 240 and the extraction electrode 205 are doped with the second type impurity. Wherein, if the first type impurity is a P-type impurity (e.g. boron element), the second type impurity is an N-type impurity (e.g. phosphorus element); if the first type of impurity is an N-type impurity, the second type of impurity is a P-type impurity.
Optionally, a sidewall 241 is formed on the peripheral side of the gate electrode 240, and the sidewall 241 includes silicon dioxide.
Optionally, the tensile-stressed hard mask layer 250 comprises a tensile-stressed silicon nitride layer.
Optionally, the gate oxide 230 and the gate electrode 240 form a step-shaped structure, and the gate oxide 230 forms a bottom step of the step-shaped structure.
Optionally, the gate oxide 230 is a step-type gate oxide.
Optionally, the first metal wire 271, the second metal wire 272, and the third metal wire 273 include tungsten, aluminum, or copper.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A method for forming an LDMOS device, comprising:
providing a substrate, wherein a surrounding STI structure is formed in the substrate, an active region of the LDMOS device is arranged in the surrounding STI structure, a gate oxide is formed on the active region, a gate electrode is formed on the gate oxide, a well doped region and a drift region are formed in the active region, a source electrode and a channel leading-out electrode are formed in the well doped region, and a drain electrode is formed in the drift region;
forming a hard mask layer with tensile stress on the surfaces of the substrate, the grid and the grid oxide;
forming an interlayer dielectric layer on the surface of the hard mask layer with the tensile stress;
forming a first metal connecting wire, a second metal connecting wire and a third metal connecting wire in the interlayer dielectric layer and the tensile stress hard mask layer, wherein the bottom end of the first metal connecting wire is connected with the source electrode and the channel leading-out electrode, the bottom end of the second metal connecting wire is connected with the grid electrode, and the bottom end of the third metal connecting wire is connected with the drain electrode;
and carrying out heat treatment, wherein during the heat treatment, deuterium gas penetrates through the hard mask layer with tensile stress to neutralize the dangling bond on the surface of the gate.
2. The method of claim 1, wherein said tensile hard mask layer comprises a tensile silicon nitride layer.
3. The method of claim 2, wherein forming a tensile hard mask layer on the surface of the substrate, the gate and the gate oxide comprises:
depositing silicon nitride over the substrate, the gate electrode and the gate oxide by at least two CVD processes to form the tensile stressed silicon nitride layer;
wherein after each of said CVD processes, UV light irradiation is performed.
4. The method of any one of claims 1 to 3, wherein said performing a heat treatment comprises:
the heat treatment is performed in a furnace tube.
5. The method of claim 4, wherein the temperature of the heat treatment is 300 to 600 degrees Celsius.
6. The method of claim 5, wherein said forming a first metal line and a second metal line in said interlevel dielectric layer and said tensile-stressed hardmask layer comprises:
etching is carried out, the hard mask layer and the interlayer dielectric layer of the tensile stress in the first target area, the second target area and the third target area are removed, a first through hole, a second through hole and a third through hole are formed respectively, and the preset areas of the source electrode and the channel leading-out electrode, the preset area of the grid electrode and the preset area of the drain electrode are exposed;
forming a metal layer on the interlayer dielectric layer, wherein the metal layer fills the first through hole, the second through hole and the third through hole;
and flattening the metal layer, and removing the metal layer outside the first through hole, the second through hole and the third through hole, wherein the metal layer in the first through hole forms the first metal connecting line, the metal layer in the second through hole forms the second metal connecting line, and the metal layer in the third through hole forms the third metal connecting line.
7. An LDMOS device, comprising:
the LDMOS device comprises a substrate, wherein a surrounding STI structure is formed in the substrate, an active region of the LDMOS device is arranged in the surrounding STI structure, a well doping region and a drift region are formed in the active region, a source electrode and a channel leading-out electrode are formed in the well doping region, and a drain electrode is formed in the drift region;
the gate oxide is formed on the substrate of the active region;
the grid electrode is formed on the grid oxide, and dangling bonds on the surface of the grid electrode are neutralized by deuterium gas;
a tensile hard mask layer formed on the surfaces of the substrate, the gate and the gate oxide;
the interlayer dielectric layer is formed on the hard mask layer with the tensile stress;
the first metal connecting wire is formed in the interlayer dielectric layer and the hard mask layer of the tensile stress, and the bottom end of the first metal connecting wire is connected with the source electrode and the channel leading-out electrode;
the second metal connecting wire is formed in the interlayer dielectric layer and the hard mask layer of the tensile stress, and the bottom end of the second metal connecting wire is connected with the grid;
and the third metal connecting wire is formed in the interlayer dielectric layer and the hard mask layer of the tensile stress, and the bottom end of the third metal connecting wire is connected with the drain electrode.
8. The device of claim 7, wherein the tensile-stressed hard mask layer comprises a tensile-stressed silicon nitride layer.
9. The device of claim 8, wherein the gate oxide and the gate electrode form a step-type structure, and the gate oxide forms a bottom step of the step-type structure.
10. The device of claim 9, wherein the gate oxide is a stepped gate oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011038210.1A CN112185817A (en) | 2020-09-28 | 2020-09-28 | LDMOS device and forming method thereof |
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| CN202011038210.1A CN112185817A (en) | 2020-09-28 | 2020-09-28 | LDMOS device and forming method thereof |
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| CN112185817A true CN112185817A (en) | 2021-01-05 |
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| CN (1) | CN112185817A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113921591A (en) * | 2021-09-24 | 2022-01-11 | 上海华虹宏力半导体制造有限公司 | LDMOS device and forming method thereof |
| CN114093950A (en) * | 2021-11-12 | 2022-02-25 | 中国电子科技集团公司第五十五研究所 | LDMOS device of stepped STI auxiliary field plate and manufacturing method thereof |
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| US20050255684A1 (en) * | 2004-05-17 | 2005-11-17 | Pdf Solutions, Inc. | Implantation of deuterium in MOS and DRAM devices |
| US20140001474A1 (en) * | 2012-07-02 | 2014-01-02 | Zhongshan Hong | Cmos device and fabrication method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050255684A1 (en) * | 2004-05-17 | 2005-11-17 | Pdf Solutions, Inc. | Implantation of deuterium in MOS and DRAM devices |
| US20140001474A1 (en) * | 2012-07-02 | 2014-01-02 | Zhongshan Hong | Cmos device and fabrication method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113921591A (en) * | 2021-09-24 | 2022-01-11 | 上海华虹宏力半导体制造有限公司 | LDMOS device and forming method thereof |
| CN114093950A (en) * | 2021-11-12 | 2022-02-25 | 中国电子科技集团公司第五十五研究所 | LDMOS device of stepped STI auxiliary field plate and manufacturing method thereof |
| CN114093950B (en) * | 2021-11-12 | 2023-06-13 | 中国电子科技集团公司第五十五研究所 | LDMOS device of stepped STI auxiliary field plate and manufacturing method thereof |
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Application publication date: 20210105 |