JP4764988B2 - Method for manufacturing insulated gate field effect transistor - Google Patents

Description

  In this invention, a trench (groove) is formed on a semiconductor substrate, and a lateral power MOSFET (insulated gate type field effect) such as a gate electrode, a contact hole between a metal electrode on the surface and a drain region at the bottom of the trench, and a channel region is formed inside the trench. The present invention relates to a method for manufacturing a transistor. This horizontal power MOSFET is often used as a main component of a semiconductor device such as a power IC.

In recent years, with the rapid spread of portable devices and the advancement of communication technology, the importance of power ICs incorporating power MOSFETs has increased. In particular, trench on-resistance power MOSFETs (hereinafter referred to as TLPM) that can be further highly integrated by controlling the on-resistance lower than conventional planar-type lateral power MOSFETs and reducing the device pitch can be the same as the control circuit. A power IC integrated on a semiconductor substrate is expected to have a smaller size, lower power consumption, higher reliability, and lower cost as compared with a conventional power IC having the same combination.
As disclosed by the present inventors, the TLPM has a type of TLPM in which a drain contact is provided at the bottom of the trench (hereinafter referred to as TLPM / D) and a type of TLPM in which a source contact is provided at the bottom of the trench (hereinafter referred to as TLPM). / S). In these TLPMs, in both the region for driving current as a MOSFET (hereinafter referred to as an active region) and the region for pulling out a polysilicon gate serving as a gate electrode on the substrate surface (hereinafter referred to as a gate region), In the central portion, the drain electrode on the device surface and the drain region at the bottom of the trench (for TLPM / D), or the source electrode on the device surface and the source region at the bottom of the trench (for TLPM / S) are electrically connected. A conductor such as polysilicon is formed (for example, see Patent Document 1 or 2).

On the other hand, when an insulating film is embedded in a trench formed in a semiconductor substrate, voids are not generated, and the insulation of an STI (Sallow Trench Isolation) structure that can prevent deterioration of characteristics of an element formed in the semiconductor substrate. In order to obtain a method for manufacturing a gate-type field effect transistor, a step of forming a groove in the surface of the semiconductor substrate and a TEOS (Tetra Ethyl in the groove)
Ortho Silicate-Si (OC ₂ H ₅ ) ₄ ) In a manufacturing method for forming an STI structure by embedding an insulating film generated by decomposing gas, TEOS gas is vapor-phase pyrolyzed as a step of embedding the insulating film. An invention is known which is a manufacturing method including a first growth step of growing a first insulating film and a second growth step of growing the second insulating film by surface pyrolyzing the TEOS ( Patent Document 3—Problems, Solution).

  FIG. 13 shows a plan view of the main part of the TLPM. FIG. 14 is a cross-sectional view taken along line AA in FIG. 13 and 14, reference numeral 53 denotes a rectangular trench, and in particular, FIG. 13 shows a planar pattern of the trench. The narrower width of the trench 53 (the width in the AA direction) is, for example, 2.5 μm. Source electrodes 78 and 80 are located on the surfaces on both sides of the trench 53. An insulating film 55 is sandwiched between the electrodes 78 and 80, and openings (contact holes) 66 and 68 formed in the insulating film 55 and metal materials 70, 72, 74, and 76 filled in the openings, The surface source electrodes 78, 80 and the source region 58 on the silicon substrate surface are conductively connected. A polysilicon gate electrode 59 is located on the side surface of the trench 53 with a gate oxide film 57 interposed therebetween, and further, a drain region 54 at the bottom of the trench and the surface of the trench 53 are disposed in the center of the trench 53 with an insulating film 55 interposed therebetween. An opening 67 filled with metal materials 71 and 75 for conductively connecting the drain electrode 79 is located.

  A manufacturing process of an Nch TLPM wafer having the bottom of the trench 53 as the drain region 54 will be described with reference to FIGS. As shown in FIG. 4, a P well region 51 is selectively formed on a P type silicon substrate (P sub) 50. As shown in FIG. 5, a trench 53 is formed by anisotropic etching such as RIE using a thermal oxide film or a CVD oxide film 52 as a mask. The size of the trench 53 is determined according to the electrical characteristics required for the TLPM 40. For example, the size required for the trench 53 of the TLPM 40 having a withstand voltage of 30 V is 2.5 μm wide and 2.0 μm deep. Next, using the oxide film 52 as an ion implantation mask, a drain region 54 is formed at the bottom of the trench 53. A LOCOS oxide film 56 (not shown) is formed on the portion corresponding to the boundary of the outer peripheral portion of the TLPM 40 as necessary to form an element isolation region. Next, after sacrificial oxide film (not shown) is formed and removed to clean the inner surface of the trench 53, a gate oxide film 57 is formed to a thickness of 17 nm as shown in FIG. After a polysilicon film having a thickness of 05 μm is formed on the entire surface, a polysilicon gate electrode 59 is formed on the sidewall of the trench 53 via the gate oxide film 57 by anisotropic etching. After the source region 58 is formed as shown in FIG. 7, a buried oxide film 55 is formed in the trench 53 with an HTO (High Temperature Oxide) film, as shown in FIG. The HTO film 55 becomes an interlayer insulating film 55 between the gate electrode 59 and a drain electrode 79 described later. Further, the interlayer insulating film 55 embedded in the trench 53 needs to completely fill at least the trench 53 in order to polish and planarize the outermost surface thereof by chemical mechanical polishing (hereinafter abbreviated as CMP). For example, in the case of the above-mentioned trench having a width of 2.5 μm and a depth of 2.0 μm, the trench can be completely filled even if the thickness of the insulating film is 2.0 μm or less because the width is narrow. Considering the protruding portion on the semiconductor substrate, in order to flatten the outermost surface of the insulating film without hindrance, an insulating film having a thickness of at least 2.0 μm or more is required. After that, as shown in FIG. 9, an opening (contact hole) 67 and other openings 66 for establishing electrical continuity with the drain region 54 at the bottom of the trench 53 are formed in the interlayer insulating film 55 by photolithography. As shown in FIG. 14, the opening 67 is filled with the barrier metal 71 and the buried metal plug 75, and the openings 66 and 68 are filled with the barrier metal 70 and 72 and the buried metal plugs 74 and 76, respectively. Further, metal electrodes (drain electrode 79, source electrodes 78, 80) are formed on the outermost surface, and the TLPM element 40 is obtained.

In this TLPM 40, when the width of the trench 53 is 2.5 μm as described above as shown in FIG. 11b, which is partially enlarged, at least the necessary width 0 as the contact width of the opening 67 in the center of the insulating film 55 in the trench. Even if a 6 μm hole is provided, in order to ensure a dielectric breakdown voltage of 30 V required between the gate electrode 59 and the opening 67 (arrow dotted line T1), at least the required film thickness of 0. A sufficient thickness of 05 μm or more can be obtained. Since the TLPM 40 has a trench structure as described above, the size of the element can be made relatively small even in the case of a high breakdown voltage element as compared with a conventional planar type MOSFET having no trench 53. There is.
JP 2002-353447 A JP 2002-280549 A JP 2000-200241 A

However, the TLPM has a problem that the mass productivity is not good because it is necessary to form a thick HTO film having a low deposition rate as an interlayer insulating film embedded in the trench. For example, in order to fill a trench having a depth of 2 μm with an HTO film and polishing the outermost surface of the HTO film by CMP for planarization with the TLPM having the above-mentioned dimensional specifications, an HTO film having a thickness exceeding 2 μm is formed. Must. The formation of an HTO film having a thickness of 2 μm or more has a problem that not only the film formation time is too long, but also the frequency of repair necessary for maintenance of the HTO film formation apparatus is high, and the apparatus cannot be operated efficiently. . More specifically, since the film formation rate of the HTO film is usually about 1.5 nm / min, in the case of 1.5 nm / min, in order to obtain the thickness of the HTO film of 2 μm, the film formation time is about 22 Time is required and the maintenance of the HTO film is performed once for every 4 μm of HTO film (ie, once for 2 μm thick HTO film, 2 lots). It must be. For this reason, as described above, the formation of a HOT film having a thickness of more than 2 μm has a problem in mass productivity.

  On the other hand, Patent Document 3 discloses an insulating film called a TEOS oxide film whose deposition rate is several times faster than that of an HTO film. However, when the TEOS oxide film is used as the insulating film for embedding the trench formed on the surface of the TLPM element substrate as described above, the film formation time is surely shortened, but the TLPM element is manufactured. Many breakdown defects occurred between the gate and the drain. The reason for this is thought to be that the insulation breakdown voltage was reduced by atoms and molecules such as C and H existing in the film because the thickness of the insulating film in the trench portion was as thick as 2 μm or more. Actually, when the leak location was examined by the OBIC (Optical Beam Induced Current) method, cross-sectional observation, etc., many leaks were observed at the arrows such as T1 and T2 as shown in FIG. 11b. According to SIMS (Secondary Ion Mass Spectrum) analysis (secondary ion mass spectrometry), it was considered that the cause of the decrease in the withstand voltage of the TEOS oxide film was due to residual impurities such as carbon.

The OBIC method is a known example of a failure analysis method for a semiconductor device, which uses a light excitation microscope that scans and irradiates a semiconductor device with laser light and observes a photoexcitation current caused by electron-hole pairs generated in the semiconductor device. It is a technique.
The present invention has been made in view of the above-described problems, and an object of the present invention is to reduce the number of gate-drain insulation defects in a method for manufacturing an insulated gate field-effect transistor without increasing the number of defects. An object of the present invention is to provide a method of manufacturing an insulated gate field effect transistor capable of efficiently forming a trench buried insulating film in time.

According to the first aspect of the present invention, the object is to form a trench in the first conductivity type semiconductor substrate and to form a second conductivity type first region at the bottom of the trench. A step of forming a gate electrode film on a sidewall of the trench through a gate insulating film, a step of forming a second conductivity type second region formed adjacent to the trench on a semiconductor substrate, and the trench In a method of manufacturing an insulated gate field effect transistor , comprising: embedding an insulating film therein ; forming an opening reaching the first region from the surface of the insulating film; and embedding a metal plug in the opening . ,
In the step of embedding the insulating film, the first TEOS oxide film is deposited to a thickness capable of forming a recess along the shape of the trench , and an annealing process is performed to remove carbon that is an impurity, so that the thickness is 0.05 μm or more. A step of forming a first insulating film, and a step of forming a second insulating film by depositing a second TEOS oxide film on the first insulating film and not performing an annealing process for removing carbon as the impurity with the manufacturing method of an insulated gate field effect transistor consisting of, it is achieved.

According to the second aspect of the present invention, the insulated gate field effect transistor according to claim 1, further comprising a planarization step of polishing the insulating film after the step of embedding the insulating film. The method is preferred.
According to the third aspect of the present invention, the method for manufacturing an insulated gate field effect transistor according to claim 1 or 2, wherein the width of the opening is wider than the width of the recess. preferable.

  According to the present invention, in a method of manufacturing an insulated gate field effect transistor, an insulated gate field effect capable of efficiently forming a trench-filled insulating film in a shorter time without increasing insulation failure between the gate and drain. A method for manufacturing a transistor can be provided.

  Hereinafter, an embodiment according to the present invention will be described in detail with reference to the drawings. In the following embodiments, the case of TLPM / D will be described as a trench insulated gate field effect transistor, but it goes without saying that the case of TLPM / S can be similarly produced by the method for manufacturing a semiconductor substrate according to the present invention. . As long as the gist of the present invention is not exceeded, the present invention is not limited to the description of the examples described below.

A method for manufacturing an insulated gate field effect transistor according to the present invention will be described below. FIG. 1 is a cross-sectional view of the main part in the manufacturing process of the TLPM according to the present invention corresponding to the cross-sectional view of the main part in the manufacturing process of the TLPM shown in FIG. 1A is a cross-sectional view of the main part of the TLPM corresponding to the step of forming the first insulating film 5a in the trench 3, and FIG. 1B corresponds to the step of forming the second insulating film 5b in the trench 3. The principal part sectional drawing of TLPM which performs is shown, respectively. The manufacturing process up to FIG. 8 is almost the same as the conventional manufacturing process shown in FIGS. 4 to 7 and will be described briefly here.
As shown in FIGS. 4 to 7, the P well layer 2, the trench 3, the N drain layer 4, the LOCOS oxide film (not shown) and the like are formed on the P type Si substrate (P sub) 1 in FIG. After the formation, a gate oxide film 7 is formed by a thermal oxidation method, and a polysilicon film (not shown) is formed on the entire surface by a CVD method, and then the polysilicon film is patterned by anisotropic etching such as RIE. Thus, the gate electrode film 9 is formed. Next, an N source region 8 is formed by ion implantation.

  Next, as shown in FIG. 1A, a TEOS oxide film 5a is formed as a first insulating film to a thickness of 1 μm or less so that a recess is formed along the shape of the trench 3 without filling the trench 3. . The TEOS oxide film was formed by introducing TEOS gas at a flow rate of 130 ml / min and oxygen gas at a flow rate of 6 ml / min into a film formation chamber at a heater temperature of 680 ° C. and 60 Pa, and a film formation rate of 4 nm / min. Next, the TEOS 5a film is annealed at 850 ° C. for 30 minutes in an oxygen atmosphere, so that silicon oxide generated by thermal decomposition of the TEOS gas is deposited and formed into an oxide film in the process of forming the TEOS oxide film. At the same time, the reduced carbon component caught and trapped at the same time can be removed. The annealing temperature is desirably 850 ° C. or lower from the viewpoint that the impurity diffusion layers such as the source region and the drain region formed on the semiconductor substrate are not substantially changed by the heat treatment. As a result, the insulation property of the TEOS oxide film can be improved. By this treatment, for example, the resistivity of the TEOS oxide film 5a, which was 4 MΩ / cm before the annealing treatment, increased to nearly 10 MΩ / cm after the annealing.

Next, as shown in FIG. 1B, as the second insulating film, the TEOS oxide film 5b is again formed to a thickness of 1 μm so that the trench is completely filled. An annealing treatment for 30 minutes was performed. The TEOS oxide film 5b as the second insulating film does not necessarily require annealing. The annealing process at 850 ° C. for 30 minutes can only remove impurities such as carbon having a thickness of about 1 μm from the surface, but the second TEOS oxide film 5b is also subjected to the annealing process after the annealing process. In the polishing by CMP, the first insulating film 5a and the second insulating film 5b have the same film quality, which is preferable from the point that there is no difference in the polishing rate.
FIG. 10 shows the LOCOS oxide film 6 added to FIG. Thereafter, in order to flatten the unevenness on the surface of the TEOS oxide film 5b, as shown in FIG. 12, it is polished by CMP so as to correspond to each electrode position in the TLPM region as shown in FIG. , Openings (contact holes) 16, 17, 18 are formed by a photolithographic technique. Barrier metals 20, 21, 22 such as a Ti—TiN film and buried metal plugs 24 such as tungsten are formed in the openings 16, 17, 18. , 25, 26 and metal electrode films 28, 29, 30 such as an aluminum film are formed in this order, the TLPM element 100 of the present invention shown in FIG. 3 is completed. Here, when the width of the opening 17 is controlled so that the opening width is such that the second insulating film 5b in the trench is removed and removed (for example, 1 μm in width), impurities such as carbon are contained in the insulating film in the trench. As a result, the reliability is improved.

The tungsten plugs 24, 25 and 26 are formed as follows. First, after nucleation of tungsten by a reduction reaction using tungsten hexafluoride and monosilane on the Ti-TiN film, the openings (contact holes) 16 and 17 by a reduction reaction using tungsten hexafluoride and hydrogen. , 18 is formed to form a tungsten film having a thickness equal to or greater than the thickness. Next, by dry etching, the tungsten film other than the openings (contact holes) 16, 17 and 18 is etched back and removed to form the tungsten plug.
When the TEOS oxide film is embedded in the trench of the TLPM element, as described above, between the source electrode and the drain electrode (particularly between the polysilicon gart electrode and the drain contact hole) in the insulating film in the trench. In order to satisfy the withstand voltage, it is necessary to remove impurities such as carbon remaining in the TEOS oxide film and to make the distance between both electrodes 0.05 μm or more. The first insulating film 5a and the second insulating film 5b are preferably annealed at 850 ° C. for 30 minutes. However, according to the annealing conditions, the resistivity is sufficiently high at 10 MΩ / cm. Therefore, the TEOS oxide film 5b as the second insulating film does not necessarily have a problem in practice even if it is not necessarily annealed to increase the resistance, as described above, because only the first insulating film satisfies the above conditions. It is.

  In the case where the insulating film embedded in the trench is formed by the TEOS oxide film according to the present invention and in the case where the insulating film is formed only by the HTO oxide film as in the prior art, the film formation for 10 lots and the necessary processing are performed. A comparison of the time with the device maintenance time is as follows. However, the film formation time of the HTO film is when the film thickness is 2 μm, and the film formation time of the TEOS oxide film is when the film thickness of 1 μm is formed twice. Both the TEOS oxide film and the HTO film and annealing treatment include temperature rise and temperature drop times, and the maintenance time of the apparatus is 4 hours once.

As can be seen from Table 1, according to the method of manufacturing an insulated gate field effect transistor of the present invention, the conventional HTO film, which took 226 hours in all 10 lots, can be halved to 114 hours in 10 lots. did it.
With respect to 100 TLPM elements created according to the present invention and 100 TLPM elements created by a conventional manufacturing method, the dielectric breakdown voltage between the gate electrode in the trench and the drain contact hole was examined. The dielectric strength in the case of the element is 120V ± 10V, whereas the dielectric strength in the case of the TLPM element according to the conventional manufacturing method is 118V ± 10V, which is a comparable dielectric strength.
Next, in order to compare the present invention with the film formation time, the film formation time was examined in the case of forming a TEOS oxide film with a film thickness of 2 μm at a time. According to the present invention, the film formation time for one lot from the above Table 1 takes 10 hours, but the film formation time for one film thickness of 2 μm can be shortened to 8.5 hours, which is 1.5 hours. However, in the case of the present invention, in the first TEOS oxide film 5a, as shown in FIG. 1A, since the trench 3 is not completely filled with the oxide film, the impurity is obtained by annealing at 850 ° C. for 30 minutes. In the case of one annealing treatment (when only the first insulating film is annealed) for 10.5 hours and two annealing treatments (first and second) 11 hours in the case of annealing the two insulating films).

On the other hand, when a film thickness of 2 μm is formed at a time, the trench width formed in the TLPM element is as narrow as 2.5 μm. The thickness of the oxide film is 4 μm, and the annealing process for 30 minutes is no longer sufficient in time, and impurities cannot be removed sufficiently. It has been found that when the film thickness is 4 μm, the annealing time needs to be 8 hours in order to obtain a TEOS oxide film from which impurities are sufficiently removed.
As a result, when the film formation time, the annealing time, and the temperature increase / decrease time of 30 minutes are added, the total time is 17 hours. Therefore, it can be seen that the time is shorter when the TEOS oxide film having a thickness of 1 μm is formed twice. The time required for removing carbon atoms C from the TEOS oxide film will be described below. A diffusion equation representing the concentration C (x, t) after t time with the diffusion distance x from the original position of carbon atom C (contained position in the film) is expressed by the following equation. In this formula, Cs is the initial concentration of carbon atoms, and D is the carbon diffusion constant.

From this equation, in order to remove the carbon atoms C from the TEOS oxide film by diffusion to the outside, assuming that the diffusion distance x in the equation is the film thickness of the TEOS oxide film, the TEOS oxide film It can be seen that the film thickness is determined in relation to (Dt) ^1/2 . In other words, it shows that the annealing time of 30 minutes when the film thickness of the first TEOS oxide film 5a is 1 μm is required, and that the annealing time of 8 hours is required when the film thickness of the trench is 4 μm. Furthermore, if the film thickness to be annealed is 4 times (1 μm is 4 μm), the processing time is 16 times (30 minutes is 8 hours). Nevertheless, in the case of the TEOS oxide film (4 μm film thickness), the processing time can be significantly shortened compared with the conventional method of filling the trench with a 2 μm thick HTO film (processing time 21 hours).

In the TLPM element, the case where the TEOS oxide film 5b as the second insulating film is not annealed will be described in detail below. The specification required for the oxide film filling the trench is that the annealed oxide film thickness is at least 0.05 μm or more necessary to ensure the withstand voltage between the drain electrode and the source electrode in the oxide film. . In this embodiment, the thickness of the LOCOS oxide film is 0.2 μm, and the polishing amount of CMP is 1.5 μm. Therefore, as shown in FIG. 12, among the TEOS oxide films 5a and 5b according to the present invention, 1.3 μm is removed by polishing. Further, since the required breakdown voltage can be secured by the first annealing process of the TEOS oxide film 5a (film thickness: 1 μm), the second TEOS oxide film 5b does not necessarily need to be annealed. Therefore, an element was actually created and the effect was confirmed.
Since the second TEOS oxide film 5b is not increased in resistance by not performing the second annealing process, there is a concern about fluctuations in the polishing rate of the CMP and the etching rate of the TEOS oxide film. An experiment was conducted. The results are shown in Table 2. As can be seen from Table 2, although the TEOS oxide film polishing rate fluctuated (from 850 mm / min to 760 mm / min) depending on the presence or absence of annealing treatment, CMP is performed by pressing the surface against the pad. In addition, the polishing speed is regulated by the slow one appearing on the surface, so that it is considered that there is actually no problem. Variations in the etching rate due to the oxide film etcher were both 210 mm / min and were not seen at all. Based on this result, when actually applied to a TLPM element, there was almost no problem in the CMP polishing and the processed shape of the contact hole.

A TLPM element according to Example 2 was prepared by the following procedure. As in Example 1, the first TEOS oxide film 5a was formed to a thickness of 1 μm, and then annealed at 850 ° C. for 30 minutes. Next, a second TEOS oxide film 5b is formed to a thickness of 1 μm, and after that, annealing is not performed, and after polishing 1.3 μm by CMP as in the prior art, a contact hole is opened and a barrier metal is formed in the opening. Then, a buried tungsten plug and a metal electrode were formed.
With respect to 100 TLPM elements obtained by the above-described Example 2 and 100 elements prepared by the conventional technique, the withstand voltage between the gate electrode and the drain plug was examined in the same manner as the dotted line T in FIG. The withstand voltage in the case of the present invention was 119V ± 10V, whereas the withstand voltage in the case of the conventional method was almost equal to 118V ± 10V. Moreover, it has confirmed with an actual TLPM element that it has the same withstand voltage as that described in the first embodiment. This is considered to indicate the result of the effective modification (high resistance) for having an effective withstand voltage by the first annealing process of the TEOS oxide film 5a.

  In the first and second embodiments described above, the TEOS oxide film is used for both the first insulating film 5a and the second insulating film 5b, but the first insulating film may be an HTO film. If necessary, a TEOS oxide film as a third insulating film can be further formed. In this case, the thickness of the TEOS oxide film as the third insulating film is 0.5 μm to 1 μm. This third insulating film does not require an annealing process because the withstand voltage is already secured by the second insulating film.

Schematic sectional view of an insulated gate field effect transistor made by the manufacturing method of the present invention The principal part top view of the insulated gate field effect transistor made by the manufacturing method of this invention Sectional drawing of the principal part of the insulated gate field effect transistor made by the manufacturing method of this invention Sectional drawing of the principal part of the one-step semiconductor device in the manufacturing process concerning the manufacturing method of the conventional insulated gate field effect transistor Sectional drawing of the principal part of the one-step semiconductor device in the manufacturing process concerning the manufacturing method of the conventional insulated gate field effect transistor Sectional drawing of the principal part of the one-step semiconductor device in the manufacturing process concerning the manufacturing method of the conventional insulated gate field effect transistor Sectional drawing of the principal part of the one-step semiconductor device in the manufacturing process concerning the manufacturing method of the conventional insulated gate field effect transistor Sectional drawing of the principal part of the one-step semiconductor device in the manufacturing process concerning the manufacturing method of the conventional insulated gate field effect transistor Sectional drawing of the principal part of the one-step semiconductor device in the manufacturing process concerning the manufacturing method of the conventional insulated gate field effect transistor Sectional drawing of an essential part of one step of an insulated gate field effect transistor in the manufacturing process according to the manufacturing method of the present invention. (A) is principal part sectional drawing of the insulated gate field effect transistor made by the manufacturing method of this invention, (b) is typical expanded sectional view of the insulated gate field effect transistor made by the manufacturing method of this invention Sectional drawing of the principal part of one step of the insulated gate field effect transistor in the manufacturing process according to the manufacturing method of the present invention Plan view of relevant part of a semiconductor device according to a conventional method of manufacturing an insulated gate field effect transistor Schematic cross-sectional view of a semiconductor device manufactured by a conventional method of manufacturing an insulated gate field effect transistor

Explanation of symbols

1 P-type Si substrate 2 P well region 3 Trench 4 N drain region 5a First insulating film 5b Second insulating film 6 LOCOS oxide film (element isolation oxide film)
7 Gate oxide film 8 N source region 9 Gate electrode film 16, 17, 18 Opening (contact hole)
20, 21, 22 Barrier metal 24, 25, 26 Tungsten plug 28, 29, 30 Metal electrode 40 Insulated gate field effect transistor, TLPM (trench lateral MOSFET)
100 TLPM element (trench lateral MOSFET) according to the present invention.

Claims (3)

Forming a trench in a first conductivity type semiconductor substrate; forming a second conductivity type first region at the bottom of the trench; and forming a gate electrode film on a sidewall of the trench through a gate insulating film. A step of forming a second region of a second conductivity type formed adjacent to the trench on the semiconductor substrate, a step of embedding an insulating film in the trench, and reaching the first region from the surface of the insulating film In a method of manufacturing an insulated gate field effect transistor comprising the steps of forming an opening and embedding a metal plug in the opening
In the step of embedding the insulating film, the first TEOS oxide film is deposited to a thickness capable of forming a recess along the shape of the trench , and an annealing process is performed to remove carbon that is an impurity, so that the thickness is 0.05 μm or more. A step of forming a first insulating film, and a step of forming a second insulating film by depositing a second TEOS oxide film on the first insulating film and not performing an annealing process for removing carbon as the impurity insulated gate field effect method for producing a transistor, characterized by comprising a. 2. The method of manufacturing an insulated gate field effect transistor according to claim 1, further comprising a planarization step by polishing after the step of embedding the insulating film. 6. The method of manufacturing an insulated gate field effect transistor according to claim 5, wherein the width of the opening is wider than the width of the recess.

Images