WO2019137093A1 - Sic-based di-mosfet preparation method and sic-based di-mosfet - Google Patents
Sic-based di-mosfet preparation method and sic-based di-mosfet Download PDFInfo
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- WO2019137093A1 WO2019137093A1 PCT/CN2018/115873 CN2018115873W WO2019137093A1 WO 2019137093 A1 WO2019137093 A1 WO 2019137093A1 CN 2018115873 W CN2018115873 W CN 2018115873W WO 2019137093 A1 WO2019137093 A1 WO 2019137093A1
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229910052760 oxygen Inorganic materials 0.000 claims description 28
- 239000001301 oxygen Substances 0.000 claims description 28
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 24
- 238000000137 annealing Methods 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 238000000206 photolithography Methods 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- -1 oxygen ions Chemical class 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 4
- 239000007943 implant Substances 0.000 claims 3
- 238000002513 implantation Methods 0.000 claims 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 54
- 229910010271 silicon carbide Inorganic materials 0.000 description 53
- 239000000463 material Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Definitions
- the invention belongs to the field of semiconductor devices, and in particular relates to a method for preparing a SiC-based DI-MOSFET and a SiC-based DI-MOSFET.
- SiC Silicon Carbide
- DI-MOSFET Double Implanted Metal Oxide Semiconductor Field Effect Transistor
- a gate oxide layer is formed by thermal oxygen on the surface of the SiC, polysilicon is deposited thereon to form a gate electrode, and a dielectric layer is deposited to isolate the gate. Finally, a source metal and a drain metal are deposited and annealed to prepare a source electrode and a drain electrode. Since the gate and the SiC epitaxial layer are separated by a thin layer of gate oxide, the gate-drain capacitance is large, which limits the switching speed of the device and increases the switching loss of the device.
- a first technical problem to be solved by the present invention is to provide a method of preparing a SiC-based DI-MOSFET.
- a second technical problem to be solved by the present invention is to provide a SiC-based DI-MOSFET.
- the invention provides a preparation method of a SiC-based DI-MOSFET, comprising the following steps:
- S1 selecting an SiC epitaxial substrate obtained by epitaxially growing a SiC epitaxial layer on the front surface of the SiC substrate;
- S2 implanting p-type ions into a partial region of the surface of the SiC epitaxial layer by using a photolithographic mask to form two p-type ion implantation regions; then implanting n-type ions into a partial region of the surface of each p-type ion implantation region by using a photolithographic mask Forming an n-type ion implantation region in each p-type ion implantation region; and injecting the injected p-type ions and n-type ions by one annealing;
- S4 performing high temperature thermal oxidation treatment to form an oxide layer on the surface of the SiC epitaxial layer, and the thickness of the oxide layer in the oxygen ion implantation region is greater than the thickness of the oxide layer in the remaining region of the surface of the SiC epitaxial layer;
- S6 depositing a dielectric layer on the gate, so that the dielectric layer coats the gate, and then etching and removing the dielectric layer and the oxide layer on the surface of the two p-type ion implantation regions by using a photolithography mask, in each of the dielectric layers Forming a source-level contact hole on one side, and a bottom portion of each source-level contact hole is a p-type ion implantation region and a bare portion of the surface of the n-type ion implantation region;
- the oxygen ion implantation depth of the oxygen ion implantation region is 30 nm to 1000 nm.
- the oxygen ion implantation region has an oxygen ion implantation concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 22 cm ⁇ 3 .
- the temperature of the one-time annealing is 1500 ° C to 1900 ° C.
- the temperature of the high temperature thermal oxidation treatment is 600 ° C to 2000 ° C.
- the temperature of the secondary annealing is from 800 ° C to 1200 ° C.
- the present invention provides a SiC-based DI-MOSFET, which is prepared by the above preparation method, and includes:
- An SiC epitaxial substrate comprising a SiC substrate and a SiC epitaxial layer epitaxially grown on the front surface of the SiC substrate;
- each n-type ion implantation region is located in a p-type ion implantation region;
- An oxide layer covering the SiC epitaxial layer between the two p-type ion implantation regions and covering each p-type ion implantation region and a partial region of each n-type ion implantation region, and the two p-type ion implantation regions
- the thickness of the oxide layer is greater than the thickness of the oxide layer in the remaining regions;
- the dielectric layer is covered by a gate, and a source-level contact hole is disposed on each side of the dielectric layer;
- a source-level metal layer covering the surface of the two source-level contact holes and the dielectric layer, and the source-level metal layer is in ohmic contact with the p-type ion implantation region and the n-type ion implantation region at the bottom of each source-level contact hole ;
- a drain metal layer overlies the back side of the SiC substrate, and the contact of the drain metal layer with the back side of the SiC substrate is an ohmic contact.
- Any range recited in the present invention includes any value between the end value and the end value, and any subrange of any value between the end value or the end value.
- each of the raw materials in the present invention can be obtained by commercially available purchase, and the apparatus used in the present invention can be carried out by using conventional equipment in the art or by referring to the prior art in the related art.
- the present invention has the following beneficial effects:
- the SiC-based DI-MOSFET of the present invention reduces the gate-drain capacitance of the DI-MOSFET device by increasing the thickness of the oxide layer between the SiC epitaxial layer between the gate and the two p-type ion implantation regions, thereby further reducing the gate-drain capacitance of the DI-MOSFET device. Further increase the operating frequency of the device and reduce the dynamic loss of the device.
- FIG. 1 is a flow chart of a method for fabricating a SiC-based DI-MOSFET according to an embodiment of the present invention
- 2-8 are schematic diagrams showing steps of a method for fabricating a SiC-based DI-MOSFET according to an embodiment of the present invention.
- This embodiment provides a method for preparing a SiC-based DI-MOSFET. As shown in FIG. 1, the preparation method includes the following steps:
- S1 selecting an SiC epitaxial substrate obtained by epitaxially growing a SiC epitaxial layer 2 on the front surface of the SiC substrate 1, as shown in FIG. 2;
- S4 performing a high-temperature thermal oxidation treatment to form an oxide layer 6 on the surface of the SiC epitaxial layer 2 (including the p-type ion implantation region 3, the n-type ion implantation region 4, and the oxygen ion implantation region 5), and the oxygen ion implantation region 5
- the thickness of the oxide layer 6 is greater than the thickness of the oxide layer 6 in the remaining area of the surface of the SiC epitaxial layer 2, as shown in FIG. 5;
- S6 depositing a dielectric layer 8 on the gate electrode 7, so that the dielectric layer 8 coats the gate electrode 7, and then etching the dielectric layer 8 and the oxide layer 6 on the surface of the two p-type ion implantation regions 3 by using a photolithography mask. Removing, a source-level contact hole is formed on each side of the dielectric layer 8, and the bottom of each source-level contact hole is a bare portion of the surface of the p-type ion implantation region 3 and the n-type ion implantation region 4, as shown in FIG. Show
- S7 depositing a source metal layer 9 on the surface of the two source contact holes and the dielectric layer 8, depositing a drain metal layer 10 on the back surface of the SiC substrate 1, and then causing the source metal layer 9 and each by secondary annealing.
- the p-type ion implantation region 3 and the n-type ion implantation region 4 at the bottom of a source-level contact hole each form an ohmic contact, and the drain metal layer 10 forms an ohmic contact with the back surface of the SiC substrate 1, as shown in FIG.
- the oxygen ion implantation depth of the oxygen ion implantation region 5 is 30 nm to 1000 nm, and the oxygen ion implantation concentration of the oxygen ion implantation region 5 is 1 x 10 18 cm -3 to 1 x 10 22 cm -3 .
- the temperature of the high temperature thermal oxidation treatment is 600 ° C to 2000 ° C.
- the temperature of one annealing is 1500 ° C to 1900 ° C.
- the temperature of the secondary annealing is 800 ° C to 1200 ° C.
- the above lithography mask refers to a mask formed by a photolithography process in a chip processing technique, which may be an occlusion material for an ion implantation process or a masking material used in an etch process.
- the material of the above lithography mask may be a photoresist or other materials such as a medium, a metal, or the like.
- the embodiment further provides a SiC-based DI-MOSFET, which is prepared by the above preparation method, and includes:
- SiC epitaxial substrate comprising a SiC substrate 1 and an SiC epitaxial layer 2 epitaxially grown on the front surface of the SiC substrate 1;
- each n-type ion implantation region 4 is located in a p-type ion implantation region 3;
- the dielectric layer 8 is covered with a gate 7, and a dielectric contact hole is disposed on each side of the dielectric layer 8;
- a source-level metal layer 9 covering the surfaces of the two source-level contact holes and the dielectric layer 8, and the source-level metal layer 9 and the p-type ion implantation region 3 and the n-type ion implantation region 4 at the bottom of each source-level contact hole
- the contacts are all ohmic contacts
- a drain metal layer 10 covers the back surface of the SiC substrate 1, and the contact of the drain metal layer 10 with the back surface of the SiC substrate 1 is an ohmic contact.
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Abstract
Disclosed are a SiC-based DI-MOSFET preparation method and a SiC-based DI-MOSFET. The SiC-based DI-MOSFET comprises a SiC epitaxial substrate; two p-type ion implantation regions (3) and two n-type ion implantation regions (4) formed on the surface of a SiC epitaxial layer (2), each n-type ion implantation region (4) being located in each p-type ion implantation region (3); an oxide layer (6), the thickness of the oxide layer (6) between the two p-type ion implantation regions (3) being greater than the thickness of the oxide layer (6) at other regions; a gate (7) covering the surface of the oxide layer (6); a dielectric layer (8) wrapping the gate (7), two sides of the dielectric layer (8) being separately provided with a source contact hole; a source metal layer (9) covering the two source contact holes and the surface of the dielectric layer (8); and a drain metal layer (10) covering the back of a SiC substrate (1), the drain metal layer (10) being in ohmic contact the SiC substrate (1). The SiC-based DI-MOSFET can reduce gate leakage capacitance of devices.
Description
本发明属于半导体器件领域，尤其是涉及一种SiC基DI-MOSFET的制备方法及SiC基DI-MOSFET。The invention belongs to the field of semiconductor devices, and in particular relates to a method for preparing a SiC-based DI-MOSFET and a SiC-based DI-MOSFET.
碳化硅(Silicon Carbide,SiC)是一种优异的宽禁带半导体材料，具有高临界击穿电场强度、高饱和电子迁移率、高热导率等优点。基于SiC制备的电力电子器件，可以实现较同等电气级别的硅基器件更高的转换效率、更高的工作频率以及更低的功率损耗。SiC基的开关器件主要为DI-MOSFET(Double Implanted Metal Oxide Semiconductor Field Effect Transistor)，这种器件主要通过两次离子注入形成p型掺杂区和n型掺杂区并高温退火激活杂质。然后，在SiC表面通过热氧形成栅氧层，在其上淀积多晶硅形成栅极并淀积介质层将栅极隔离。最后，淀积源级金属和漏极金属并退火制备源电极、漏电极。由于栅极与SiC外延层只通过薄薄的一层栅氧层隔开，栅漏电容偏大，从而限制了器件的开关速度，同时增加了器件的开关损耗。Silicon Carbide (SiC) is an excellent wide bandgap semiconductor material with high critical breakdown electric field strength, high saturation electron mobility, and high thermal conductivity. Power electronic devices based on SiC can achieve higher conversion efficiency, higher operating frequency and lower power loss than silicon-based devices of the same electrical grade. The SiC-based switching device is mainly a DI-MOSFET (Double Implanted Metal Oxide Semiconductor Field Effect Transistor). This device mainly forms a p-type doped region and an n-type doped region by two ion implantations and a high temperature annealing activating impurities. Then, a gate oxide layer is formed by thermal oxygen on the surface of the SiC, polysilicon is deposited thereon to form a gate electrode, and a dielectric layer is deposited to isolate the gate. Finally, a source metal and a drain metal are deposited and annealed to prepare a source electrode and a drain electrode. Since the gate and the SiC epitaxial layer are separated by a thin layer of gate oxide, the gate-drain capacitance is large, which limits the switching speed of the device and increases the switching loss of the device.
如何降低SiC基DI-MOSFET的栅漏电容进而提高其开关速度已经成为本领域技术人员亟待解决的技术难题。How to reduce the gate-drain capacitance of SiC-based DI-MOSFET and increase its switching speed has become a technical problem to be solved by those skilled in the art.
发明内容Summary of the invention
本发明要解决的第一个技术问题是提供一种SiC基DI-MOSFET的制备方法。A first technical problem to be solved by the present invention is to provide a method of preparing a SiC-based DI-MOSFET.
本发明要解决的第二个技术问题是提供一种SiC基DI-MOSFET。A second technical problem to be solved by the present invention is to provide a SiC-based DI-MOSFET.
为解决上述第一个技术问题，发明采用如下的技术方案：In order to solve the above first technical problem, the invention adopts the following technical solutions:
本发明提供一种SiC基DI-MOSFET的制备方法，包括如下步骤：The invention provides a preparation method of a SiC-based DI-MOSFET, comprising the following steps:
S1：选取在SiC衬底正面外延生长一SiC外延层后得到的SiC外延基片；S1: selecting an SiC epitaxial substrate obtained by epitaxially growing a SiC epitaxial layer on the front surface of the SiC substrate;
S2：利用光刻掩膜向SiC外延层表面的部分区域注入p型离子，形成两p型离子注入区；然后利用光刻掩膜向每一p型离子注入区表面的部分区域注入n型离子，在每一p型离子注入区形成一n型离子注入区；再通过一次退火激活注入的p型离子和n型离子；S2: implanting p-type ions into a partial region of the surface of the SiC epitaxial layer by using a photolithographic mask to form two p-type ion implantation regions; then implanting n-type ions into a partial region of the surface of each p-type ion implantation region by using a photolithographic mask Forming an n-type ion implantation region in each p-type ion implantation region; and injecting the injected p-type ions and n-type ions by one annealing;
S3：利用光刻掩膜向位于两p型离子注入区之间的SiC外延层表面的部分区域注入氧离子，形成氧离子注入区；S3: implanting oxygen ions into a partial region of the surface of the SiC epitaxial layer between the two p-type ion implantation regions by using a photolithography mask to form an oxygen ion implantation region;
S4：进行高温热氧化处理，在SiC外延层的表面形成一氧化层，且氧离子注入区的氧化层厚度大于SiC外延层表面其余区域的氧化层厚度；S4: performing high temperature thermal oxidation treatment to form an oxide layer on the surface of the SiC epitaxial layer, and the thickness of the oxide layer in the oxygen ion implantation region is greater than the thickness of the oxide layer in the remaining region of the surface of the SiC epitaxial layer;
S5：在氧化层表面沉积一多晶硅层，然后利用光刻掩膜将氧离子注入区两侧的部分多晶硅层刻蚀去除，形成栅极；S5: depositing a polysilicon layer on the surface of the oxide layer, and then etching a part of the polysilicon layer on both sides of the oxygen ion implantation region by using a photolithography mask to form a gate;
S6：在栅极上沉积一介质层，使得介质层将栅极包覆，然后利用光刻掩膜将两p型离子注入区表面的介质层和氧化层均刻蚀去除，在介质层的每一侧形成一源级接触孔，且每一源级接触孔的底部为p型离子注入区和n型离子注入区表面裸露的部分区域；S6: depositing a dielectric layer on the gate, so that the dielectric layer coats the gate, and then etching and removing the dielectric layer and the oxide layer on the surface of the two p-type ion implantation regions by using a photolithography mask, in each of the dielectric layers Forming a source-level contact hole on one side, and a bottom portion of each source-level contact hole is a p-type ion implantation region and a bare portion of the surface of the n-type ion implantation region;
S7：在两源级接触孔和介质层的表面沉积一源级金属层，在SiC衬底的背面沉积一漏极金属层，然后通过二次退火使得源级金属层与源级接触孔底部的p型离子注入区和n型离子注入区均形成欧姆接触，且漏极金属层与SiC衬底的背面形成欧姆接触。S7: depositing a source-level metal layer on the surface of the two-source contact hole and the dielectric layer, depositing a drain metal layer on the back surface of the SiC substrate, and then performing a secondary annealing to make the source-level metal layer and the source-level contact hole bottom Both the p-type ion implantation region and the n-type ion implantation region form an ohmic contact, and the drain metal layer forms an ohmic contact with the back surface of the SiC substrate.
优选地，所述步骤S3中，所述氧离子注入区的氧离子的注入深度为30nm至1000nm。Preferably, in the step S3, the oxygen ion implantation depth of the oxygen ion implantation region is 30 nm to 1000 nm.
优选地，所述步骤S3中，所述氧离子注入区的氧离子的注入浓度为1x10
18cm
-3至1x10
22cm
-3。
Preferably, in the step S3, the oxygen ion implantation region has an oxygen ion implantation concentration of 1×10 18 cm −3 to 1×10 22 cm −3 .
优选地，所述一次退火的温度为1500℃至1900℃。Preferably, the temperature of the one-time annealing is 1500 ° C to 1900 ° C.
优选地，上述步骤S4中，所述高温热氧化处理的温度为600℃至2000℃。Preferably, in the above step S4, the temperature of the high temperature thermal oxidation treatment is 600 ° C to 2000 ° C.
优选地，所述二次退火的温度为800℃至1200℃。为解决上述第二个技术问题，本发明提供一种SiC基DI-MOSFET，该SiC基DI-MOSFET采用上述制备方法制得，其包括：Preferably, the temperature of the secondary annealing is from 800 ° C to 1200 ° C. In order to solve the above second technical problem, the present invention provides a SiC-based DI-MOSFET, which is prepared by the above preparation method, and includes:
一SiC外延基片，该SiC外延基片包括SiC衬底和在SiC衬底正面外延生长的一SiC外延层；An SiC epitaxial substrate comprising a SiC substrate and a SiC epitaxial layer epitaxially grown on the front surface of the SiC substrate;
形成于SiC外延层表面的两p型离子注入区和两n型离子注入区，且每一n型离子注入区位于一p型离子注入区内；Forming two p-type ion implantation regions and two n-type ion implantation regions on the surface of the SiC epitaxial layer, and each n-type ion implantation region is located in a p-type ion implantation region;
一氧化层，该氧化层覆盖两p型离子注入区之间的SiC外延层，并覆盖每一p型离子注入区和每一n型离子注入区的部分区域，且两p型离子注入区之间的氧化层厚度大于其余区域的氧化层厚度；An oxide layer covering the SiC epitaxial layer between the two p-type ion implantation regions and covering each p-type ion implantation region and a partial region of each n-type ion implantation region, and the two p-type ion implantation regions The thickness of the oxide layer is greater than the thickness of the oxide layer in the remaining regions;
一栅极，覆盖于氧化层的表面；a gate covering the surface of the oxide layer;
一介质层，该介质层将栅极包覆，且介质层的两侧各设置有一源级接触孔；a dielectric layer, the dielectric layer is covered by a gate, and a source-level contact hole is disposed on each side of the dielectric layer;
一源级金属层，覆盖于两源级接触孔和介质层的表面，且源级金属层与每一源级 接触孔底部的p型离子注入区和n型离子注入区的接触均为欧姆接触；a source-level metal layer covering the surface of the two source-level contact holes and the dielectric layer, and the source-level metal layer is in ohmic contact with the p-type ion implantation region and the n-type ion implantation region at the bottom of each source-level contact hole ;
一漏极金属层，覆盖于SiC衬底的背面，且漏极金属层与SiC衬底的背面的接触为欧姆接触。A drain metal layer overlies the back side of the SiC substrate, and the contact of the drain metal layer with the back side of the SiC substrate is an ohmic contact.
本发明所记载的任何范围包括端值以及端值之间的任何数值以及端值或者端值之间的任意数值所构成的任意子范围。Any range recited in the present invention includes any value between the end value and the end value, and any subrange of any value between the end value or the end value.
如无特殊说明，本发明中的各原料均可通过市售购买获得，本发明中所用的设备可采用所属领域中的常规设备或参照所属领域的现有技术进行。Unless otherwise specified, each of the raw materials in the present invention can be obtained by commercially available purchase, and the apparatus used in the present invention can be carried out by using conventional equipment in the art or by referring to the prior art in the related art.
与现有技术相比较，本发明具有如下有益效果：Compared with the prior art, the present invention has the following beneficial effects:
1)本发明的SiC基DI-MOSFET的制备方法，通过氧离子注入和高温热氧化形成氧化层，且氧离子注入区的氧化层厚度大于其余区域的氧化层厚度，即增大了栅极与两p型离子注入区之间的SiC外延层之间的氧化层厚度，从而降低了DI-MOSFET器件的栅漏电容，进而进一步提高器件的工作频率，降低器件的动态损耗。1) The method for preparing a SiC-based DI-MOSFET of the present invention, wherein an oxide layer is formed by oxygen ion implantation and high-temperature thermal oxidation, and an oxide layer thickness of the oxygen ion implantation region is larger than that of the remaining region, that is, the gate electrode is increased. The thickness of the oxide layer between the SiC epitaxial layers between the two p-type ion implantation regions reduces the gate-drain capacitance of the DI-MOSFET device, thereby further increasing the operating frequency of the device and reducing the dynamic loss of the device.
2)本发明的SiC基DI-MOSFET，通过增大了栅极与两p型离子注入区之间的SiC外延层之间的氧化层厚度，从而降低了DI-MOSFET器件的栅漏电容，进而进一步提高器件的工作频率，降低器件的动态损耗。2) The SiC-based DI-MOSFET of the present invention reduces the gate-drain capacitance of the DI-MOSFET device by increasing the thickness of the oxide layer between the SiC epitaxial layer between the gate and the two p-type ion implantation regions, thereby further reducing the gate-drain capacitance of the DI-MOSFET device. Further increase the operating frequency of the device and reduce the dynamic loss of the device.
下面结合附图对本发明的具体实施方式作进一步详细的说明The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
图1为本发明实施例提供的SiC基DI-MOSFET的制备方法的流程图；1 is a flow chart of a method for fabricating a SiC-based DI-MOSFET according to an embodiment of the present invention;
图2-图8为本发明实施例提供的SiC基DI-MOSFET的制备方法的步骤示意图。2-8 are schematic diagrams showing steps of a method for fabricating a SiC-based DI-MOSFET according to an embodiment of the present invention.
为了更清楚地说明本发明，下面结合优选实施例对本发明做进一步的说明。本领域技术人员应当理解，下面所具体描述的内容是说明性的而非限制性的，不应以此限制本发明的保护范围。In order to more clearly illustrate the invention, the invention will be further described in conjunction with the preferred embodiments. It should be understood by those skilled in the art that the following detailed description is intended to be illustrative and not restrictive.
实施例1Example 1
本实施例提供一种SiC基DI-MOSFET的制备方法，如图1所示，该制备方法包括如下步骤：This embodiment provides a method for preparing a SiC-based DI-MOSFET. As shown in FIG. 1, the preparation method includes the following steps:
S1：选取在SiC衬底1正面外延生长一SiC外延层2后得到的SiC外延基片，如图2所示；S1: selecting an SiC epitaxial substrate obtained by epitaxially growing a SiC epitaxial layer 2 on the front surface of the SiC substrate 1, as shown in FIG. 2;
S2：利用光刻掩膜向SiC外延层2表面的部分区域注入p型离子，形成两p型离子注入区3；然后利用光刻掩膜向每一p型离子注入区3表面的部分区域注入n 型离子，在每一p型离子注入区3形成一n型离子注入区4；再通过一次退火激活注入的p型离子和n型离子，如图3所示；S2: implanting p-type ions into a partial region of the surface of the SiC epitaxial layer 2 by using a photolithography mask to form two p-type ion implantation regions 3; and then implanting a partial region of the surface of each p-type ion implantation region 3 by using a photolithography mask N-type ions, forming an n-type ion implantation region 4 in each p-type ion implantation region 3; and injecting the injected p-type ions and n-type ions by one annealing, as shown in FIG. 3;
S3：利用光刻掩膜向位于两p型离子注入区3之间的SiC外延层2表面的部分区域注入氧离子，形成氧离子注入区5，如图4所示；S3: implanting oxygen ions into a partial region of the surface of the SiC epitaxial layer 2 between the two p-type ion implantation regions 3 by using a photolithography mask to form an oxygen ion implantation region 5, as shown in FIG. 4;
S4：进行高温热氧化处理，在SiC外延层2(包括p型离子注入区3、n型离子注入区4和氧离子注入区5)的表面形成一氧化层6，且氧离子注入区5的氧化层6厚度大于SiC外延层2表面其余区域的氧化层6厚度，如图5所示；S4: performing a high-temperature thermal oxidation treatment to form an oxide layer 6 on the surface of the SiC epitaxial layer 2 (including the p-type ion implantation region 3, the n-type ion implantation region 4, and the oxygen ion implantation region 5), and the oxygen ion implantation region 5 The thickness of the oxide layer 6 is greater than the thickness of the oxide layer 6 in the remaining area of the surface of the SiC epitaxial layer 2, as shown in FIG. 5;
S5：在氧化层6表面沉积一多晶硅层，然后利用光刻掩膜将氧离子注入区5两侧的部分多晶硅层刻蚀去除，形成栅极7，如图6所示；S5: depositing a polysilicon layer on the surface of the oxide layer 6, and then etching a part of the polysilicon layer on both sides of the oxygen ion implantation region 5 by using a photolithography mask to form a gate electrode 7, as shown in FIG. 6;
S6：在栅极7上沉积一介质层8，使得介质层8将栅极7包覆，然后利用光刻掩膜将两p型离子注入区3表面的介质层8和氧化层6均刻蚀去除，在介质层8的每一侧形成一源级接触孔，且每一源级接触孔的底部为p型离子注入区3和n型离子注入区4表面裸露的部分区域，如图7所示；S6: depositing a dielectric layer 8 on the gate electrode 7, so that the dielectric layer 8 coats the gate electrode 7, and then etching the dielectric layer 8 and the oxide layer 6 on the surface of the two p-type ion implantation regions 3 by using a photolithography mask. Removing, a source-level contact hole is formed on each side of the dielectric layer 8, and the bottom of each source-level contact hole is a bare portion of the surface of the p-type ion implantation region 3 and the n-type ion implantation region 4, as shown in FIG. Show
S7：在两源级接触孔和介质层8的表面沉积一源级金属层9，在SiC衬底1的背面沉积一漏极金属层10，然后通过二次退火使得源级金属层9与每一源级接触孔底部的p型离子注入区3和n型离子注入区4均形成欧姆接触，且漏极金属层10与SiC衬底1的背面形成欧姆接触，如图8所示。S7: depositing a source metal layer 9 on the surface of the two source contact holes and the dielectric layer 8, depositing a drain metal layer 10 on the back surface of the SiC substrate 1, and then causing the source metal layer 9 and each by secondary annealing. The p-type ion implantation region 3 and the n-type ion implantation region 4 at the bottom of a source-level contact hole each form an ohmic contact, and the drain metal layer 10 forms an ohmic contact with the back surface of the SiC substrate 1, as shown in FIG.
上述步骤S3中，氧离子注入区5的氧离子的注入深度为30nm至1000nm，氧离子注入区5的氧离子的注入浓度为1x10
18cm
-3至1x10
22cm
-3。
In the above step S3, the oxygen ion implantation depth of the oxygen ion implantation region 5 is 30 nm to 1000 nm, and the oxygen ion implantation concentration of the oxygen ion implantation region 5 is 1 x 10 18 cm -3 to 1 x 10 22 cm -3 .
上述步骤S4中，高温热氧化处理的温度为600℃至2000℃。In the above step S4, the temperature of the high temperature thermal oxidation treatment is 600 ° C to 2000 ° C.
上述步骤S2中，一次退火的温度为1500℃至1900℃。In the above step S2, the temperature of one annealing is 1500 ° C to 1900 ° C.
上述步骤S7中，二次退火的温度为800℃至1200℃。In the above step S7, the temperature of the secondary annealing is 800 ° C to 1200 ° C.
上述光刻掩膜指芯片加工技术中由光刻工艺形成的掩膜，其可以是用于离子注入过程的遮挡材料，也可以是用于刻蚀工艺中的掩蔽材料。上述光刻掩膜的材质可能是光刻胶，也可能是其他材料，比如介质、金属等。The above lithography mask refers to a mask formed by a photolithography process in a chip processing technique, which may be an occlusion material for an ion implantation process or a masking material used in an etch process. The material of the above lithography mask may be a photoresist or other materials such as a medium, a metal, or the like.
本实施例还提供一种SiC基DI-MOSFET，该SiC基DI-MOSFET采用上述制备方法制得，其包括：The embodiment further provides a SiC-based DI-MOSFET, which is prepared by the above preparation method, and includes:
一SiC外延基片，该SiC外延基片包括SiC衬底1和在SiC衬底1正面外延生长的一SiC外延层2；a SiC epitaxial substrate comprising a SiC substrate 1 and an SiC epitaxial layer 2 epitaxially grown on the front surface of the SiC substrate 1;
形成于SiC外延层2表面的两p型离子注入区3和两n型离子注入区4，且每一 n型离子注入区4位于一p型离子注入区3内；Forming two p-type ion implantation regions 3 and two n-type ion implantation regions 4 on the surface of the SiC epitaxial layer 2, and each n-type ion implantation region 4 is located in a p-type ion implantation region 3;
一氧化层6，该氧化层6覆盖两p型离子注入区3之间的SiC外延层2，并覆盖每一p型离子注入区3和每一n型离子注入区4的部分区域，且两p型离子注入区3之间的氧化层6厚度大于其余区域的氧化层6厚度；An oxide layer 6 covering the SiC epitaxial layer 2 between the two p-type ion implantation regions 3, and covering each p-type ion implantation region 3 and a partial region of each n-type ion implantation region 4, and two The thickness of the oxide layer 6 between the p-type ion implantation regions 3 is greater than the thickness of the oxide layer 6 in the remaining regions;
一栅极7，覆盖于氧化层6的表面；a gate 7 covering the surface of the oxide layer 6;
一介质层8，该介质层8将栅极7包覆，且介质层8的两侧各设置有一源级接触孔；a dielectric layer 8, the dielectric layer 8 is covered with a gate 7, and a dielectric contact hole is disposed on each side of the dielectric layer 8;
一源级金属层9，覆盖于两源级接触孔和介质层8的表面，且源级金属层9与每一源级接触孔底部的p型离子注入区3和n型离子注入区4的接触均为欧姆接触；a source-level metal layer 9 covering the surfaces of the two source-level contact holes and the dielectric layer 8, and the source-level metal layer 9 and the p-type ion implantation region 3 and the n-type ion implantation region 4 at the bottom of each source-level contact hole The contacts are all ohmic contacts;
一漏极金属层10，覆盖于SiC衬底1的背面，且漏极金属层10与SiC衬底1的背面的接触为欧姆接触。A drain metal layer 10 covers the back surface of the SiC substrate 1, and the contact of the drain metal layer 10 with the back surface of the SiC substrate 1 is an ohmic contact.
显然，本发明的上述实施例仅仅是为清楚地说明本发明所作的举例，而并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无法对所有的实施方式予以穷举。凡是属于本发明的技术方案所引伸出的显而易见的变化或变动仍处于本发明的保护范围之列。It is apparent that the above-described embodiments of the present invention are merely illustrative of the present invention and are not intended to limit the embodiments of the present invention. Other variations or modifications of the various forms may be made by those skilled in the art in light of the above description. It is not possible to exhaust all implementations here. Obvious changes or variations that come within the scope of the invention are still within the scope of the invention.
Claims (7)
- 一种SiC基DI-MOSFET的制备方法，其特征在于，包括如下步骤：A method for preparing a SiC-based DI-MOSFET, comprising the steps of:S1：选取在SiC衬底(1)正面外延生长一SiC外延层(2)后得到的SiC外延基片；S1: selecting an SiC epitaxial substrate obtained by epitaxially growing a SiC epitaxial layer (2) on the front surface of the SiC substrate (1);S2：利用光刻掩膜向SiC外延层(2)表面的部分区域注入p型离子，形成两p型离子注入区(3)；然后利用光刻掩膜向每一p型离子注入区(3)表面的部分区域注入n型离子，在每一p型离子注入区(3)形成一n型离子注入区(4)；再通过一次退火激活注入的p型离子和n型离子；S2: using a photolithographic mask to implant p-type ions into a partial region of the surface of the SiC epitaxial layer (2) to form two p-type ion implantation regions (3); and then using a photolithographic mask to each p-type ion implantation region (3) a portion of the surface is implanted with n-type ions, an n-type ion implantation region (4) is formed in each of the p-type ion implantation regions (3); and the implanted p-type ions and n-type ions are activated by one annealing;S3：利用光刻掩膜向位于两p型离子注入区(3之间的SiC外延层(2)表面的部分区域注入氧离子，形成氧离子注入区(5)；S3: using a lithography mask to implant oxygen ions in a portion of the surface of the SiC epitaxial layer (2) between the two p-type ion implantation regions (3) to form an oxygen ion implantation region (5);S4：进行高温热氧化处理，在SiC外延层(2)的表面形成一氧化层(6)，且氧离子注入区(5)的氧化层(6)厚度大于SiC外延层(2)表面其余区域的氧化层(6)厚度；S4: performing a high-temperature thermal oxidation treatment to form an oxide layer (6) on the surface of the SiC epitaxial layer (2), and the oxide layer (6) of the oxygen ion implantation region (5) has a thickness larger than that of the remaining surface of the SiC epitaxial layer (2) Oxide layer (6) thickness;S5：在氧化层(6)表面沉积一多晶硅层，然后利用光刻掩膜将氧离子注入区(5)两侧的部分多晶硅层刻蚀去除，形成栅极(7)；S5: depositing a polysilicon layer on the surface of the oxide layer (6), and then etching a part of the polysilicon layer on both sides of the oxygen ion implantation region (5) by using a photolithography mask to form a gate electrode (7);S6：在栅极(7)上沉积一介质层(8)，使得介质层(8)将栅极(7)包覆，然后利用光刻掩膜将两p型离子注入区(3)表面的介质层(8)和氧化层(6)均刻蚀去除，在介质层(8)的每一侧形成一源级接触孔，且每一源级接触孔的底部为p型离子注入区(3)和n型离子注入区(4)表面裸露的部分区域；S6: depositing a dielectric layer (8) on the gate (7), so that the dielectric layer (8) coats the gate (7), and then implants the surface of the two p-type ions into the region (3) by using a photolithographic mask. The dielectric layer (8) and the oxide layer (6) are both etched and removed, and a source-level contact hole is formed on each side of the dielectric layer (8), and the bottom of each source-level contact hole is a p-type ion implantation region (3) And an exposed portion of the surface of the n-type ion implantation region (4);S7：在两源级接触孔和介质层(8)的表面沉积一源级金属层(9)，在SiC衬底(1)的背面沉积一漏极金属层(10)，然后通过二次退火使得源级金属层(9)与源级接触孔底部的p型离子注入区(3)和n型离子注入区(4)均形成欧姆接触，且漏极金属层(10)与SiC衬底(1)的背面形成欧姆接触。S7: depositing a source metal layer (9) on the surface of the two-source contact hole and the dielectric layer (8), depositing a drain metal layer (10) on the back surface of the SiC substrate (1), and then performing second annealing The source-level metal layer (9) is formed into an ohmic contact with the p-type ion implantation region (3) and the n-type ion implantation region (4) at the bottom of the source-level contact hole, and the drain metal layer (10) and the SiC substrate ( The back side of 1) forms an ohmic contact.
- 根据权利要求1所述的SiC基DI-MOSFET的制备方法，其特征在于，所述步骤S3中，所述氧离子注入区(5)的氧离子的注入深度为30nm至1000nm。The method of fabricating a SiC-based DI-MOSFET according to claim 1, wherein in the step S3, the oxygen ion implantation region (5) has an implantation depth of oxygen ions of 30 nm to 1000 nm.
- 根据权利要求1所述的SiC基DI-MOSFET的制备方法，其特征在于，所述步骤S3中，所述氧离子注入区(5)的氧离子的注入浓度为1x10 18cm -3至1x10 22cm -3。 The method for fabricating a SiC-based DI-MOSFET according to claim 1, wherein in the step S3, the oxygen ion implantation region (5) has an oxygen ion implantation concentration of 1 x 10 18 cm -3 to 1 x 10 22 Cm -3 .
- 根据权利要求1所述的SiC基DI-MOSFET的制备方法，其特征在于，所述一次退火的温度为1500℃至1900℃。The method of fabricating a SiC-based DI-MOSFET according to claim 1, wherein the temperature of the primary annealing is 1500 ° C to 1900 ° C.
- 根据权利要求1所述的SiC基DI-MOSFET的制备方法，其特征在于，上述步骤S4中，所述高温热氧化处理的温度为600℃至2000℃。The method of manufacturing a SiC-based DI-MOSFET according to claim 1, wherein in the step S4, the temperature of the high-temperature thermal oxidation treatment is 600 ° C to 2000 ° C.
- 根据权利要求1所述的SiC基DI-MOSFET的制备方法，其特征在于，所述二次退火的温度为800℃至1200℃。The method of fabricating a SiC-based DI-MOSFET according to claim 1, wherein the temperature of the second annealing is from 800 ° C to 1200 ° C.
- 一种SiC基DI-MOSFET，该SiC基DI-MOSFET采用权利要求1-6任一项所述的制备方法制得，其特征在于，其包括：A SiC-based DI-MOSFET obtained by the preparation method according to any one of claims 1 to 6, characterized in that it comprises:一SiC外延基片，该SiC外延基片包括SiC衬底(1)和在SiC衬底(1)正面外延生长的一SiC外延层(2)；a SiC epitaxial substrate comprising a SiC substrate (1) and a SiC epitaxial layer (2) epitaxially grown on the front surface of the SiC substrate (1);形成于SiC外延层(2)表面的两p型离子注入区(3)和两n型离子注入区(4)，且每一n型离子注入区(4)位于一p型离子注入区(3)内；Two p-type ion implantation regions (3) and two n-type ion implantation regions (4) formed on the surface of the SiC epitaxial layer (2), and each n-type ion implantation region (4) is located in a p-type ion implantation region (3) )Inside;一氧化层(6)，该氧化层(6)覆盖两p型离子注入区(3)之间的SiC外延层(2)，并覆盖每一p型离子注入区(3)和每一n型离子注入区(4)的部分区域，且两p型离子注入区(3)之间的氧化层(6)厚度大于其余区域的氧化层(6)厚度；An oxide layer (6) covering the SiC epitaxial layer (2) between the two p-type ion implantation regions (3) and covering each p-type ion implantation region (3) and each n-type a partial region of the ion implantation region (4), and a thickness of the oxide layer (6) between the two p-type ion implantation regions (3) is greater than a thickness of the oxide layer (6) of the remaining region;一栅极(7)，覆盖于氧化层(6)的表面；a gate (7) covering the surface of the oxide layer (6);一介质层(8)，该介质层(8)将栅极(7)包覆，且介质层(8)的两侧各设置有一源级接触孔；a dielectric layer (8), the dielectric layer (8) is covered with a gate (7), and a source-level contact hole is disposed on each side of the dielectric layer (8);一源级金属层(9)，覆盖于两源级接触孔和介质层(8)的表面，且源级金属层(9)与每一源级接触孔底部的p型离子注入区(3)和n型离子注入区(4)的接触均为欧姆接触；a source metal layer (9) covering the surface of the two source contact holes and the dielectric layer (8), and the source metal layer (9) and the p-type ion implantation region at the bottom of each source contact hole (3) The contact with the n-type ion implantation region (4) is an ohmic contact;一漏极金属层(10)，覆盖于SiC衬底(1)的背面，且漏极金属层(10)与SiC衬底(1)的背面的接触为欧姆接触。A drain metal layer (10) covers the back surface of the SiC substrate (1), and the contact of the drain metal layer (10) with the back surface of the SiC substrate (1) is an ohmic contact.
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| PCT/CN2018/115873 WO2019137093A1 (en) | 2018-01-12 | 2018-11-16 | Sic-based di-mosfet preparation method and sic-based di-mosfet |
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| CN (1) | CN108257872A (en) |
| WO (1) | WO2019137093A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108257872A (en) * | 2018-01-12 | 2018-07-06 | 北京品捷电子科技有限公司 | The preparation method of SiC bases DI-MOSFET a kind of and SiC bases DI-MOSFET |
| CN111129155A (en) * | 2019-12-25 | 2020-05-08 | 重庆伟特森电子科技有限公司 | Preparation method of low-gate-drain capacitance silicon carbide DI-MOSFET |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998019344A1 (en) * | 1996-10-25 | 1998-05-07 | Siliconix Incorporated | Threshold adjust in vertical dmos transistor |
| JP2000100747A (en) * | 1998-09-18 | 2000-04-07 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| CN103168361A (en) * | 2010-07-26 | 2013-06-19 | 住友电气工业株式会社 | Semiconductor device |
| CN105161540A (en) * | 2015-09-15 | 2015-12-16 | 电子科技大学 | VDMOS device structure with low miller capacitance and manufacturing method of VDMOS device structure |
| CN106384747A (en) * | 2016-11-25 | 2017-02-08 | 东莞市联洲知识产权运营管理有限公司 | Field effect transistor |
| CN108257872A (en) * | 2018-01-12 | 2018-07-06 | 北京品捷电子科技有限公司 | The preparation method of SiC bases DI-MOSFET a kind of and SiC bases DI-MOSFET |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014107420A (en) * | 2012-11-28 | 2014-06-09 | Sumitomo Electric Ind Ltd | Silicon carbide semiconductor device and method for manufacturing the same |
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2018
- 2018-01-12 CN CN201810031538.7A patent/CN108257872A/en active Pending
- 2018-11-16 WO PCT/CN2018/115873 patent/WO2019137093A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998019344A1 (en) * | 1996-10-25 | 1998-05-07 | Siliconix Incorporated | Threshold adjust in vertical dmos transistor |
| JP2000100747A (en) * | 1998-09-18 | 2000-04-07 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| CN103168361A (en) * | 2010-07-26 | 2013-06-19 | 住友电气工业株式会社 | Semiconductor device |
| CN105161540A (en) * | 2015-09-15 | 2015-12-16 | 电子科技大学 | VDMOS device structure with low miller capacitance and manufacturing method of VDMOS device structure |
| CN106384747A (en) * | 2016-11-25 | 2017-02-08 | 东莞市联洲知识产权运营管理有限公司 | Field effect transistor |
| CN108257872A (en) * | 2018-01-12 | 2018-07-06 | 北京品捷电子科技有限公司 | The preparation method of SiC bases DI-MOSFET a kind of and SiC bases DI-MOSFET |
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