CN109243979A - Semiconductor power device and preparation method thereof - Google Patents
Semiconductor power device and preparation method thereof Download PDFInfo
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- CN109243979A CN109243979A CN201710556890.8A CN201710556890A CN109243979A CN 109243979 A CN109243979 A CN 109243979A CN 201710556890 A CN201710556890 A CN 201710556890A CN 109243979 A CN109243979 A CN 109243979A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000002360 preparation method Methods 0.000 title abstract description 4
- 238000009413 insulation Methods 0.000 claims abstract description 114
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 229920005591 polysilicon Polymers 0.000 claims abstract description 85
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims abstract description 70
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 27
- 230000003647 oxidation Effects 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 263
- 239000011241 protective layer Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000012298 atmosphere Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 27
- 239000003518 caustics Substances 0.000 abstract description 5
- 206010020843 Hyperthermia Diseases 0.000 abstract description 2
- 230000036031 hyperthermia Effects 0.000 abstract description 2
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
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- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 239000011261 inert gas Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention proposes semiconductor power devices and preparation method thereof.The method of the production semiconductor power device includes: to sequentially form epitaxial layer, well region, source region and body contact zone in the side of substrate；The first rank gate insulation sub-layer is formed in the side of the separate substrate of epitaxial layer, well region, source region and body contact zone；Second-order gate insulation sub-layer and the first polysilicon sub-layer are formed far from the side of substrate in the first rank gate insulation sub-layer；The second polysilicon sub-layer is formed in the side of the separate substrate of second-order gate insulation sub-layer and the first polysilicon sub-layer and is lithographically formed grid；Wherein, second-order gate insulation sub-layer is by carrying out the formation of localized hyperthermia's oxidation processes to the first polysilicon layer.Production method proposed by the invention, high-temperature oxydation successively can be carried out to polysilicon sub-layer and obtain multistage gate insulation layer structure, it avoids lithographic method to make its surface more smooth and be easy to cause surface irregularity or residual corrosive agent, and then improve the use reliability of semiconductor power device.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically, the present invention relates to semiconductor power devices and preparation method thereof.
Background technique
Now, carbofrax material has excellent physically and electrically characteristic, with its big forbidden bandwidth, high critical breakdown potential
The particular advantages such as field, high heat conductance and high saturation drift velocity become production high pressure, high power, high temperature resistant, high frequency, Flouride-resistani acid phesphatase
The ideal material of device has broad application prospects at military and civil aspect.And silicon carbide power device has switch speed
The advantage that degree is fast, conducting resistance is small, lesser drift layer thickness can realize that higher breakdown voltage is horizontal, reduce power and open
The volume of module is closed, energy consumption is reduced, it is with the obvious advantage in the application fields such as power switch, converter.
Currently, improving the reliability of MOSFET element to reduce the electric field strength that gate oxide is born, it is thus proposed that whole
Body is in the multistage gate oxide structure of symmetrical multistage " step " shape.But since its multistage gate oxide structure is by etching
Gate oxide and formed, which can cause to damage to gate oxide, to be unfavorable for power device reliably and with long-term
Property.
Therefore, the method for making the multistage gate oxide structure in semiconductor power device at this stage still has much room for improvement.
Summary of the invention
The present invention is directed to solve at least some of the technical problems in related technologies.
The present invention is the following discovery based on inventor and completes:
The present inventor has found that the etching technics used at this stage exists everywhere due to lithographic method itself in the course of the research
The different defect of etch rate, no matter wet etching or dry etching, can make etching after gate oxide surface occur not
Smooth problem, especially wet etching are also easy to cause gate oxide remained on surface corrosive liquid, to influence the semiconductor
Power device long-term usability and stability.
The technical issues of damage is caused to multistage gate oxide structure, the application are easy in order to solve above-mentioned etching technics
Propose a kind of method for making Metal-Oxide Semiconductor field effect transistor (MOSFET) device, multistage gate insulation layer
Structure includes first grid insulating sublayer and at least one second gate insulating sublayer, and second gate insulating sublayer is by more than first
The partial region of crystal silicon layer carries out high temperature oxidation process and obtains.The gate electrode insulation surface that the production method obtains is smooth, keeps away
Exempt from lithographic method to be easy to cause surface irregularity or remain the adverse effect of corrosive agent, it can also be by adjusting each gate insulation sub-layer
Size design the specific size of step, to improve the use reliability of the semiconductor power device.
In view of this, an object of the present invention is to provide a kind of surface that can make multistage gate insulation layer structure is more flat
Whole, the higher production semiconductor power device method of step dimension precision.
In the first aspect of the present invention, the invention proposes a kind of methods for making semiconductor power device.
According to an embodiment of the invention, the described method includes: sequentially forming epitaxial layer, well region, source region in the side of substrate
And body contact zone, wherein the side of the substrate is arranged in the epitaxial layer, and the well region is using the center line of the substrate as axis
It is symmetrically disposed in side of the epitaxial layer far from the substrate, the source region and the body contact zone are separately with institute
The center line for stating substrate is that side of the well region far from the substrate is axisymmetrically arranged in；In the epitaxial layer, well region, source
Area and the side far from the substrate of body contact zone form the first rank gate insulation sub-layer；It is remote in the first rank gate insulation sub-layer
Side from the substrate forms second-order gate insulation sub-layer and the first polysilicon sub-layer；In the second-order gate insulation sub-layer
With the side far from the substrate of the first polysilicon sub-layer, the second polysilicon sub-layer is formed, and sub- to second polysilicon
Layer and the first polysilicon sub-layer carry out photoetching and form grid；Wherein, the formation second-order gate insulation sub-layer and first
The step of polysilicon sub-layer, further comprises: in the side of the first rank gate insulation sub-layer far from the substrate, sequentially forming
First polysilicon layer and have patterned protective layer；To the region that do not protected by the protective layer of first polysilicon layer
High temperature oxidation process is carried out, to obtain second-order gate insulation sub-layer and the first polysilicon sub-layer；And the removal protective layer.
Inventor it was unexpectedly observed that using the embodiment of the present invention production semiconductor power device method, can be layer by layer
Multistage gate insulation layer structure is obtained and carrying out high temperature oxidation process to polysilicon sub-layer, to make the table of multistage gate insulation layer
Face is more smooth, avoids lithographic method and be easy to cause surface irregularity or remain the adverse effect of corrosive agent, and can be by adjusting
The size of each gate insulation sub-layer accurately designs the size of step, so that the use for improving the semiconductor power device is reliable
Property.
In the second aspect of the present invention, the invention proposes a kind of semiconductor power devices.
According to an embodiment of the invention, the semiconductor power device is made by above-mentioned method.
Inventor it was unexpectedly observed that the embodiment of the present invention semiconductor power device, the surface of multistage gate insulation layer is more
Smooth and dimensional accuracy is higher, so as to keep the long-term reliability of the semiconductor power device more preferable.Those skilled in the art's energy
Enough understand, feature and advantage described in the method above for production semiconductor power device are still applied to this and partly lead
Body power device, details are not described herein.
In the third aspect of the present invention, the invention proposes a kind of semiconductor power devices.
According to an embodiment of the invention, the semiconductor power device includes: substrate；Epitaxial layer, the epitaxial layer setting
In the side of the substrate；Well region, the well region are remote for the epitaxial layer is axisymmetrically arranged in the center line of the substrate
Side from the substrate；Source region, the source region are separate for the well region is axisymmetrically arranged in the center line of the substrate
The side of the substrate；Body contact zone, the body contact zone are that the trap is axisymmetrically arranged in the center line of the substrate
Side of the area far from the substrate；Gate insulation layer, the gate insulation layer be arranged in the well region and the source region far from described
The side of substrate, the gate insulation layer is the multiple-rank arrangement being made of multiple gate insulation sub-layers, and is formed by silica；Grid
Pole, side of the gate insulation layer far from the substrate is arranged in the grid, and the grid is by multiple polysilicon sub-layer groups
At.
Inventor it was unexpectedly observed that the embodiment of the present invention semiconductor power device, the surface of multistage gate insulation layer is more
Smooth and dimensional accuracy is higher, so as to keep the long-term reliability of the semiconductor power device more preferable.
Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 is the method flow diagram of the production semiconductor power device of one embodiment of the invention；
Fig. 2 is the schematic diagram of product structure of the production method step S100 of one embodiment of the invention；
Fig. 3 is the schematic diagram of product structure of the production method step S200 of one embodiment of the invention；
Fig. 4 is the semi-finished product structure schematic diagram of the production method step S310 of one embodiment of the invention；
Fig. 5 is the semi-finished product structure schematic diagram of the production method step S310 of one embodiment of the invention；
Fig. 6 is the schematic diagram of product structure of the production method step S310 of one embodiment of the invention；
Fig. 7 is the schematic diagram of product structure of the production method step S320 of one embodiment of the invention；
Fig. 8 is the schematic diagram of product structure of the production method step S330 of one embodiment of the invention；
Fig. 9 is the schematic diagram of product structure of the production method step S300 of another embodiment of the present invention；
Figure 10 is the semi-finished product structure schematic diagram of the production method step S400 of one embodiment of the invention；
Figure 11 is the schematic diagram of product structure of the production method step S400 of one embodiment of the invention；
Figure 12 is the schematic diagram of product structure of the production method step S500 of one embodiment of the invention；
Figure 13 is the semi-finished product structure schematic diagram of the production method step S600 of one embodiment of the invention；
Figure 14 is the semi-finished product structure schematic diagram of the production method step S600 of one embodiment of the invention；
Figure 15 is the schematic diagram of product structure of the production method step S600 of one embodiment of the invention；
Figure 16 is the structural schematic diagram of the semiconductor power device of one embodiment of the invention；
Figure 17 is the structural schematic diagram of the semiconductor power device of another embodiment of the present invention；
Figure 18 is the method flow diagram of the production semiconductor power device of another embodiment of the present invention；
Figure 19 is the method flow diagram of the production semiconductor power device of another embodiment of the present invention.
Appended drawing reference
100 substrates
110 epitaxial layers
120 well regions
130 source regions
140 body contact zones
200 gate insulation layers
210 first rank gate insulation sub-layers
220 second-order gate insulation sub-layers
300 grids
310 first polysilicon layers
320 first polysilicon sub-layers
330 second polysilicon sub-layers
400 protective layers
410 compacted zones
500 spacer medium layers
600 contact holes
700 drain electrodes
800 source electrodes
Specific embodiment
The embodiment of the present invention is described below in detail, those skilled in the art is it will be appreciated that following example is intended for solving
The present invention is released, and is not construed as limitation of the present invention.Unless stated otherwise, it is not expressly recited in embodiment below specific
Technology or conditions, those skilled in the art can be according to common technology or conditions in the art or according to product description
It carries out.Reagents or instruments used without specified manufacturer is the conventional products that can be bought by city.
In one aspect of the invention, the invention proposes a kind of methods for making semiconductor power device.Referring to Fig.1~
15, production method of the invention is described in detail.
According to an embodiment of the invention, referring to Fig.1, which includes:
S100: in the side of substrate, epitaxial layer, well region, source region and body contact zone are sequentially formed.
In this step, epitaxial layer 110, well region 120, source region 130 are sequentially formed in the side of substrate 100 with reference to Fig. 2
With body contact zone 140；Wherein, the side of substrate 100 is arranged in epitaxial layer 110, and well region 120 is with the center line AA ' of substrate 100
Side of the epitaxial layer 110 far from substrate 100 is axisymmetrically set, and source region 130 and body contact zone 140 are separately with substrate
100 center line AA ' is that side of the well region 120 far from substrate 100 is axisymmetrically arranged in.
According to an embodiment of the invention, substrate 100, epitaxial layer 110, well region 120, source region 130 and body contact zone 140 tool
Body material is not particularly limited, and those skilled in the art can be designed according to the requirement of the semiconductor power device
And selection.In some embodiments of the invention, the first conductivity type material may be selected in substrate 100, and epitaxial layer 110 may be selected the
The second conduction type may be selected in one conductivity type material, well region 120, and the first conductivity type material may be selected in source region 130, and body connects
Touching area 140 may be selected the second conductivity type material；Wherein, the first conduction type is selected from one of N-type and p-type, and second leads
Another kind of the electric type in N-type and p-type.In this way, those skilled in the art can be according to the specific of the semiconductor power device
Requirement selection, to determine that the first conduction type is N-type or p-type, to make the scope of application of the semiconductor power device
It is wider.In some specific examples of the invention, substrate 100 can also be is formed by the silicon carbide of the N-type of nitrating.In this way, adopting
With the substrate 100 of above-mentioned material, forbidden bandwidth is big, critical breakdown electric field is high, thermal conductivity is high and saturation drift velocity is high etc. solely
Special advantage can make the semiconductor power device have the advantage that switching speed is fast, conducting resistance is small.
According to an embodiment of the invention, the specific cross-sectional shape of well region 120, source region 130 and body contact zone 140, not
It is particularly limited, specifically such as strip or ring-type, those skilled in the art can be according to the specific of the semiconductor power device
Requirement is designed.In some embodiments of the invention, well region 120, source region 130 and body contact zone 140 cross section
Two can be each independently using substrate center line as the strip of symmetrical centre.In other embodiments of the invention, well region
120, the cross section of source region 130 and body contact zone 140 can be each independently the annular centered on substrate center line.
According to an embodiment of the invention, formed epitaxial layer 110, well region 120, source region 130 and body contact zone 140 specific side
Method is not particularly limited, and those skilled in the art can select according to the specific material of above-mentioned each structure.In the present invention
Some embodiments in, can the silicon carbide substrates 100 of nitrating formed nitrating N-type epitaxy layer 110；Again by being lithographically formed
Exposure mask, and specific region is selected to inject aluminium ion, form the well region 120 of p-type；Then by being lithographically formed exposure mask, and spy is selected
Determine region injection Nitrogen ion, forms the source region 130 of N-type；Later by being lithographically formed exposure mask, and select specific region injection aluminium from
Son forms the body contact zone 140 of p-type；Finally, carrying out the high temperature anneal carrys out activator impurity.In this way, can get the semiconductor function
The semiconductor functional module of rate device.
S200: it is sub- that the first rank gate insulation is formed in the side of the separate substrate of epitaxial layer, well region, source region and body contact zone
Layer.
In this step, with reference to Fig. 3, in the separate substrate of epitaxial layer 110, well region 120, source region 130 and body contact zone 140
100 side forms the first rank gate insulation sub-layer 210.
According to an embodiment of the invention, the specific material of the first rank gate insulation sub-layer 210 is not particularly limited, this field
Technical staff can select according to the specifically used requirement of the semiconductor power device.In some embodiments of the invention,
The first rank gate insulation sub-layer 210 can be to be formed by silica, in this way, the first rank gate insulation sub-layer 210 can be with
Subsequently through the second-order gate insulation sub-layer 220 for carrying out high temperature oxidation process acquisition to polysilicon sub-layer, it is equal that thickness is collectively formed
Even gate insulation layer is whole.
According to an embodiment of the invention, the specific method for forming the first rank gate insulation sub-layer 210 is not particularly limited, this
Field technical staff can select according to the specific material of the gate insulation sub-layer.In some embodiments of the invention, it insulate
Sub-layer 210 can be in the silica generated by thermal oxidation.In this way, can be in epitaxial layer 110, well region 120, source region 130
With the side of the separate substrate 100 of body contact zone 140, thickness is formed uniformly and the gate insulation sub-layer of surfacing.
According to an embodiment of the invention, the specific thickness of the first rank gate insulation sub-layer 210 is not particularly limited, this field
Technical staff can be designed and adjust according to the specific number of steps of the gate insulation layer of multiple-rank arrangement.In some implementations of the invention
In example, by taking second order gate insulation layer structure as an example, the thickness of the first rank gate insulation sub-layer 210 can be 50nm.In this way, can get makes
With the semiconductor power device of better reliability.
S300: in the first side of the rank gate insulation sub-layer far from substrate, second-order gate insulation sub-layer and the first polycrystalline are formed
Silicon sub-layer.
In this step, in 210 side far from substrate 100 of the first rank gate insulation sub-layer, it is sub- to form second-order gate insulation
Layer 220 and the first polysilicon sub-layer 320.According to an embodiment of the invention, forming second-order gate insulation sub-layer 220 and the first polycrystalline
The specific method of silicon sub-layer 320 is not particularly limited, and those skilled in the art can be according to the tool of second-order gate insulation sub-layer 220
Body material is selected.It in some embodiments of the invention, can further comprise S310, S320 with reference to Figure 18, step S300
And S330, each step is described in detail below:
S310: it in the first side of the rank gate insulation sub-layer far from substrate, sequentially forms the first polysilicon layer and there is pattern
The protective layer of change.
In this step, in 210 side far from substrate 100 of the first rank gate insulation sub-layer, the first polysilicon is successively formed
Layer 310 and have patterned protective layer 400.The inventors of the present application found that the first polysilicon layer 310 can be effectively protected
Single order gate insulation sub-layer 210 is influenced from etching, so that product reliability can be improved, and subsequent can also have patterned guarantor
Sheath 400 is exposure mask, and specific region is selected to carry out high temperature oxidation process to the first polysilicon layer 310.
According to an embodiment of the invention, the specific thickness of the first polysilicon layer 310 is not particularly limited, art technology
Personnel can be adjusted according to the requirement and practical manufacturing situation of the semiconductor power device.In some implementations of the invention
In example, by taking second order gate insulation layer structure as an example, the thickness of the first polysilicon layer 310 can be 100nm.In this way, using above-mentioned thickness
First polysilicon layer 310 of degree, can more effectively protect the first rank gate insulation sub-layer 210, and a part as gate insulation layer
It can make the better reliability of the semiconductor power device.
According to an embodiment of the invention, the specific material of protective layer 400 is not particularly limited, as long as the protection of the material
The first polysilicon layer 310 that layer 400 can be effectively protected part is not influenced by high temperature oxidation process, and those skilled in the art can root
It is selected according to the concrete technology condition of high temperature oxidation process.In some embodiments of the invention, protective layer 400 can be selected from nitrogen
SiClx or aluminium oxide.In this way, structure is finer and close using the protective layer 400 of above-mentioned material, it is more that oxidizing gas entrance can be completely cut off
Crystal silicon can more effectively protect the first polysilicon layer of part 310 not influenced by high temperature oxidation process.
According to an embodiment of the invention, the specific thickness of protective layer 400 is not also particularly limited, as long as the guarantor of the thickness
Sheath 400 can protect the first polysilicon layer of part 310 not influenced by high temperature oxidation process, and those skilled in the art can basis
The concrete technology condition of high temperature oxidation process is selected.In some embodiments of the invention, the thickness of protective layer 400 can not
Less than 150nm.In this way, using the protective layer 400 of above-mentioned thickness, can more effectively protect the first polysilicon layer of part 310 not by
High temperature oxidation process influences.
According to an embodiment of the invention, forming the first polysilicon layer 310 and the specific side with patterned protective layer 400
Method is not particularly limited, and those skilled in the art can carry out according to the specific material of the first polysilicon layer 310 and protective layer 400
Selection.In some embodiments of the invention, step S310 can further comprise: Fig. 4 be referred to, in the first rank gate insulation sub-layer
210 sides far from substrate 100 form the first polysilicon layer 310 by chemical vapor deposition method；Referring again to Fig. 5, first
Side of the polysilicon layer 310 far from substrate 100 forms compacted zone 410 by chemical vapor deposition method；It is right then referring to Fig. 6
Compacted zone 410 carries out photoetching treatment, and being formed has patterned protective layer 400.In this way, can it is more efficient, accurately form first
Polysilicon layer 310 and have patterned protective layer 400.
S320: high temperature oxidation process is carried out to the region of the unprotected layer protection of the first polysilicon layer.
In this step, the region that the unprotected layer 400 of the first polysilicon layer 310 is protected is carried out at high-temperature oxydation
Reason, to obtain second-order gate insulation sub-layer 220 and the first polysilicon sub-layer 320, the schematic diagram of product structure which obtains
Please refer to Fig. 7.Specifically, the oxygen of high temperature can make the polysilicon of the first polysilicon layer 310 of part exposure be oxidized to dioxy
SiClx, so that the second-order gate insulation sub-layer 220 with specific pattern is directly formed in the region of unprotected layer 400 protection,
And and surfacing uniform by the thickness of the gate insulation sub-layer of high temperature oxidation process acquisition, so as to make the semiconductor power
The long-time service good reliability of device.
Although present inventor is it was unexpectedly observed that the first polysilicon layer 310 of 400 covering part of protected seam will not
It is aoxidized by gas, but in the intersection of second-order gate insulation sub-layer 220 and the first polysilicon sub-layer 320, due to oxygen gas
Ability with horizontal proliferation, so the partial polysilicon of intersection still can be oxidized, so that it is distinctive to form selective oxidation
Such as the inclined-plane intersection of " beak ", Fig. 7 is specifically please referred to.
According to an embodiment of the invention, the actual conditions of high temperature oxidation process, such as temperature and atmosphere type etc., not by
Special limitation, those skilled in the art can select and adjust according to the specific material of the first polysilicon layer 310 and thickness.
In some embodiments of the invention, the temperature of high temperature oxidation process can be 800~1200 degrees Celsius, and be in purity oxygen or
It is carried out under the atmosphere of high pure oxygen.In this way, can get thickness more evenly and table using the high temperature oxidation process of above-mentioned process conditions
The more smooth second-order gate insulation sub-layer 220 in face.It should be noted that " high pure oxygen " herein specifically refers to purity and is greater than
The oxygen of 99.995v/v%, impurity are also only the N that will not influence oxidation reaction2, the inert gases such as Ar.
According to an embodiment of the invention, the specific cross-sectional shape of the second-order gate insulation sub-layer 220 formed is not by special
Limitation, specifically such as strip, circle or square, those skilled in the art can be according to well region 120, source region 130 and body
The specific cross-sectional shape of contact zone 140 is correspondingly designed.In some embodiments of the invention, second-order gate insulation is sub-
The cross-sectional shape of layer 220 can be strip, in this way, the gate insulation layer of strip cross section can preferably be such that grid and strip is distributed
Semiconductor functional module between insulate.In other embodiments of the invention, the cross section shape of second-order gate insulation sub-layer 220
Shape can be circle, in this way, the gate insulation layer of circular cross section can preferably make the semiconductor function mould of grid and annular spread
It insulate between block.
S330: removal protective layer.
In this step, the protective layer 400 on removal 320 surface of the first polysilicon sub-layer, so not oxidized more than first
Crystal silicon sub-layer 320 can give over to a part of grid.According to an embodiment of the invention, removal protective layer 400 specific method not by
Special limitation, those skilled in the art can select according to the specific material of protective layer 400 and the first polysilicon sub-layer 320
It selects.In some embodiments of the invention, the method for removing protective layer 400 can choose wet etching.In this way, by above-mentioned
Method can effectively cleared first polysilicon sub-layer 320 protective layer 400 remained on surface, and due to the first polysilicon sub-layer 320
Protective effect, the corrosive liquid of wet etching will not cause to damage to the first rank gate insulation sub-layer 210, so as to further mention
The long-time service reliability of the high semiconductor power device.
In some embodiments of the invention, it can get by step S310~S330 by the first rank gate insulation sub-layer 210
The two rank gate insulation layer structures as shown in Figure 8 formed with second gate insulating sublayer 220.In other embodiments of the invention
In, it can continue to repeat step S310~S330, i.e. repeated deposition polysilicon layer, the patterned protective layer of formation, localized hyperthermia
Oxidation processes and removal protective layer, then can form multiple second in 210 side far from substrate 100 of the first rank gate insulation sub-layer
Rank gate insulation sub-layer 220 and multiple first polysilicon sub-layers 320, thus available by the first rank gate insulation sub-layer 210 and multiple
Second gate insulating sublayer 220 forms the gate insulation layer structure of three ranks or three ranks as shown in Figure 9 or more.It should be noted that this
All " multiple " specifically refer to two or more in text.
S400: in the side of the separate substrate of second-order gate insulation sub-layer and the first polysilicon sub-layer, the second polycrystalline is formed
Silicon sub-layer, and photoetching is carried out to the second polysilicon sub-layer and the first polysilicon sub-layer and forms grid.
In some embodiments of the invention, by taking second order gate insulation layer structure as an example, in 220 He of second-order gate insulation sub-layer
The side of the separate substrate 100 of first polysilicon sub-layer 320 forms the second polysilicon sub-layer 330, the knot of the semi-finished product of the step
Structure please refers to Figure 10；And photoetching is carried out to the second polysilicon sub-layer 330 and the first polysilicon sub-layer 320 and forms grid 300, it should
The structure of the product of step please refers to Figure 11.In this way, can be sub- by the first not oxidized polysilicon sub-layer 320 and the second polysilicon
Layer 330 is combined, and can get the grid 300 of the semiconductor power device using photoetching treatment.It should be noted that Figure 11
Middle grid 300 is made of the first polysilicon sub-layer 320 (not marking in figure) and the second polysilicon sub-layer 330 (not marking in figure)
's.
According to an embodiment of the invention, the specific method for forming the second polysilicon layer 330 is not particularly limited, this field
Technical staff can select according to the specific material of the second polysilicon layer 330.In some embodiments of the invention, can be with,
The second polysilicon layer 330 is formed by chemical vapor deposition method.In this way, can more efficient, accurate landform using above method shape
At the second polysilicon layer 330.
According to an embodiment of the invention, the specific thickness of the second polysilicon layer 330 is not particularly limited, as long as the thickness
The second polysilicon layer 330 can effectively constitute the grid of the semiconductor power device, those skilled in the art can basis
The requirement of the semiconductor power device and practical manufacturing situation are adjusted.In some embodiments of the invention, with two
For rank gate insulation layer structure, the thickness of the second polysilicon layer 330 can be 500nm.In this way, using more than the second of above-mentioned thickness
Crystal silicon layer 330, a part that can be used as gate insulation layer can make the better reliability of the semiconductor power device.
In some embodiments of the invention, with reference to Figure 19, which can also further comprise step S500, S600
And S700, the more perfect semiconductor power device of so available structure and function are below described in detail each step:
S500: in the side of the first rank gate insulation sub-layer and the separate substrate of grid, spacer medium layer is formed.
In this step, in the side of the first rank gate insulation sub-layer 210 and the separate substrate 100 of grid 300, isolation is formed
The structure of dielectric layer 500, the product which obtains please refers to Figure 12.
According to an embodiment of the invention, the specific material of spacer medium layer 500 is not particularly limited, those skilled in the art
Member can be selected according to the specifically used requirement of the semiconductor power device and the specific material of grid 200.Of the invention
In some embodiments, spacer medium layer 500 can be the composite construction of layer of silicon dioxide and one layer of boron-phosphorosilicate glass.In this hair
In other bright embodiments, spacer medium layer 500 can be the composite construction of one layer of silicon nitride and one layer of boron-phosphorosilicate glass.Such as
This, the composite construction formed using above-mentioned different materials can make the buffer action of spacer medium layer 500 more preferable, and then make
The better reliability of the semiconductor power device.
According to an embodiment of the invention, the specific method for forming spacer medium layer 500 is not particularly limited, this field skill
Art personnel can select according to the specific material of the spacer medium layer 500.It in some embodiments of the invention, can be first
The side of the separate substrate 100 of rank gate insulation sub-layer 210 and grid 300 is sequentially depositing layer of silicon dioxide or silicon nitride, one layer
Boron-phosphorosilicate glass.In this way, the spacer medium layer 500 of composite construction can be formed, to make the isolation effect of the spacer medium layer 500
More preferably.
S600: carrying out photoetching to spacer medium layer and the first rank gate insulation sub-layer and forms contact hole, contact hole and every
Source electrode is formed far from the side of substrate from dielectric layer, and is formed and is drained in the other side of substrate.
In this step, photoetching is carried out to spacer medium layer 500 and the first rank gate insulation sub-layer 210, and forms contact hole
600 and gate insulation layer 200, the structure of the semi-finished product of the step please refer to Figure 13；It is remote in contact hole 600 and spacer medium layer 500
Side from substrate 100 forms source electrode 700, and the structure of the product of the step please refers to Figure 14；It is formed in the other side of substrate 100
Drain electrode 800, the structure of the product of the step please refers to Figure 15.It should be noted that gate insulation layer 200 is by the first rank in Figure 13
Gate insulation sub-layer 210 (not marked in figure) and second-order gate insulation sub-layer 220 (not marked in figure) composition.
According to an embodiment of the invention, the specific cross-sectional shape of the spacer medium layer 500 after photoetching is not limited particularly
System, specifically such as strip, circle or square etc., those skilled in the art can be according to the tools of second-order gate insulation sub-layer 220
Body cross-sectional shape is correspondingly designed.In some embodiments of the invention, the cross-sectional shape of spacer medium layer 500 can
Think strip.In other embodiments of the invention, the cross-sectional shape of spacer medium layer 500 can be circle.
According to an embodiment of the invention, source electrode 700 and the specific material of drain electrode 800 are not particularly limited, as long as the material
The source-drain electrode that material is formed can form the switch module of the semiconductor power device with grid, and those skilled in the art can basis
The specifically used requirement of the semiconductor power device is designed and selects, and details are not described herein.According to an embodiment of the invention,
The specific method for forming source electrode 700 and drain electrode 800 is not also particularly limited, and those skilled in the art can be according to source electrode 700
It is selected with the specific material of drain electrode 800, details are not described herein.
In conclusion according to an embodiment of the invention, the invention proposes a kind of method for making semiconductor power device,
Multistage gate insulation layer structure can be obtained and carrying out high temperature oxidation process to polysilicon sub-layer layer by layer, to keep multistage grid exhausted
The surface more smooth of edge layer avoids lithographic method and be easy to cause surface irregularity or remain the adverse effect of corrosive agent, and can
The size of step is accurately designed by adjusting the size of each gate insulation sub-layer, to improve making for the semiconductor power device
Use reliability.
In another aspect of the invention, the invention proposes a kind of semiconductor power devices.Implementation according to the present invention
Example, which made by above-mentioned method.
In conclusion according to an embodiment of the invention, multistage grid are exhausted the invention proposes a kind of semiconductor power device
The surface more smooth and dimensional accuracy of edge layer are higher, so as to keep the long-term reliability of the semiconductor power device more preferable.Ability
Field technique personnel are, it is understood that above for feature and advantage described in the method for making semiconductor power device, still
Suitable for the semiconductor power device, details are not described herein.
In another aspect of the invention, the invention proposes a kind of semiconductor power devices.Referring to Fig.1 6~17, to this
The semiconductor power device of invention is described in detail.
According to an embodiment of the invention, the semiconductor power device includes: substrate 100, epitaxial layer 110, trap with reference to Figure 16
Area 120, source region 130, body contact zone 140, gate insulation layer 200 and grid 300；Wherein, substrate 100 is arranged in epitaxial layer 110
Side；Well region 120 is that side of the epitaxial layer 110 far from substrate 100 is axisymmetrically arranged in the center line AA ' of substrate 100；Source
Area 130 is that side of the well region 120 far from substrate 100 is axisymmetrically arranged in the center line AA ' of substrate 100；Body contact zone 140
It is that side of the well region 120 far from substrate 100 is axisymmetrically set with the center line AA ' of substrate 100；Gate insulation layer 200 is arranged
In the side of well region 120 and the separate substrate 100 of source region 130, gate insulation layer 200 is multistage to be made of multiple gate insulation sub-layers
Structure, and formed by silica；And grid 300 is arranged in side of the gate insulation layer 200 far from substrate 100, and grid 300 by
Multiple polysilicon sub-layer compositions.It should be noted that Figure 16 gate insulation only for reference for being not intended to limit the semiconductor power device
Layer 200 is two stage structures；All " multiple-rank arrangement " specifically refer to herein, are in symmetrical multi-stage stairs shape, including but not limited to
Two ranks, those skilled in the art can be designed as three ranks or more multistage according to actual needs.
Present inventor has found after study, can be layer by layer and carrying out high temperature oxidation process to polysilicon sub-layer
The multistage gate insulation layer structure for obtaining semiconductor power device, to make the surface more smooth of multistage gate insulation layer, to avoid
Gate electrode insulation surface out-of-flatness or the adverse effect for remaining corrosive agent, and then the use that the semiconductor power device can be improved can
By property.
It should be noted that the semiconductor power device other than above-mentioned each structure, further include other necessary structures or
Composition, specifically such as spacer medium layer, source electrode, drain electrode, those skilled in the art can be according to the tool of the semiconductor power device
Body requirement is supplemented and is designed.In some embodiments of the invention, with reference to Figure 17, which can be with
Further comprise: spacer medium layer 500, source electrode 700 and drain electrode 800；Wherein, spacer medium layer 500 is arranged in 300 He of grid
The side of the separate substrate 100 of gate insulation layer 300；Source electrode 700 is arranged in spacer medium layer 500, source region 130 and body contact zone
The side of 140 separate substrate 100；And the other side of substrate 100 is arranged in drain electrode 800.In this way, the semiconductor power device has
There is more perfect structure and function.
In conclusion according to an embodiment of the invention, multistage grid are exhausted the invention proposes a kind of semiconductor power device
The surface more smooth and dimensional accuracy of edge layer are higher, so as to keep the long-term reliability of the semiconductor power device more preferable.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (10)
1. a kind of method for making semiconductor power device characterized by comprising
In the side of substrate, epitaxial layer, well region, source region and body contact zone are sequentially formed, wherein the epitaxial layer is arranged described
The side of substrate, the well region are that the epitaxial layer axisymmetrically is arranged in far from the substrate with the center line of the substrate
Side, the source region and the body contact zone are separately that the trap is axisymmetrically arranged in the center line of the substrate
Side of the area far from the substrate；
The first rank gate insulation sub-layer is formed in the side far from the substrate of the epitaxial layer, well region, source region and body contact zone；
In the side of the first rank gate insulation sub-layer far from the substrate, second-order gate insulation sub-layer and the first polysilicon are formed
Sub-layer；
In the side far from the substrate of the second-order gate insulation sub-layer and the first polysilicon sub-layer, the second polysilicon is formed
Sub-layer, and photoetching is carried out to the second polysilicon sub-layer and the first polysilicon sub-layer and forms grid；
Wherein, the formation second-order gate insulation sub-layer and the step of the first polysilicon sub-layer, further comprise:
In the side of the first rank gate insulation sub-layer far from the substrate, sequentially forms the first polysilicon layer and there is patterning
Protective layer；
High temperature oxidation process is carried out to the region that do not protected by the protective layer of first polysilicon layer, to obtain second
Rank gate insulation sub-layer and the first polysilicon sub-layer；And
Remove the protective layer.
2. the method according to claim 1, wherein in the first rank gate insulation sub-layer far from the substrate
Side forms multiple second-order gate insulation sub-layers and multiple first polysilicon sub-layers.
3. the method according to claim 1, wherein the temperature of the high temperature oxidation process is taken the photograph for 800~1200
Family name's degree, and carried out under the atmosphere of purity oxygen or high pure oxygen.
4. the method according to claim 1, wherein the protective layer is selected from silicon nitride or aluminium oxide.
5. the method according to claim 1, wherein the thickness of the protective layer is not less than 150nm.
6. the method according to claim 1, wherein there is the step of patterned protective layer to wrap for the formation
It includes:
Compacted zone is formed far from the side of the substrate in first polysilicon layer；
Photoetching treatment is carried out to the compacted zone, is formed described with patterned protective layer.
7. the method according to claim 1, wherein the method for removing the protective layer is wet etching.
8. the method according to claim 1, wherein the substrate is formed by silicon carbide.
9. a kind of semiconductor power device, which is characterized in that made by method according to any one of claims 1 to 8.
10. a kind of semiconductor power device characterized by comprising
Substrate；
The side of the substrate is arranged in epitaxial layer, the epitaxial layer；
Well region, the well region are that one of the epitaxial layer far from the substrate is axisymmetrically arranged in the center line of the substrate
Side；
Source region, the source region are that one of the well region far from the substrate is axisymmetrically arranged in the center line of the substrate
Side；
Body contact zone, the body contact zone are that the well region axisymmetrically is arranged in far from the lining with the center line of the substrate
The side at bottom；
The side far from the substrate of the well region and the source region, the grid are arranged in gate insulation layer, the gate insulation layer
Insulating layer is the multiple-rank arrangement being made of multiple gate insulation sub-layers, and is formed by silica；And
Grid, side of the gate insulation layer far from the substrate is arranged in the grid, and the grid is by multiple polysilicons
Sub-layer composition.
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Effective date of registration: 20210219 Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518118 BYD Road, Pingshan New District, Shenzhen, Guangdong 3009 Patentee before: BYD Co.,Ltd. |