CN114335144A

CN114335144A - SiC MOSFET structure and manufacturing method thereof

Info

Publication number: CN114335144A
Application number: CN202111648848.1A
Authority: CN
Inventors: 李明山; 乔庆楠; 王敬; 袁松
Original assignee: Wuhu Qidi Semiconductor Co ltd
Current assignee: Wuhu Qidi Semiconductor Co ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-04-12

Abstract

The invention discloses a SiC MOSFET structure which comprises a SiC substrate layer, a SiC epitaxial layer, a P-well region, a P + region and an N + region, wherein the SiC epitaxial layer grows on the SiC substrate layer, the SiC epitaxial layer covers the SiC substrate layer, and the P-well region, the P + region and the N + region are arranged on one side, far away from the SiC substrate layer, of the SiC epitaxial layer. And a P-well area, a P + area and an N + area are arranged on two sides of the SiC epitaxial layer, the N + area is positioned in the P-well area, the top of the P + area is flush with the bottom of the N + area, and the depth of the bottom of the P + area is greater than that of the bottom of the P-well area. The structure reduces the ohmic contact resistance of the self-aligned SiC MOSFET front source contact and reduces the device loss. The invention also discloses a manufacturing method of the SiC MOSFET.

Description

SiC MOSFET structure and manufacturing method thereof

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a SiC MOSFET structure and a manufacturing method thereof.

Background

The SiC material has the advantages of wide band gap, high saturation drift velocity, high thermal conductivity, high critical breakdown electric field and the like, and is particularly suitable for preparing high-power, high-voltage and high-temperature resistant MOSFET devices. At present, international wolfsped, Infineon, Rohm, ST, etc. companies have introduced very mature MOSFET products, with voltage ranges covering 650V-1700V.

Unlike the conventional Si material, since the doped impurity ions hardly diffuse in the SiC material even under the high temperature condition of 1700 ℃, the self-aligned channel cannot be formed in the form of double diffusion as in the Si material. In the manufacturing of the SiC MOSFET, a channel is generally formed by two times of implantation, namely well implantation and source implantation, but this method is very dependent on the alignment precision of photolithography, and for the manufacturing of the MOSFET device with a channel length less than 0.6 μm, the difference between the channel lengths on both sides is easily caused by the deviation introduced by this manufacturing method, which further causes the performance degradation of the device and the reliability reduction. In order to reduce the dependency on the alignment precision of a photoetching machine in the manufacture of a SiC MOSFET, at present, three processes are used for forming a self-aligned channel of the SiC MOSFET, namely a side wall self-aligned process, a polysilicon oxidation self-aligned process and an inclined mask injection self-aligned process, although the self-aligned process can solve the problem that the lengths of the channels on two sides of a device are not equal, because source injection is generally heavy doping, and in order to inhibit the conduction of a parasitic diode in the MOSFET, impurities which are the same as a well region need to be injected into a source region, and the injection is also generally heavy doping, very high compensation doping is introduced into a source contact injection region, so that the impurity activation efficiency is low, and ohmic contact is increased.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide the SiC MOSFET structure which is simple in structure and convenient to use, and the structure reduces the ohmic contact resistance of the self-aligned SiC MOSFET front source contact and reduces the device loss; the invention also provides a manufacturing method of the SiC MOSFET.

In order to achieve the purpose, the technical scheme of the invention is as follows: a SiC MOSFET structure comprises a SiC substrate layer, a SiC epitaxial layer, a P-well area, a P + area and an N + area, wherein the SiC epitaxial layer grows on the SiC substrate layer, the SiC epitaxial layer covers the SiC substrate layer, and the P-well area, the P + area and the N + area are arranged on one side, far away from the SiC substrate layer, of the SiC epitaxial layer.

Furthermore, a P-well area, a P + area and an N + area are arranged on two sides of the SiC epitaxial layer, the N + area is located in the P-well area, the top of the P + area is flush with the bottom of the N + area, and the depth of the bottom of the P + area is larger than that of the bottom of the P-well area.

Further, L type structure that P-well district was placed for the level includes perpendicular district and transverse zone, the top in perpendicular district and the top parallel and level of SiC epitaxial layer, and N + district is arranged in the space that L type structure formed, the top in N + district with erect district top parallel and level, the length in N + district is unanimous with transverse zone length, the tip of the one end in perpendicular district is kept away from in P + district, the bottom in P + district is dark in the bottom in transverse zone, the top in P + district and the top parallel and level in transverse zone.

Further, the SiC MOSFET structure further comprises source ohmic contact metal and drain ohmic contact metal, the source ohmic contact metal is arranged above the P + region and the N + region in a Z-shaped structure, the source ohmic contact metal covers the P + region and part of the N + region, the drain ohmic contact metal is arranged at the bottom of the SiC substrate layer in a flat plate shape, and the drain ohmic contact metal covers the bottom of the SiC substrate layer.

Furthermore, a gate dielectric and a polycrystalline silicon gate are arranged at the top of the SiC epitaxial layer, the bottom of the gate dielectric is attached to the top of the SiC epitaxial layer, the top of the vertical region of the P-well region and the top of the N + region, the gate dielectric covers the SiC epitaxial layer, the vertical region of the P-well region and part of the N + region, and the polycrystalline silicon gate is positioned above the gate dielectric and covers the gate dielectric; and interlayer dielectrics ILD are arranged on the upper surface of the polycrystalline silicon grid electrode, two side walls of the polycrystalline silicon grid electrode and two side walls of the grid dielectric.

Furthermore, a metal layer I is arranged on the upper surface of the source ohmic contact metal and the upper surface of the interlayer dielectric ILD, a gate contact hole is exposed out of the metal layer I, a metal layer II is arranged on the lower surface of the drain ohmic contact metal to form a drain, and a passivation dielectric PA layer and a polyimide layer are sequentially arranged on the metal layer I from bottom to top and expose out of the source.

The invention also relates to a manufacturing method of the SiC MOSFET, based on the SiC MOSFET structure, the manufacturing method comprises the following steps:

the method comprises the following steps: cleaning the SiC epitaxial layer by adopting an RCA method, and removing natural oxides on the surface of the SiC epitaxial layer by using BOE (buffered oxide etch) or DHF (diffused HF) to obtain a clean silicon carbide epitaxial wafer;

step two: depositing a medium on the surface of the clean SiC epitaxial layer to serve as a P-well implantation mask, coating photoresist on the P-well implantation mask to protect the P-well implantation mask, exposing and etching the P-well implantation mask corresponding to the P-well implantation area, and implanting ions at high temperature to form the P-well area;

step three: forming an N + implantation mask by adopting a CVD medium deposition and etching method without removing the P-well implantation mask, and performing high-temperature implantation to form an N + region;

step four: removing the N + injection mask, forming a P + injection mask through CVD deposition again, coating photoresist on the P + injection mask to protect the P + injection mask, exposing and etching the P + injection mask corresponding to the P + injection region, performing high-temperature injection to form a P + region, etching the SiC epitaxial layer without removing the P + injection mask, and etching the surface SiC layer;

step five: removing the P + implantation mask, cleaning the wafer by using diluted HCl and RCA, and depositing a carbon film on the surface to protect the surface; then, the wafer is activated and annealed by high-temperature ion implantation at high temperature, then the carbon film on the surface of the wafer is removed, and the surface of SiC is subjected to sacrificial oxidation to form SiO₂And cleaning with BOE to remove SiO₂；

Step six: forming a gate dielectric and a polysilicon gate on the surface by a gate oxide process, and etching the redundant gate dielectric and polysilicon gate outside the gate oxide by using photoresist as a mask;

step seven: depositing an interlayer dielectric (ILD) by a CVD method, and forming a source contact hole by photoetching and etching;

step eight: depositing source ohmic contact metal on the front surface and depositing drain ohmic contact metal on the back surface, wherein the source ohmic contact metal is arranged above the P + region and the N + region in a Z-shaped structure, and the drain ohmic contact metal is arranged at the bottom of the SiC substrate layer in a flat plate shape;

step nine: and performing metal thickening treatment on the upper surface of the source ohmic contact metal, the upper surface of the interlayer dielectric ILD and the lower surface of the drain ohmic contact metal positioned on the back surface, exposing a gate contact hole on the upper surface, depositing a passivation medium on the upper surface, and etching the passivation medium in the gate and source contact region by photoetching.

Further, in the fourth step, the SiC epitaxial layer of the P + injection region is etched downward, the surface of the P + injection region is etched, the etching depth is greater than or equal to the width of the N + injection, and the depth of the P + region is greater than the depth of the N + region.

Further, the specific operation of the step five is as follows: removing the P + implantation mask on the surface, cleaning by diluted HCl and RCA, and depositing a carbon film on the surface or forming a carbon-rich layer as a high-temperature annealing protective layer by high-temperature treatment of photoresist, wherein the thickness of the film is 10nm-600 nm; annealing at 1600-1900 deg.c for 5-60 min in high temperature inert gas atmosphere; activating the injected impurities and recovering partial crystal lattice damage in the high-temperature annealing process, removing the carbon film layer on the surface, and then performing sacrificial oxidation on the surface of SiC to form SiO₂And cleaning with BOE to remove SiO₂And removing the damaged layer on the surface.

Further, the specific operations of step eight and step nine are as follows:

a. depositing source ohmic contact metal on the front surface, forming silicide contact through rapid thermal annealing, arranging a metal layer I on the upper surface of the source ohmic contact metal and the upper surface of the interlayer dielectric ILD for metal thickening deposition, and forming a grid electrode and a source electrode of the device through photoetching; b. sequentially arranging a passivation medium PA layer and a polyimide layer on the metal layer I from bottom to top, and depositing and etching a passivation medium of the metal layer I;

c. thinning the SiC substrate layer on the back side to reduce the specific on-resistance of the device; depositing drain ohmic contact metal on the back surface and forming ohmic contact through laser annealing;

d. and arranging a metal layer II on the lower surface of the drain ohmic contact metal to thicken the back metal to form the drain of the device.

The technical scheme adopted by the invention has the advantages that:

1. the SiC MOSFET device structure comprises a substrate, wherein an epitaxial layer is arranged outside the substrate, a P-well region, an N + source electrode and a P + source electrode are formed on the surface of the epitaxial layer through ion implantation, and the difference of the SiC MOSFET device structure and the conventional MOSFET is that the P + source electrode is etched downwards, an over-doped amorphous layer on the surface is removed, and the maximum effective concentration region doped by the P + source electrode is close to the contact surface so as to form lower specific contact resistance, and injected impurities are activated and etching damage is recovered through high-temperature annealing.

2. According to the invention, the excessive doping layer and the amorphous layer on the surface, which are caused by N + and P + injection, are removed by etching, and the effective doping concentration of the corresponding P + source electrode under the contact forming layer is the highest, so that the specific contact resistance is reduced, the ohmic contact resistance of the self-aligned SiC MOSFET front source electrode contact is reduced, and the device loss is reduced.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a schematic diagram of a SiC MOSFET structure of the present invention;

FIG. 2 cleans and removes the epitaxial wafer of native oxide on the surface;

FIG. 3P-well mask etch and implant;

FIG. 4-1 mask deposition and etching to form self-aligned sidewalls;

FIG. 4-2 uses polysilicon oxidation to form a self-aligned mask;

FIG. 5-1N plus implant forms a first source contact;

FIG. 5-2N plus implant to form a second source contact;

FIG. 6 is a P + implantation mask deposition etch and implantation formation;

FIG. 7 is a P + implant mask used to etch the P + source;

FIG. 8 carbon film deposition and high temperature annealing and sacrificial oxidation;

FIG. 9 high temperature gate oxide and polysilicon gate deposition and etching;

FIG. 10 interlayer dielectric ILD deposition and etching;

FIG. 11 ohmic contact metal deposition and annealing;

FIG. 12Power Metal deposition and etching to form the gate and source;

FIG. 13PA passivation and PI passivation deposition and etching;

FIG. 14 backside substrate thinning;

FIG. 15 backside ohmic metal deposition and laser annealing;

FIG. 16 backside metal deposition;

figure 17 shows a MOSFET structure with the same features.

The labels in the above figures are respectively: 1. a SiC substrate layer; 2. a SiC epitaxial layer; 3. a P-well area; 31. a vertical area; 32. a transverse zone; 4. a P + region; 5. an N + region; 6. a source ohmic contact metal; 7. a drain ohmic contact metal; 8. a gate dielectric; 9. a polysilicon gate; 10. an interlayer dielectric ILD; 11. a metal layer I; 12. a metal layer II; 13. passivating the medium PA layer; 14. a polyamide layer; 15. p-well implantation mask; 16. injecting a mask N +; 17. injecting a mask with P +; 18. a carbon film.

Detailed Description

In the present invention, it is to be understood that the term "length"; "Width"; "Up"; "Down"; "front"; "Back"; "left"; "Right"; "vertical"; "horizontal"; "Top"; "bottom" "inner"; "outer"; "clockwise"; "counterclockwise"; "axial"; "planar direction"; "circumferential" and the like indicate orientations or positional relationships that are based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the indicated device or element must have a particular orientation; constructed and operative in a particular orientation and therefore should not be construed as limiting the invention.

In the invention, an N + source electrode and a P + source electrode are an N + region and a P + region, which are also called Nplus and Pplus; polymide is polyamide also called PI passivation, the material of a passivation medium PA layer is silicon dioxide andor silicon carbide, and the material of an interlayer medium ILD is silicon dioxide or boron-phosphorus-silicon glass; BOE (buffered oxide etch) is a buffered oxide etching solution and is formed by mixing hydrofluoric acid and water or ammonium fluoride and water; dhf (diluted hf) is dilute hydrogen fluoride; CVD is chemical vapor deposition, PECVD is plasma enhanced chemical vapor deposition, LPCVD is low pressure chemical vapor deposition, APCVD is atmospheric pressure chemical vapor deposition; the RTA anneal is a rapid thermal anneal.

As shown in fig. 1 to 17, a SiC MOSFET structure includes a SiC substrate layer 1, a SiC epitaxial layer 2, a P-well region 3, a P + region 4, and an N + region 5, where the SiC epitaxial layer 2 grows on the SiC substrate layer 1, the SiC epitaxial layer 2 covers the SiC substrate layer 1, and the P-well region 3, the P + region 4, and the N + region 5 are disposed on one side of the SiC epitaxial layer 2 away from the SiC substrate layer 1. And a P-well region 3, a P + region 4 and an N + region 5 are arranged on two sides of the SiC epitaxial layer 2, the N + region 5 is positioned in the P-well region 3, the top of the P + region 4 is flush with the bottom of the N + region 5, and the depth of the bottom of the P + region 4 is greater than that of the bottom of the P-well region 3. The structure reduces the ohmic contact resistance of the self-aligned SiC MOSFET front source contact and reduces the device loss.

L type structure that P-well district 3 was placed for the level includes perpendicular district 31 and horizontal district 32, the top of perpendicular district 31 and the top parallel and level of SiC epitaxial layer 2, N + district 5 is arranged in L type structure formation's space, the top of N + district 5 with perpendicular district 31 top parallel and level, the length of N + district 5 is unanimous with horizontal district 32 length, P + district 4 is located the tip of the one end of perpendicular district 31 of horizontal district 32 keeping away from, the bottom of P + district 4 is dark in the bottom of horizontal district 32, the top of P + district 4 and the top parallel and level of horizontal district 32, P + district 4 and P-well district 3 constitute Z style of calligraphy structure, P + district 4 and N + district 5 constitute the step form. In the invention, the P-well region 3 is divided into the vertical region 31, the horizontal region 32 and the L-type structure, which is only used for convenience of describing the overall structure of the SiC MOSFET, in practice, the P-well region 3 is formed by ion implantation, other ions are implanted into the corresponding region of the P-well region 3 to form the N + region 5, other ions are implanted into the corresponding regions of the P-well region 3, the N + region 5 and the SiC epitaxial layer 2 to form the P + region 4, and finally, the corners of the L-type structure of the P-well region 3 are in circular arc transition by forming the described shape.

The SiC MOSFET structure further comprises a source ohmic contact metal 6 and a drain ohmic contact metal 7, wherein the source ohmic contact metal 6 is arranged above the P + region 4 and the N + region 5 in a Z-shaped structure, the source ohmic contact metal 6 covers the P + region 4 and part of the N + region 5, namely the source ohmic contact metal 6 completely covers the P + region 4, the source ohmic contact metal 6 covers part of the N + region 5, the drain ohmic contact metal 7 is arranged at the bottom of the SiC substrate layer 1 in a flat plate shape, and the drain ohmic contact metal 7 covers the bottom of the SiC substrate layer 1.

In the invention, the material of the source ohmic contact metal 6 and the drain ohmic contact metal 7 can be metal Ni, and can also be other metals or alloys, and is selected according to practical application.

The top of the SiC epitaxial layer 2 is provided with a gate dielectric 8 and a polysilicon gate 9, the bottom of the gate dielectric 8 is attached to the top of the SiC epitaxial layer 2, the top of the vertical region of the P-well region 3 and the top of the N + region 5, the gate dielectric 8 covers the SiC epitaxial layer 2, the vertical region 31 of the P-well region 3 and part of the N + region 5, and the polysilicon gate 9 is positioned above the gate dielectric 8 and covers the gate dielectric 8; an interlayer dielectric ILD10 is arranged on the upper surface of the polysilicon gate 9, two side walls of the polysilicon gate 9 and two side walls of the gate dielectric 8, the interlayer dielectric ILD10 is of an inverted U-shaped structure, a chamfer is arranged on the outer surface of a corner of the inverted U-shaped structure, and one side wall of one end of the source ohmic contact metal 6 is attached to the interlayer dielectric ILD 10.

And a metal layer I11 is arranged on the upper surface of the source ohmic contact metal 6 and the upper surface of the interlayer dielectric ILD10, a gate contact hole is exposed on the metal layer I11, a metal layer II 12 is arranged on the lower surface of the drain ohmic contact metal 7 to form a drain 20, a passivation dielectric PA layer 13 and a polyimide layer 14 are sequentially arranged on the metal layer I11 from bottom to top, and a source 19 is exposed.

The SiC MOSFET device structure comprises a substrate, wherein an epitaxial layer is arranged outside the substrate, a P-well region, an N + source electrode and a P + source electrode are formed on the surface of the epitaxial layer through ion implantation, and the difference of the SiC MOSFET device structure and the conventional MOSFET is that the P + source electrode is etched downwards, an over-doped amorphous layer on the surface is removed, and the maximum effective concentration region doped by the P + source electrode is close to the contact surface so as to form lower specific contact resistance, and injected impurities are activated and etching damage is recovered through high-temperature annealing.

Based on the SiC MOSFET structure, the invention also relates to a manufacturing method of the SiC MOSFET, which comprises the following steps:

step two: depositing a medium on the surface of the clean SiC epitaxial layer to serve as a P-well implantation mask 15, coating photoresist on the P-well implantation mask to protect the P-well implantation mask, exposing and etching the P-well implantation mask 15 corresponding to the P-well implantation area, and implanting ions at high temperature to form the P-well area 3;

step three: forming an N + implantation mask 16 by adopting a CVD medium deposition and etching method without removing the P-well implantation mask, and performing high-temperature implantation to form an N + region 5;

step four: removing the N + injection mask 16, forming a P + injection mask 17 through CVD deposition again, coating photoresist on the P + injection mask to protect the P + injection mask, exposing and etching the P + injection mask 17 corresponding to the P + injection region, performing high-temperature injection to form a P + region 4, and etching the SiC epitaxial layer without removing the P + injection mask 17 to etch the SiC layer on the surface layer; in the step, the SiC epitaxial layer of the P + injection region is etched downwards, the surface of the P + injection region is etched, the etching depth is larger than or equal to the width of the N + injection region, and the depth of the P + region 4 is larger than that of the N + region 5.

Step five: removing the P + implantation mask 17, firstly cleaning the wafer by adopting dilute HCl and RCA, and depositing a carbon film 18 on the surface to protect the surface; then, carrying out activation annealing of high-temperature implanted ions on the wafer at high temperature, removing the carbon film 18 on the surface of the wafer, carrying out sacrificial oxidation on the surface of the SiC to form SiO, and cleaning by BOE to remove the SiO;

the specific operation is as follows: removing the P + implantation mask 17 on the surface, cleaning by diluted HCl and RCA, depositing a carbon film on the surface or forming a carbon-rich layer as a high-temperature annealing protective layer by high-temperature treatment of photoresist, wherein the thickness of the film layer is 10nm-600 nm; annealing at 1600-1900 deg.c for 5-60 min in high temperature inert gas atmosphere; activating the injected impurities in the high-temperature annealing process and recovering partial crystal lattice damage, removing the carbon film layer on the surface, then performing sacrificial oxidation on the surface of the SiC to form SiO, and cleaning by BOE to remove the damage layer on the surface of the SiO.

Step six: forming a gate dielectric 8 and a polysilicon gate 9 on the surface by a gate oxide process, and etching the redundant gate dielectric and polysilicon gate except the gate oxide by using photoresist as a mask;

the specific operation is as follows: forming a gate dielectric and a polysilicon gate on the surface by a gate oxide process, wherein the gate dielectric is formed at the temperature of 1150-1500 ℃ in O₂Oxidizing in the atmosphere for 20-40min, and annealing in the NO atmosphere for 30-60min at the same temperature to reduce the interface state density of the gate dielectric. Depositing in-situ doped polysilicon on the surface of the gate dielectric by LPCVD with the thickness of 300-800nm, and etching away the redundant dielectric and polysilicon except the gate oxide by using photoresist as a mask.

Step seven: depositing an interlayer dielectric ILD10 by a CVD method, and forming a source contact hole by photoetching and etching;

step eight: depositing source ohmic contact metal 6 on the front surface, depositing drain ohmic contact metal 7 on the back surface, wherein the source ohmic contact metal 6 is arranged above the P + region 4 and the N + region 5 in a Z-shaped structure, the source ohmic contact metal 6 covers the P + region 4 and part of the N + region 5, namely the source ohmic contact metal 6 completely covers the P + region 4, the source ohmic contact metal 6 covers part of the N + region 5, and the drain ohmic contact metal 7 is arranged at the bottom of the SiC substrate layer 1 in a flat plate shape; the drain electrode ohmic contact metal 7 covers the bottom of the SiC substrate layer 1

Step nine: and performing metal thickening treatment on the upper surface of the source ohmic contact metal 6, the upper surface of the interlayer dielectric ILD10 and the lower surface of the drain ohmic contact metal 7 positioned on the back surface, exposing a gate contact hole on the upper surface, depositing a passivation medium on the upper surface, and etching away the passivation medium in the gate and source contact region by photoetching.

The concrete operations of the step eight and the step nine are as follows:

a. depositing a source ohmic contact metal 6 on the front surface, forming silicide contact through rapid annealing, arranging a metal layer I11 on the upper surface of the source ohmic contact metal 6 and the upper surface of an interlayer dielectric ILD10 for metal thickening deposition, and forming a grid electrode and a source electrode of the device through photoetching; b. sequentially arranging a passivation medium PA layer 13 and a polyimide layer 14 on the metal layer I11 from bottom to top, and depositing and etching a passivation medium of the metal layer I11;

c. thinning the back SiC substrate layer 1 to reduce the specific on-resistance of the device; depositing drain electrode ohmic contact metal 7 on the back surface and forming ohmic contact through laser annealing;

d. and a metal layer II 12 is arranged on the lower surface of the drain ohmic contact metal 7 to thicken the back metal to form a drain electrode of the device.

Example one

As shown in fig. 2, the silicon carbide epitaxial wafer is cleaned by the RCA method, and boe (buffered oxide etch) or dhf (diluted hf) is used to remove the native oxide on the surface of the silicon carbide, so as to obtain a clean silicon carbide epitaxial wafer.

As shown in fig. 3, on the clean SiC surface, a mask is formed by a deposition method, the mask is a P-well implantation mask 15, the type of the mask may be polysilicon formed by LPCVD deposition, silicon dioxide or silicon dioxide deposited by PECVD, USG, etc., and the P-well implantation mask is protected by coating photoresist on the P-well implantation mask, exposing and developing the P-well implantation mask 15 corresponding to the P-well implantation area, transferring the P-well mask pattern to the mask layer by photolithography and dry etching, and performing Al ion implantation to form the P-well area.

As shown in fig. 4-1, without removing the P-well mask pattern, performing deposition and etching of a CVD (chemical vapor deposition) film layer, forming self-aligned trench implantation masks, i.e. circular arc structures in the figure, on both sides of the P-well mask, wherein the deposited medium may be the same as or different from the P-well mask, and the CVD deposition method is not limited to PECVD, LPCVD or APCVD. In the step, self-aligned side wall technology is adopted for forming self-aligned channels on two sides of the P-well mask, when a CVD film layer is deposited, the film layer grows isotropically, and through the combined action of deposition and etching, the reverse etching of the CVD deposition mask forms side walls, namely the self-aligned mask, at the corner formed by the P-well implantation mask 15 and the P-well area.

As shown in fig. 5-1, implanting nitrogen or phosphorus with the self-aligned mask and P-well mask to form N + contact source region (N + region 5); the self-aligned mask and the P-well mask form the N + implant mask 16, also referred to as the P-well implant mask and its sidewalls.

As shown in fig. 6, the P-well implantation mask and its sidewall are removed, a new mask, i.e., the P + implantation mask 17, is deposited, the P + implantation pattern is etched, and Al is implanted to form a P + source contact region, i.e., the P + region 4.

As shown in fig. 7, without removing the P + implantation mask 17, SiC source etching is performed with the implantation mask as a mask for etching SiC to form a SiC trench in order to remove the over-doped amorphous layer and the impurity compensation layer on the surface; and etching the SiC of the P + injection region downwards, wherein the etching depth is more than or equal to the width of N + injection, so that a high-concentration region of the P + injection is ensured to be closer to the surface, a good ohmic contact of a source electrode is formed, the problem of low effective hole carrier concentration in a high-compensation region of the P + injection and the N + injection on a shallow surface is avoided, and a good ohmic contact of the source electrode P + and the N + is formed at the same time.

As shown in fig. 8, after removing the P + implantation mask 17 on the surface and cleaning by diluted HCl and RCA, depositing a carbon film on the surface or forming a carbon-rich layer as a high temperature annealing protection layer by high temperature treatment using photoresist, the thickness of the film layer is 10nm to 600 nm; annealing at 1600-1900 deg.c for 5-60 min in high temperature inert gas atmosphere; activating the injected impurities and recovering partial crystal lattice damage in the high-temperature annealing process, removing the carbon film layer on the surface, and then performing sacrificial oxidation on the surface of SiC to form SiO₂And cleaning with BOE to remove SiO₂And removing the damaged layer on the surface.

As shown in fig. 9, a gate dielectric and a polysilicon gate are formed on the surface by a gate oxide process, wherein the gate dielectric is formed at O by a high temperature of 1150-₂Oxidizing in the atmosphere for 20-40min, and annealing in the NO atmosphere for 30-60min at the same temperature to reduce the interface state density of the gate dielectric. Depositing in-situ doped polysilicon on the surface of the gate dielectric by LPCVD with the thickness of 300-800nm, and etching away the redundant dielectric and polysilicon except the gate oxide by using photoresist as a mask.

As shown in fig. 10, an interlayer dielectric ILD is deposited by a CVD method, and a source contact hole is formed by photolithography and etching;

as shown in fig. 11, a source ohmic contact metal 6 is deposited on the front surface, and a silicide contact is formed by RTA annealing;

as shown in fig. 12, a metal layer i 11 is disposed on the upper surface of the source ohmic contact metal 6 and the upper surface of the interlayer dielectric ILD10 for metal thickening deposition, and the gate and the source of the device are formed by photolithography and etching;

as shown in fig. 13, a passivation dielectric PA layer 13 and a polyimide layer 14 are sequentially disposed on the metal layer i 11 from bottom to top, and a passivation dielectric is deposited and etched on the metal layer i 11;

as shown in fig. 14, the back side SiC substrate layer 1 is subjected to thinning processing to reduce the specific on-resistance of the device;

as shown in fig. 15, a drain ohmic contact metal 7 is deposited on the back surface and ohmic contact is formed by laser annealing;

as shown in fig. 16, a metal layer ii 12 is provided on the lower surface of the drain ohmic contact metal 7 to thicken the back metal, thereby forming the drain of the device.

Example two

As shown in fig. 3, on the clean SiC surface, a mask is formed by deposition, namely, a P-well implantation mask 15, the type of the mask is polysilicon formed by LPCVD deposition, and photoresist is coated on the P-well implantation mask to protect the P-well implantation mask, the P-well implantation mask 15 corresponding to the P-well implantation region is exposed and developed, and the P-well mask pattern is transferred onto the mask layer by photolithography and dry etching, and Al ion implantation is performed to form the P-well region.

As shown in FIG. 4-2, without removing the P-well mask pattern, the wafer with the polysilicon mask is placed into an oxidation furnace, and high temperature oxidation is performed at 800-₂A layer forming a self-aligned N + implant mask;

as shown in fig. 5-2, nitrogen or phosphorus implantation is performed with the self-aligned N + implantation mask to form an N + contact source region, i.e., N + region 5; the self-aligned N + implant mask is the N + implant mask 16, also referred to as the P-well implant mask and its sidewalls.

As shown in fig. 9, a gate dielectric and a polysilicon gate are formed on the surface by a gate oxide process, wherein the gate dielectric is formed at O by a high temperature of 1150-₂Oxidizing in the atmosphere for 20-40min, and annealing in the NO atmosphere for 30-60min at the same temperature to reduce the interface state density of the gate dielectric. Depositing in-situ doped polysilicon on the surface of the gate dielectric by LPCVD with the thickness of 300-And m, using the photoresist as a mask to etch away the redundant medium and the polysilicon except the gate oxide.

According to the invention, the excessive doping layer and the amorphous layer on the surface, which are caused by N + and P + injection, are removed by etching, and the effective doping concentration of the corresponding P + source electrode under the contact forming layer is the highest, so that the specific contact resistance is reduced, the ohmic contact resistance of the self-aligned SiC MOSFET front source electrode contact is reduced, and the device loss is reduced.

The invention is described above with reference to the accompanying drawings, it is obvious that the specific implementation of the invention is not limited by the above-mentioned manner, and it is within the scope of the invention to adopt various insubstantial modifications of the technical solution of the invention or to apply the concept and technical solution of the invention directly to other occasions without modification.

Claims

1. A SiC MOSFET structure characterized by: the SiC substrate layer (1), the SiC epitaxial layer (2), the P-well area (3), the P + area (4) and the N + area (5) are included, the SiC epitaxial layer (2) grows on the SiC substrate layer (1), the SiC substrate layer (1) is covered by the SiC epitaxial layer (2), and the P-well area (3), the P + area (4) and the N + area (5) are arranged on one side, away from the SiC substrate layer (1), of the SiC epitaxial layer (2).

2. A SiC MOSFET structure according to claim 1, wherein: the SiC epitaxial layer is characterized in that a P-well area (3), a P + area (4) and an N + area (5) are arranged on two sides of the SiC epitaxial layer (2), the N + area (5) is located in the P-well area (3), the top of the P + area (4) is flush with the bottom of the N + area (5), and the depth of the bottom of the P + area (4) is larger than that of the bottom of the P-well area (3).

3. A SiC MOSFET structure according to claim 2, characterized in that: l type structure that P-well district (3) was placed for the level includes perpendicular district (31) and transverse zone (32), the top of perpendicular district (31) and the top parallel and level of SiC epitaxial layer (2), N + district (5) are arranged in the space that L type structure formed, the top of N + district (5) and perpendicular district (31) top parallel and level, the length of N + district (5) is unanimous with transverse zone (32) length, P + district (4) are located transverse zone (32) and keep away from the tip of the one end of perpendicular district (31), the bottom of P + district (4) is dark in the bottom of transverse zone (32), the top of P + district (4) and the top parallel and level of transverse zone (32).

4. A SiC MOSFET structure according to claim 3, wherein: the SiC MOSFET structure further comprises source ohmic contact metal (6) and drain ohmic contact metal (7), wherein the source ohmic contact metal (6) is arranged above the P + region (4) and the N + region (5) in a Z-shaped structure, the source ohmic contact metal (6) covers the P + region (4) and part of the N + region (5), the drain ohmic contact metal (7) is arranged at the bottom of the SiC substrate layer (1) in a flat plate shape, and the drain ohmic contact metal (7) covers the bottom of the SiC substrate layer (1).

5. The SiC MOSFET structure of claim 4, wherein: the top of the SiC epitaxial layer (2) is provided with a gate dielectric (8) and a polycrystalline silicon grid (9), the bottom of the gate dielectric (8) is attached to the top of the SiC epitaxial layer (2), the top of the vertical region of the P-well region (3) and the top of the N + region (5), the gate dielectric (8) covers the SiC epitaxial layer (2), the vertical region (31) of the P-well region (3) and part of the N + region (5), and the polycrystalline silicon grid (9) is positioned above the gate dielectric (8) and covers the gate dielectric (8); and an interlayer dielectric ILD (10) is arranged on the upper surface of the polysilicon gate (9), two side walls of the polysilicon gate (9) and two side walls of the gate dielectric (8).

6. The SiC MOSFET structure of claim 5, wherein: a metal layer I (11) is arranged on the upper surface of the source ohmic contact metal (6) and the upper surface of the interlayer dielectric ILD (10), a grid contact hole is exposed out of the metal layer I (11), a metal layer II (12) is arranged on the lower surface of the drain ohmic contact metal (7) to form a drain electrode (15), and a passivation dielectric PA layer (13) and a polyimide layer (14) are sequentially arranged on the metal layer I (11) from bottom to top and expose the source electrode (14).

7. A method for manufacturing a SiC MOSFET, characterized in that: a SiC MOSFET structure according to any one of claims 1 to 6, said method of fabrication comprising:

the method comprises the following steps: removing natural oxides on the surface of the SiC epitaxial layer to obtain a clean silicon carbide epitaxial wafer;

step two: depositing a medium on the surface of the clean SiC epitaxial layer to be used as a P-well injection mask (15), adopting a photoresist mask as protection, etching the P-well injection mask (15) corresponding to the P-well injection region, and injecting ions at high temperature to form the P-well region (3);

step three: forming an N + implantation mask (16) by adopting a medium deposition and etching method without removing the P-well implantation mask, and performing high-temperature implantation to form an N + region (5);

step four: removing the N + injection mask (16), forming a P + injection mask (17) through deposition again, protecting by using a photoresist mask, etching the P + injection mask (17) corresponding to the P + injection region, performing high-temperature injection to form a P + region (4), etching the SiC epitaxial layer without removing the P + injection mask (17), and etching the SiC layer on the surface layer;

step five: removing the P + implantation mask (17), cleaning the wafer, depositing a carbon film (18) on the surface of the wafer to protect the surface, performing activation annealing of high-temperature implantation ions at high temperature, removing the carbon film (18) on the surface of the wafer, performing sacrificial oxidation on the surface of SiC, and cleaning and removing the SiC by using BOE;

step six: forming a gate dielectric (8) and a polysilicon gate (9) on the surface by a gate oxide process, and etching the redundant gate dielectric and polysilicon gate except for the gate oxide by using photoresist as a mask;

step seven: depositing an interlayer dielectric ILD (10) on the surface, and forming a source contact hole by photoetching and etching;

step eight: depositing a source ohmic contact metal (6) on the front surface and depositing a drain ohmic contact metal (7) on the back surface;

step nine: and performing metal thickening treatment on the upper surface of the source ohmic contact metal (6), the upper surface of the interlayer dielectric ILD (10) and the lower surface of the drain ohmic contact metal (7) positioned on the back surface, exposing a gate contact hole on the upper surface, depositing a passivation medium on the upper surface, and etching away the passivation medium in the gate and source contact region through photoetching.

8. The SiC MOSFET manufacturing method of claim 7, wherein: and in the fourth step, the SiC epitaxial layer of the P + injection region is etched downwards, the surface of the P + injection region is etched, the etching depth is greater than or equal to the width of the N + injection region, and the depth of the P + region (4) is greater than that of the N + region (5).

9. The SiC MOSFET manufacturing method of claim 7, wherein: the concrete operation of the step five is as follows: removing the P + implantation mask (17) on the surface, cleaning by diluted HCl and RCA, depositing a carbon film on the surface or forming a carbon-rich layer as a high-temperature annealing protective layer by adopting photoresist high-temperature treatment, wherein the thickness of the film layer is 10nm-600 nm; annealing at 1600-1900 deg.c for 5-60 min in high temperature inert gas atmosphere; activating the injected impurities and recovering partial crystal lattice damage in the high-temperature annealing process, removing the carbon film layer on the surface, and then performing sacrificial oxidation on the surface of SiC to form SiO₂And cleaning with BOE to remove SiO₂And removing the damaged layer on the surface.

10. The SiC MOSFET manufacturing method of claim 7, wherein: the specific operations of the step eight and the step nine are as follows:

a. depositing source ohmic contact metal (6) on the front surface, forming silicide contact through rapid thermal annealing, arranging a metal layer I (11) on the upper surface of the source ohmic contact metal (6) and the upper surface of an interlayer dielectric ILD (10) for thickening deposition of metal, and forming a grid electrode and a source electrode of a device through photoetching;

b. sequentially arranging a passivation medium PA layer (13) and a polyimide layer (14) on the metal layer I (11) from bottom to top, and depositing and etching a passivation medium of the metal layer I (11);

c. thinning the back SiC substrate layer (1) to reduce the specific on-resistance of the device; depositing drain electrode ohmic contact metal (7) on the back surface and forming ohmic contact through laser annealing;

d. and arranging a metal layer II (12) on the lower surface of the drain ohmic contact metal (7) to thicken the back metal to form the drain of the device.