CN109216167A - 图案化方法 - Google Patents
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Abstract
本发明公开一种图案化方法，其利用存储阵列区内及周边区内具有不同的图案密度，所产生的蚀刻负载效应，而能够在各向异性蚀刻存储阵列区内的第一硬掩模层时，周边区内的第一硬掩模层不需覆盖住。
Description
技术领域
本发明涉及半导体制作工艺技术领域，特别是涉及一种图案化方法。
背景技术
集成电路(IC)元件尺寸随着技术的进步不断缩小。传统上通过光刻及蚀刻技术对集成电路特征进行图案化。然而，目前的光刻技术已达到其解析(分辨)极限。
随着半导体芯片元件的集成度增加，仅通过光刻技术可能难以形成超过光刻解析极限的超精细图案。因此，该技术领域仍需要一种改良的图案化方法，来形成超精细图案。
发明内容
本发明的主要目的在于提供一种改良的图案化方法，可以解决现有技术的不足。
本发明一实施例提供一种图案化方法。首先，提供一基底，其上设有一底层、一第一硬掩模层，设于该底层上、一第二硬掩模层，及一轴心形成层，设于该第二硬掩模层上。再进行一光刻及蚀刻制作工艺，在一存储阵列区内的该第二硬掩模层上，将该轴心形成层图案化成多个轴心图案，具有一第一间距，并将该轴心形成层从一周边区去除。再于该存储阵列区内的该多个轴心图案上及该周边区内的该第二硬掩模层上，沉积一间隙壁材料层。接着，各向异性蚀刻该间隙壁材料层，如此在该多个轴心图案的侧壁上形成多个间隙壁。再去除该多个轴心图案，在该存储阵列区内留下该多个间隙壁，具有一第二间距。再以该多个间隙壁做为一蚀刻掩模，各向异性蚀刻该存储阵列区内的该第二硬掩模层及该周边区内的该第二硬掩模层，如此于该存储阵列区内形成一图案化第二硬掩模层。然后以该图案化的第二硬掩模层做为一蚀刻硬掩模，各向异性蚀刻该存储阵列区内的该第一硬掩模层及该周边区内的该第一硬掩模层，如此于该存储阵列区内形成一图案化第一硬掩模层。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图7为本发明一实施例所绘示的一种图案化方法的示意图。
主要元件符号说明
10 基底
101 存储阵列区
102 周边区
12 底层
14 第一硬掩模层
14a 图案化的第一硬掩模层
14b 剩余的第一硬掩模层
16 第二硬掩模层
16a 图案化的第二硬掩模层
18 轴心形成层
18a 轴心图案
180 有机介电层
182 抗反射层
20 光致抗蚀剂图案
22 间隙壁材料层
22a 间隙壁
P1 第一间距
P2 第二间距
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技艺人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图7，其为依据本发明一实施例所绘示的一种图案化方法。如图1所示，首先提供一基底10，其上设有一底层12、一第一硬掩模层14，设于底层12上、一第二硬掩模层16，及一轴心形成层18，设于第二硬掩模层16上。
根据本发明一实施例，基底10可以包含一硅基底，但不限于此。根据本发明一实施例，底层12可以包含多晶硅。根据本发明一实施例，
第一硬掩模层14可以包含氮化硅，第二硬掩模层16可以包含多晶硅。根据本发明另一实施例，第一硬掩模层14可以包含碳氮化硅(SiCN)，第二硬掩模层16可以包含非晶硅。
根据本发明一实施例，轴心形成层18可以包含一有机介电层(organicdielectric layer)180及一抗反射层182，设于有机介电层180上。根据本发明一实施例，抗反射层182可以包含氮氧化硅(SiON)，但不限于此。
接着，进行一光刻制作工艺，在一存储阵列区101内形成一光致抗蚀剂图案20。光致抗蚀剂图案20具有一第一间距P1。在周边区102内，则未形成光致抗蚀剂图案20，故显露出轴心形成层18。
接着，如图2所示，以光致抗蚀剂图案20作为蚀刻掩模，进行一各向异性干蚀刻制作工艺，蚀刻未被光致抗蚀剂图案20覆盖的轴心形成层18，如此将轴心形成层18图案化成多个轴心图案18a，同样具有第一间距P1。周边区内的轴心形成层则被完全去除，显露出第二硬掩模层16。
接着，如图3所示，在存储阵列区101内的多个轴心图案18a上及周边区102内的第二硬掩模层16上，共形的沉积一间隙壁材料层22。根据本发明一实施例，间隙壁材料层22可以包含氮化硅或氧化硅，但不限于此。
如图4所示，各向异性蚀刻间隙壁材料层22，如此在多个轴心图案18a的侧壁上形成多个间隙壁22a。举例来说，所述各向异性蚀刻间隙壁材料层22的步骤可以利用含有CF4、CHF3、C4F8、C4F6等蚀刻气体。
如图5所示，随后去除多个轴心图案18a，在存储阵列区101内留下多个间隙壁22a，具有一第二间距P2。根据本发明一实施例，第二间距P2为该第一间距P1的一半。举例来说，所述去除多个轴心图案18a的步骤可以利用含有氧气等离子体的蚀刻气体，但不限于此。
如图6所示，接着以多个间隙壁22a做为一蚀刻掩模，各向异性蚀刻存储阵列区101内的第二硬掩模层16及周边区102内的第二硬掩模层16，将间隙壁22a的图案转移至下方的第二硬掩模层16，如此于存储阵列区101内形成一图案化的第二硬掩模层16a。举例来说，所述各向异性蚀刻存储阵列区101内的第二硬掩模层16及周边区102内的第二硬掩模层16的步骤，可以利用含有氧气及Cl2或HBr的蚀刻气体。
从图5至图6可看出，当各向异性蚀刻存储阵列区101内的第二硬掩模层16时，周边区102内的第二硬掩模层16并未被遮盖。
如图7所示，再以图案化的第二硬掩模层16a做为一蚀刻硬掩模，各向异性蚀刻存储阵列区101内的第一硬掩模层14及周边区102内的第一硬掩模层14，如此于存储阵列区101内形成一图案化的第一硬掩模层14a。举例来说，所述各向异性蚀刻存储阵列区101内的第一硬掩模层14及周边区102内的第一硬掩模层14的步骤，可以利用含有CxFy及CxHyFz的蚀刻气体，其中，CxFy例如C4F8或C4F6，而CxHyFz例如CH2F2或CHF3。
从图6至图7可看出，当各向异性蚀刻存储阵列区101内的第一硬掩模层14时，周边区102内的第一硬掩模层14并未被遮盖。根据本发明一实施例，形成于存储阵列区101内的图案化的第一硬掩模层14a暴露出底层12的一上表面，而周边区102则是被剩余的第一硬掩模层14b覆盖住。
最后，可以再进行另一各向异性干蚀刻制作工艺，以图案化的第一硬掩模层14a为蚀刻掩模，将图案化的第一硬掩模层14a的图案转移至存储阵列区101内的底层12中。
本发明的优点在于利用存储阵列区101内及周边区102内具有不同的图案密度，产生的蚀刻负载效应，而能够在各向异性蚀刻存储阵列区101内的第一硬掩模层14时，周边区102内的第一硬掩模层14不需另以保护层或光致抗蚀剂层覆盖住，因而可以节省一道光掩模。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。
Claims (10)
1.一种图案化方法，包含：
提供一基底，其上设有一底层、一第一硬掩模层，设于该底层上、一第二硬掩模层，及一轴心形成层，设于该第二硬掩模层上；
进行一光刻及蚀刻制作工艺，在一存储阵列区内的该第二硬掩模层上，将该轴心形成层图案化成多个轴心图案，具有一第一间距，并将该轴心形成层从一周边区去除；
在该存储阵列区内的该多个轴心图案上及该周边区内的该第二硬掩模层上，沉积一间隙壁材料层；
各向异性蚀刻该间隙壁材料层，如此在该多个轴心图案的侧壁上形成多个间隙壁；
去除该多个轴心图案，于该存储阵列区内留下该多个间隙壁，具有一第二间距；
以该多个间隙壁做为一蚀刻掩模，各向异性蚀刻该存储阵列区内的该第二硬掩模层及该周边区内的该第二硬掩模层，如此于该存储阵列区内形成一图案化第二硬掩模层；以及
以该图案化的第二硬掩模层做为一蚀刻硬掩模，各向异性蚀刻该存储阵列区内的该第一硬掩模层及该周边区内的该第一硬掩模层，如此于该存储阵列区内形成一图案化的第一硬掩模层。
2.如权利要求1所述的图案化方法，其中该底层包含多晶硅。
3.如权利要求1所述的图案化方法，其中该第一硬掩模层包含氮化硅，该第二硬掩模层包含多晶硅。
4.如权利要求1所述的图案化方法，其中该第一硬掩模层包含碳氮化硅，该第二硬掩模层包含非晶硅。
5.如权利要求1所述的图案化方法，其中该轴心形成层包含有机介电层及抗反射层，设于该有机介电层上。
6.如权利要求4所述的图案化方法，其中该抗反射层包含氮氧化硅。
7.如权利要求1所述的图案化方法，其中该第二间距为该第一间距的一半。
8.如权利要求1所述的图案化方法，其中当各向异性蚀刻该存储阵列区内的该第二硬掩模层时，该周边区内的该第二硬掩模层并未被遮盖。
9.如权利要求1所述的图案化方法，其中当各向异性蚀刻该存储阵列区内的该第一硬掩模层时，该周边区内的该第一硬掩模层并未被遮盖。
10.如权利要求1所述的图案化方法，其中形成于该存储阵列区内的该图案化的第一硬掩模层暴露出该底层的一上表面，而该周边区则是被剩余的该第一硬掩模层覆盖住。
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