CN109188812B

CN109188812B - Array substrate, testing method thereof, display panel and display device

Info

Publication number: CN109188812B
Application number: CN201811172986.5A
Authority: CN
Inventors: 孙世成; 齐琛凯; 付先龙; 王志强; 田建飞; 胡双
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2018-10-09
Filing date: 2018-10-09
Publication date: 2021-03-30
Anticipated expiration: 2038-10-09
Also published as: CN109188812A

Abstract

The invention discloses an array substrate, a test method thereof, a display panel and a display device, comprising N data input lines, N data signal input terminals respectively connected with the data input lines, a test control terminal, N test modules in one-to-one correspondence with the data input lines and a first test signal output terminal; and an Mth test module for supplying a signal loaded on the Mth data input line to the first test signal output terminal under control of a signal loaded on the test control terminal and a signal loaded on the (M + 1) th data input line. The above structure can test each data input line individually, and the test equipment is connected at the first test signal output terminal, i.e. the signal of each data input line can be tested. The electrical test of the data input line is not limited by the tested position any more, the test method is simple and quick, and the insulating layer on the array substrate does not need to be damaged.

Description

Array substrate, testing method thereof, display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to an array substrate, a test method thereof, a display panel and a display device.

Background

With continuous innovation of display technology, the manufacturing process of display panels becomes more and more fine, the line width requirements of signal lines in the display panels become more and more fine, and as the complexity of the manufacturing process increases, the manufactured display panels may have a plurality of defects, which may be caused by abnormal output of display chips, damaged lines of fan-out areas, damaged data selectors (multiplexers), damaged lines of display areas or abnormal electrostatic protection circuits. The above reasons all require the signal of the test data line as the analysis basis.

At present, there are two test methods for data signal lines of a display panel, the first is to fabricate a Dummy data signal line (Dummy Source) and connect a test terminal to test signals of the Dummy data signal line, but this design can only test signals of peripheral data signal lines, and cannot test all lines in the display panel. The second method is to use a laser probe station to remove the insulating layer on the data signal line by laser bombardment and then use a probe connected with an oscilloscope to test, but the test method is destructive test and the success rate is less than 70%. Therefore, it is an urgent problem to provide a testing scheme that has strong operability and can test all the circuits of the display panel.

Disclosure of Invention

The invention provides an array substrate, a test method thereof, a display panel and a display device, which are used for carrying out signal test on all data signal lines in the array substrate.

In a first aspect, the present invention provides an array substrate, including: a display area and a non-display area adjacent to the display area; the non-display area includes: a circuit region and a test region adjacent to the circuit region;

the circuit area includes: the test circuit comprises N data input lines, N data signal input terminals, N test control terminals and N test modules, wherein the N data signal input terminals are respectively connected with the data input lines; the test zone includes: a first test signal output terminal;

an Mth test module for providing a signal loaded on the Mth data input line to the first test signal output terminal under control of a signal loaded on the test control terminal and a signal loaded on the (M + 1) th data input line;

wherein M is more than or equal to 1 and less than or equal to N, and M and N are positive integers.

In a possible implementation manner, in the array substrate provided by the present invention, the mth test module includes: a first switching transistor and a second switching transistor;

a control electrode of the first switch transistor is connected with the test control terminal, a first electrode of the first switch transistor is connected with the Mth data input line, and a second electrode of the first switch transistor is connected with a first electrode of the second switch transistor; a control electrode of the second switch transistor is connected to the (M + 1) th data input line, and a second electrode of the second switch transistor is connected to the first test signal output terminal.

In a possible implementation manner, in the array substrate provided by the present invention, the circuit area further includes: a first output signal line; the test zone further comprises: a second test signal output terminal;

the test control terminal is connected with the second test signal output terminal through the first output signal line.

In a possible implementation manner, in the array substrate provided by the present invention, the circuit area further includes: a third switching transistor corresponding to each of the test modules one to one, and a first switching control signal terminal; a second output signal line; the test zone further comprises: a third test signal output terminal;

the first switch control signal terminal is connected with the third test signal output terminal through the second output signal line;

and a control electrode of the third switching transistor corresponding to the Mth test module is connected with the first switch control signal terminal, a first electrode of the third switching transistor corresponding to the Mth test module is connected with the Mth data input line, and a second electrode of the third switching transistor corresponding to the Mth test module is connected with the first test signal output terminal.

In a possible implementation manner, in the array substrate provided by the present invention, the circuit area further includes: a fourth switching transistor, a second switch control signal terminal, a test signal input terminal, a third output signal line, and a fourth output signal line; the test zone further comprises: a fourth test signal output terminal;

the second switch control signal terminal is connected with the fourth test signal output terminal through the third output signal line;

the control electrode of the fourth switching transistor is connected with the second switch control signal terminal, the first electrode of the fourth switching transistor is connected with the test signal input terminal, and the second electrode of the fourth switching transistor is connected with the first test signal output terminal through the fourth output signal line.

In a second aspect, the present invention provides a testing method based on any one of the above array substrates, including:

loading a first control signal to a test control terminal, loading a data signal to an Mth data signal input terminal, loading a second control signal to an M +1 th data signal input terminal, loading third control signals to the other data signal input terminals except the Mth and the M +1 th data signal input terminals, and controlling a signal of the Mth data input line to be supplied to a first test signal output terminal;

detecting a signal of the first test signal output terminal;

In a possible implementation manner, in the above testing method provided by the present invention, the array substrate further includes: a third switching transistor, the test method further comprising:

loading a first control signal to a test control terminal, loading a data signal to an Mth data signal input terminal, loading a second control signal to an M +1 th data signal input terminal, loading a third control signal to the other data signal input terminals except the Mth and the M +1 th data signal input terminals, loading a fourth control signal to a first switch control signal terminal, and controlling the third switch transistor to be closed.

In a possible implementation manner, in the above testing method provided by the present invention, the array substrate further includes: a fourth switching transistor, the method of testing further comprising:

loading a first control signal to the test control terminal, loading a data signal to the Mth data signal input terminal, loading a second control signal to the M +1 th data signal input terminal, loading a third control signal to the other data signal input terminals except the Mth data signal input terminal and the M +1 th data signal input terminal, loading a fifth control signal to the second switch control signal terminal, and controlling the fourth switch transistor to be closed.

In a third aspect, the present invention provides a display panel, including any one of the array substrates described above.

In a fourth aspect, the present invention provides a display device, including the display panel.

The invention has the following beneficial effects:

the invention provides an array substrate, a test method thereof, a display panel and a display device, comprising the following steps: a display area and a non-display area adjacent to the display area; the non-display area includes: a circuit region and a test region adjacent to the circuit region; the circuit area includes: the test system comprises N data input lines, N data signal input terminals, N test control terminals and N test modules, wherein the N data signal input terminals are respectively connected with the data input lines; the test zone includes: a first test signal output terminal; an Mth test module for supplying a signal loaded on the Mth data input line to the first test signal output terminal under control of a signal loaded on the test control terminal and a signal loaded on the (M + 1) th data input line; wherein M is more than or equal to 1 and less than or equal to N, and M and N are positive integers. The array substrate structure provided by the embodiment of the invention can be used for independently testing each data input line, and finally, the electrical test of all the data input lines is realized. The test module is connected between two adjacent data input lines, and can provide the test signal of the corresponding data input line to the first test signal output terminal under the control of the signal loaded on the test control terminal and the signal loaded on the adjacent data input line. Thus, the signal of each data input line can be tested only by connecting the test device at the first test signal output terminal. The electrical test of the data input line is not limited by the tested position any more, the test method is simple and quick, and the insulating layer on the array substrate does not need to be damaged.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of an array panel according to an embodiment of the present invention;

fig. 2 is a second schematic structural diagram of an array panel according to an embodiment of the present invention;

fig. 3 is a third schematic structural diagram of an array panel according to an embodiment of the present invention;

fig. 4 is a fourth schematic structural diagram of an array panel according to an embodiment of the present invention;

fig. 5 is a layout of a non-display area of an array substrate according to an embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view of a test module according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of signal line connections according to an embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view of a test signal output terminal according to an embodiment of the present invention;

fig. 9 is a layout of a test area of an array substrate according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a circuit connection relationship of a test area according to an embodiment of the present invention;

fig. 11 is a flowchart of a testing method of an array substrate according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The array substrate, the testing method thereof, the display panel and the display device according to embodiments of the present invention are described in detail below with reference to the accompanying drawings.

As shown in fig. 1, an array substrate provided in an embodiment of the present invention includes: a display area AA and a non-display area BB believed to be the display area AA. Further, the non-display area BB further includes: circuit region B1 and test region B2 adjacent to circuit region B1.

Wherein circuit area B1 includes: n Data input lines 10, N Data signal input terminals Data connected to the Data input lines 10, a test control terminal ST, and N test modules 20 corresponding to the Data input lines 10 one to one; test zone B2 includes: first test signal output terminal ctd.

The test modules in the array substrate provided in the embodiments of the present invention all have the same function, and for example, the mth test module is used to provide the signal loaded on the mth data input line to the first test signal output terminal ctd under the control of the signal loaded on the test control terminal ST and the signal loaded on the M +1 th data input line; wherein M is more than or equal to 1 and less than or equal to N, and M and N are positive integers.

Specifically, as shown in fig. 1, in the array substrate according to the embodiment of the invention, each data input line is connected to a data signal line 10 'of the display region through a Multiplexer (mut), so that a signal output by the driving chip (driving IC) can be transmitted to each data signal line 10' through the data input line. As long as it is detected whether the signal loaded on each data input line 10 is abnormal, a judgment basis is provided for judging whether the driver IC, the fan-out trace, and the trace in the bonding area are abnormal.

By adopting the structure of the array substrate provided by the embodiment of the invention, each data input line can be independently tested, and finally, the electrical test of all the data input lines is realized. The test module is connected between two adjacent data input lines, and can provide the test signal of the corresponding data input line to the first test signal output terminal under the control of the signal loaded on the test control terminal and the signal loaded on the adjacent data input line. Thus, the signal of each data input line can be tested only by connecting the test device at the first test signal output terminal. It should be noted that the test module corresponding to the last data input line may be connected to the last data input line and the first data input line, and provide the test signal of the last data input line to the first test signal output terminal for electrical test under the control of the signal loaded on the test control terminal and the signal loaded on the first data input line. The structure of the array substrate circuit area provided by the embodiment of the invention has no limitation on the tested position of the electrical test of the data input line, the test method is simple and quick, and the insulating layer on the array substrate does not need to be damaged. Compared with the existing electrical test, the embodiment of the invention adopts the structure of the array substrate to carry out the electrical test on the data input line, and can save more than 60% of time in the aspect of poor analysis, such as line type poor. For a product developer, the method for testing the signal of the data line in the product can evaluate and detect the product performance more quickly and better.

In specific implementation, as shown in fig. 2, the specific structures of the test modules are the same, and taking the mth test module as an example, the mth test module 20 includes: a first switching transistor T1 and a second switching transistor T2; a control electrode of the first switching transistor T1 is connected to the test control terminal ST, a first electrode of the first switching transistor T1 is connected to the mth data input line, and a second electrode of the first switching transistor T1 is connected to a first electrode of the second switching transistor T2; a control electrode of the second switching transistor T2 is connected to the M +1 th data input line, and a second electrode of the second switching transistor T2 is connected to the first test signal output terminal ctd.

Specifically, when a signal test of the data input line is performed, after a transmission signal of the M-th data input line is detected, the driving IC may output a first control signal to the test control terminal to enable the first switch transistor to be in a conducting state, and output a second control signal to the M + 1-th data input line to enable the second switch transistor to be in a conducting state, and at this time, output a normal test signal to the M-th data input line, so that a path may be formed between the M-th data input line and the first test signal output terminal, and then connect the first test signal output terminal through the oscilloscope, so that a signal of the M-th data input line may be tested. Meanwhile, the third control signal can be output to the other data input lines except the mth and the (M + 1) th data input lines, so that the second transistors in the test modules corresponding to the other data input lines are all in a closed state, and thus, the signal of the mth data input line can be tested independently without being interfered by other data input lines. The above-described test method may be repeated for each data input line in the array substrate, thereby individually testing signals of each data input line in the array substrate.

Further, as shown in fig. 2, circuit area B1 further includes: a first output signal line 11; test zone B2 also includes: a second test signal output terminal st; the test control terminal ST is connected to the second test signal output terminal ST through the first output signal line 11.

The first output signal line 11 may be connected to a control electrode of a first switching transistor in each test module 20, and the test control terminal ST is connected to the second test signal output terminal ST through the first output signal line 11, so that a signal of the second test signal output terminal ST is detected through an oscilloscope, and whether an output signal of the test control terminal ST is normal or not may be detected.

In the array substrate provided in the embodiment of the present invention, as shown in fig. 3, the circuit area B1 further includes: a third switching transistor T3, a first switching control signal terminal CTSW1, corresponding one-to-one to each of the test modules; a second output signal line 12; test zone B2 also includes: a third test signal output terminal ctsw 1; the first switch control signal terminal CTSW1 is connected to the third test signal output terminal CTSW1 through the second output signal line 12; a control electrode of the third switching transistor T3 corresponding to the mth test module is connected to the first switching control signal terminal CTSW1, a first electrode of the third switching transistor T3 corresponding to the mth test module is connected to the mth data input line, and a second electrode of the third switching transistor T3 corresponding to the mth test module is connected to the first test signal output terminal ctd.

In practical applications, the signal test on the data input line may be performed after the lighting test, and the first switch control signal terminal CTSW1 and the second output signal line 12 may be both the switch control signal terminal and the signal line set at the time of the lighting test. In the conventional test method, the first switch control signal terminal CTSW1 controls each third switch transistor to be turned on, and then data signals are sequentially applied to each data input signal terminal to test signals on each data input line. However, in this way, when the driver IC outputs an abnormal signal incorrectly, since the third switching transistors are all in the on state, the data signal input terminal corresponding to each data input line is likely to be loaded with an incorrect data signal, and all the data signals are provided to the first test signal output terminal ctd, so that the signal detected at the first test signal output terminal ctd cannot be known as the signal error on which data input line. Therefore, in the embodiment of the present invention, the test module is connected between two adjacent data input lines, and after the lighting test is finished, when the signal of each data input line is tested, the fourth control signal is applied to the first switch control signal terminal CTSW1 so that the third switch transistors corresponding to each test module are all in the off state, so that the signal applied to each data input line is controlled by the first switch transistor and the second switch transistor in the test module, and the problem of confusion of the test signal caused by the fact that the signal of each data input line is turned on by each third switch transistor and is output to the first test signal output terminal ctd is not caused.

Further, as shown in fig. 4, circuit area B1 further includes: a fourth switching transistor T4, a second switch control signal terminal CTSW2, a test signal input terminal CTD, a third output signal line 13, and a fourth output signal line 14; test zone B2 also includes: a fourth test signal output terminal ctsw 2; the second switch control signal terminal CTSW2 is connected to the fourth test signal output terminal CTSW2 through the third output signal line 13; a control electrode of the fourth switching transistor T4 is connected to the second switch control signal terminal CTSW2, a first electrode of the fourth switching transistor T4 is connected to the test signal input terminal CTD, and a second electrode of the fourth switching transistor T4 is connected to the first test signal output terminal CTD through the fourth output signal line 14.

In particular implementations, the driving IC may be caused to apply a fifth control signal to the second switch control signal terminal CTSW2 to put the fourth switch transistor in a state. The influence of the signal loaded to the test signal input terminal CTD by the driver IC on the test is avoided. When the switching transistor is in the floating state, a leakage signal that is larger than that in the off state is generated, and in order to avoid the influence of the leakage of the switching transistor on the test signal, the fifth control signal is applied to the second switch control signal terminal CTSW2 to put the fourth switching transistor in a state.

The array substrate provided by the embodiment of the invention comprises a plurality of switching transistors which can be thin film transistors, and the thin film transistors can be formed simultaneously with the thin film transistors in the driving circuit. The thin film transistor can be a P-type transistor or an N-type transistor, which is not limited herein. As shown in fig. 5, the layout of the non-display region of the array substrate may be formed in the same layer as the first output signal line 11, the second output signal line 12, the third output signal line 13, and the fourth output signal line 14, and the control electrode of each switching transistor may be formed in the same layer as each output signal line. Each data input line 10 may be formed on a metal layer located above each output signal line, and the data input line and the output signal line may be connected using a via hole when they need to be connected.

When the drive transistor in the array substrate and the switch transistor in the test module both adopt thin film transistors, the width-to-length ratio of the thin film transistor in the test module and the width-to-length ratio of the drive transistor in the drive circuit can be set to be consistent, so that the performance consistency of the thin film transistors is ensured, and the accuracy of test signals influenced by the performance difference of the transistors is avoided.

The second switching transistor T2 and the third switching transistor T3 have the structure shown in fig. 6, and may be fabricated by a low-temperature polycrystalline silicon process, in which a buffer layer 22 is formed on a substrate 21, a pattern of an active layer P is formed on the buffer layer, a gate insulating layer 23 is covered on the active layer P, a pattern of gate electrodes (G1 and G2) is formed on the gate insulating layer 23, an interlayer insulating layer 24 is formed on the gate electrode, a via hole exposing the active layer is formed on the interlayer insulating layer 24, a pattern of source and drain electrodes (S1, D1, S2, D2) is formed on the interlayer insulating layer 24, a planarization layer 25 is formed on the source and drain electrodes, and a protection layer 26 is formed on the planarization layer 25. Each thin film transistor on the array substrate can adopt a double-gate structure, so that the response speed is improved, and excessive leakage current is avoided.

As shown in fig. 7, the signal line in the Gate metal layer Gate and the source drain metal layer SD may be connected by a via, for example, in the layout shown in fig. 5, the connection between the source drain of the switching transistor and the output signal line may adopt the connection relationship shown in fig. 7, and these connection vias may be formed simultaneously when forming the via of the contact electrode of the source drain. The specific steps of the manufacturing process are similar to those described above, and further description is omitted.

The cross-sectional structure of each test signal terminal (ET Pad) in the test area is as shown in fig. 8, and the manufacturing process is basically the same as the above manufacturing process, except that the number of via holes formed between the source drain metal layer SD and the Gate metal layer Gate is larger than that of the via holes in the circuit area, so that the metal layers in the test area can be better contacted, after the flat layer 25 and the protective layer 26 are formed, the test area can be etched to expose the source drain metal layer, a pattern of the conductive layer 27 is formed on the source drain metal layer, the conductive layer can be made of transparent conductive materials such as ITO, and when an electrical test is performed, a clamp of an oscilloscope can be contacted with the conductive layer 27 to test signals of each data input line.

Since the array substrate provided in the embodiment of the present invention adds the test module in the circuit region, the signal output terminals for the test control signal and the first switch control signal need to be added in the test region accordingly, as shown in fig. 9, two signal output terminals st and ctsw2 may be added on the basis of the existing test region structure. In addition, as shown in fig. 9, the method further includes: flexible Printed Circuit (FPC) connecting terminal 1, silver thick liquid connecting terminal 2, test signal output terminal 3 (current electricity test terminal promptly), alignment mark 4, binding district connecting terminal 5, fan-out are walked line 6. The function of each connection terminal is the same as that in the prior art, and is not described in detail here.

Similarly, due to the change of the circuit area and the test area, the lighting fixture needs to be changed accordingly, and as shown in fig. 10, two additional contact probes for providing lighting test signals may be additionally disposed on the lighting fixture for the two additional signal output terminals.

In practical applications, the electrical test of the display panel may include three modes in the following table.

Firstly, before the display panel is manufactured and the drive IC is not bound, a signal source PG provides a test signal to each data signal line of the display panel for output, and the display panel is subjected to a lighting electrical test (Cell ET) to detect whether the display panel has a dead pixel or not. After the lighting test of the display panel is not abnormal, the driving IC is bound, and then a Module electrical test (Module ET) is carried out, and the driving IC provides a test signal. After the module electrical Test is not abnormal, the electrical Test (Test ET) of the data input lines provided by the embodiment of the invention can be performed to Test whether the signals of the data input lines are abnormal or not. The three electrical test modes described above are shown in the table above for the applied voltage at each signal terminal.

As shown in fig. 11, the method for testing the array substrate according to the embodiment of the present invention includes the following steps:

s10, loading a first control signal to the test control terminal, loading a data signal to the mth data signal input terminal, loading a second control signal to the M +1 th data signal input terminal, loading a third control signal to the remaining data signal input terminals except the mth and M +1 th data signal input terminals, and controlling a signal of the mth data input line to be supplied to the first test signal output terminal;

s20, detecting the signal of the first test signal output terminal;

Specifically, the test module includes a first switch transistor and a second switch transistor, the circuit connection relationship of the two switch transistors is shown in fig. 2, when an electrical test is performed on an mth data input line, a first control signal may be loaded to the test control terminal to control the first switch transistor to be in a conducting state, a second control signal is loaded to the M +1 th data signal input terminal to control the second switch transistor in the test module corresponding to the mth data input line to be in a conducting state, and third control signals are loaded to the data signal input terminals except the mth and M +1 th data input lines to make the second switch transistors in the test modules corresponding to the data input lines except the mth data input line in a closed state; at this time, when the data signal is applied to the mth data signal input terminal, the signal on this data input line may be detected at the first test signal output terminal, and the test on all the data input lines may be completed by repeating the above operations.

Further, when the array substrate provided by the embodiment of the present invention further includes a third switching transistor, and the structure is as shown in fig. 3, the testing method may further include:

when a first control signal is loaded on a test control terminal, a data signal is loaded on an Mth data signal input terminal, a second control signal is loaded on an M +1 th data signal input terminal, and a third control signal is loaded on the other data signal input terminals except the Mth data signal input terminal and the M +1 th data signal input terminal, a fourth control signal is loaded on a first switch control signal terminal, and the third switch transistor is controlled to be closed.

Specifically, when testing the signals loaded on the data input lines, the fourth control signal may be loaded on the first switch control signal terminal to control the third switch transistor to always handle the off state, so as to avoid that the signal of which data input line fails to be detected at the first test signal output terminal when the driving IC fails.

Further, the array substrate provided in the embodiment of the present invention further includes: when the fourth switching transistor is used, the structure is shown in fig. 4, and the test method may further include:

loading a first control signal to a test control terminal, loading a data signal to the Mth data signal input terminal, loading a second control signal to the M +1 th data signal input terminal, loading a third control signal to the other data signal input terminals except the Mth data signal input terminal and the M +1 th data signal input terminal, loading a fifth control signal to a second switch control signal terminal, and controlling the fourth switch transistor to be closed.

Specifically, when signals loaded on each data input line are tested, a fifth control signal can be loaded on the second switch control signal terminal to control the fourth switch transistor to be always in a closed state, so that the fourth switch transistor is prevented from being in a floating state, and the CTD signals output by the driving IC or the FPC are prevented from influencing a test structure of the data input line.

The switching transistors provided in the embodiments of the present invention may be thin film transistors or semiconductor field effect transistors, which are not limited herein. The control electrode of the transistor is a grid electrode, the first electrode is a source electrode, the second electrode is a drain electrode, and the functions of the source electrode and the drain electrode can be interchanged. When each transistor adopts an N-type transistor, the first control signal and the second control signal for controlling the transistor to be in a conducting state can be high-level signals, the third control signal for controlling the transistor to be in a closing state can be high-level signals, and the fourth control signal and the fifth control signal can be low-level signals; when the transistors are P-type transistors, the first control signal and the second control signal for controlling the transistors to be in the on state may be low level signals, the third control signal for controlling the transistors to be in the off state may be high level signals, and the fourth control signal and the fifth control signal may be high level signals.

Based on the same inventive concept, embodiments of the present invention further provide a display panel, where the display panel includes the array panel provided in embodiments of the present invention, and because the principle of solving the problem of the display panel is similar to that of the array, the implementation of the display device may refer to the implementation of the display panel, and repeated details are not repeated.

In addition, the embodiment of the present invention further provides a display device, which includes the display panel provided in the embodiment of the present invention, and the display device may be a liquid crystal panel, a liquid crystal display, a liquid crystal television, or another display device. Since the principle of the display device to solve the problem is similar to that of the display panel, the display device can be implemented by the display panel, and repeated descriptions are omitted.

The array substrate, the test method thereof, the display panel and the display device provided by the embodiment of the invention comprise the following steps: a display area and a non-display area adjacent to the display area; the non-display area includes: a circuit region and a test region adjacent to the circuit region; the circuit area includes: the test system comprises N data input lines, N data signal input terminals, N test control terminals and N test modules, wherein the N data signal input terminals are respectively connected with the data input lines; the test zone includes: a first test signal output terminal; an Mth test module for supplying a signal loaded on the Mth data input line to the first test signal output terminal under control of a signal loaded on the test control terminal and a signal loaded on the (M + 1) th data input line; wherein M is more than or equal to 1 and less than or equal to N, and M and N are positive integers. The array substrate structure provided by the embodiment of the invention can be used for independently testing each data input line, and finally, the electrical test of all the data input lines is realized. The test module is connected between two adjacent data input lines, and can provide the test signal of the corresponding data input line to the first test signal output terminal under the control of the signal loaded on the test control terminal and the signal loaded on the adjacent data input line. Thus, the signal of each data input line can be tested only by connecting the test device at the first test signal output terminal. The electrical test of the data input line is not limited by the tested position any more, the test method is simple and quick, and the insulating layer on the array substrate does not need to be damaged.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. An array substrate, comprising: a display area and a non-display area adjacent to the display area; the non-display area includes: a circuit region and a test region adjacent to the circuit region;

2. The array substrate of claim 1, wherein the mth test module comprises: a first switching transistor and a second switching transistor;

3. The array substrate of claim 1, wherein the circuit area further comprises: a first output signal line; the test zone further comprises: a second test signal output terminal;

4. The array substrate of claim 1, wherein the circuit area further comprises: a third switching transistor corresponding to each of the test modules one to one, and a first switching control signal terminal; a second output signal line; the test zone further comprises: a third test signal output terminal;

5. The array substrate of claim 1, wherein the circuit area further comprises: a fourth switching transistor, a second switch control signal terminal, a test signal input terminal, a third output signal line, and a fourth output signal line; the test zone further comprises: a fourth test signal output terminal;

6. A test method based on the array substrate as claimed in any one of claims 1 to 5, comprising:

detecting a signal of the first test signal output terminal;

7. The test method of claim 6, wherein the array substrate further comprises: a third switching transistor, the test method further comprising:

8. The test method of claim 6, wherein the array substrate further comprises: a fourth switching transistor, the method of testing further comprising:

9. A display panel comprising the array substrate according to any one of claims 1 to 5.

10. A display device characterized by comprising the display panel according to claim 9.