WO2014012306A1

WO2014012306A1 - Testing structure for transistor properties and testing method using same

Info

Publication number: WO2014012306A1
Application number: PCT/CN2012/083892
Authority: WO
Inventors: 魏振; 郭世波; 张小松; 陈庆友
Original assignee: 京东方科技集团股份有限公司; 合肥京东方光电科技有限公司
Priority date: 2012-07-20
Filing date: 2012-10-31
Publication date: 2014-01-23
Also published as: CN102788946B; CN102788946A

Abstract

Disclosed are a testing structure for transistor properties and a test method using same, which can simplify the test for the properties of a thin-film transistor. The structure comprises a connection unit used for array detection and a plurality of conductor washers for the transistor test. The plurality of conductor washers for the transistor test comprises a conductor washer for the gate of the transistor and a conductor washer for the source of the transistor. The conductor washer for the gate of the transistor and the conductor washer for the source of the transistor are respectively connected to a gate line and a data line through the connection unit.

Description

Transistor characteristic test structure and test method using the same

Embodiments of the present invention relate to a transistor characteristic test structure and a test method using the same. Background technique

At present, for the thin film transistor characteristic test in the display panel, as shown in FIG. 1, three motors of three motion axes are used to drive three contact heads (each contact head includes at least one probe) for gate lines, data lines, and pixels, respectively. The electrodes are contacted for testing.

Each time a thin film transistor characteristic of a given pixel is tested, three contacts are required to move into position, respectively. The process of testing the characteristics of the thin film transistor is complicated. Summary of the invention

Embodiments of the present invention provide a transistor characteristic test structure and test method, which make film transistor characteristic test easier.

A first aspect of the present invention provides a transistor characteristic test structure including a connection unit for array detection and a plurality of transistor test conductor pads. The plurality of transistor test conductor pads includes a transistor gate conductor pad and a transistor source conductor pad; the transistor gate conductor pad and the transistor source conductor pad are adapted to be respectively connected to the gate through the connection unit Line and data lines.

In the transistor characteristic test structure, for example, the connection unit includes a plurality of array detection conductor pads; the plurality of array detection conductor pads are adapted to be respectively connected to gate lines and data lines; A test conductor spacer is coupled to the plurality of array sense conductor pads.

In the transistor characteristic test structure, for example, the transistor gate conductor pad includes a first conductor pad and a second conductor pad; the transistor source conductor pad includes a third conductor pad and a fourth a conductor spacer; the plurality of array detection conductor pads including a plurality of array gate conductor pads and a plurality of array source conductor pads; the plurality of array gate conductor pads being adapted to be connected to a plurality of gate lines The plurality of array source conductor pads are adapted to be coupled to a plurality of data lines; the first conductor pads or/and the second conductor pads being adapted to be coupled to the plurality of array gate conductor pads Grid line A conductor spacer or/and a fourth conductor spacer are adapted to be connected to the data line by the plurality of array source conductor pads.

In the transistor characteristic test structure, for example, the plurality of array gate conductor pads are two array gate conductor pads; the two array gate conductor pads are adapted to be respectively connected to odd gate lines And an even gate line; the first conductor pad and the second conductor pad are respectively connected to the two array gate conductor pads.

In the transistor characteristic test structure, for example, the plurality of array source conductor pads are two array source conductor pads; the two array source conductor pads are respectively adapted to be connected to odd data lines And an even data line; the third conductor pad and the fourth conductor pad are respectively connected to the two array source conductor pads.

In the transistor characteristic test structure, for example, a plurality of source test signal switch tubes or a plurality of gate test signal switch tubes; and drains of the plurality of source test signal switch tubes are respectively connected to the plurality of Array source conductor pads; drains of the plurality of gate test signal switch tubes are respectively connected to the plurality of array gate conductor pads.

In the transistor characteristic test structure, for example, the first conductor pad is connected to a source of the plurality of gate test signal switch tubes; the second conductor pad is connected to the plurality of gates Testing a gate of the signal switch tube; the third conductor pad is connected to a source of the plurality of source test signal switch tubes; and the fourth conductor pad is connected to the plurality of source test signal switch tubes The gate.

In the transistor characteristic test structure, for example, a plurality of source test signal switch tubes and a plurality of gate test signal switch tubes; the first conductor pads are connected to the plurality of gate test signal switch tubes a source; the second conductor pad is connected to a gate of the plurality of gate test signal switch tubes; the third conductor pad is connected to a source of the plurality of source test signal switch tubes; The fourth conductor pad is said to be connected to the gate of the plurality of source test signal switch tubes.

For example, the test structure may further include an analog test transistor; the third conductor pad is connected to a gate of the analog test transistor; and the second conductor pad and the fourth conductor pad are respectively connected to the simulation Testing a source and a drain of the transistor; the second conductor pad is connected to a source of the plurality of gate test signal switch tubes; and the fourth conductor pad is connected to the plurality of source test signal switches a source of the tube; the first conductor pad is connected to a plurality of the source test signal switch tube and the gate of the gate test signal switch tube.

A second aspect of the present invention further provides a method for testing a transistor characteristic, which method is Any of the above transistor characteristic test structures, and contacting a plurality of probes with the plurality of transistor test conductor pads, and providing input of test signals for the gate lines and the data lines through the connection unit, and using a contact head The probe is in contact with the drain or pixel electrode of the thin film transistor in the pixel to perform transistor characteristic test.

In the method, for example, a contact head including four probes is respectively in contact with the first conductor spacer, the second conductor spacer, the third conductor spacer and the fourth conductor spacer, and the fourth The conductor pads respectively input test signals through the four probes corresponding to the contacts, and provide input of test signals for the gate lines and the data lines through the connection unit, and further use a probe of the contact head and a thin film transistor in the pixel The drain or pixel electrode contacts to achieve transistor characterization.

Among the methods, for example, when performing transistor characteristic testing in a pixel in a structure having an analog test transistor, a contact head including four probes, three of which are respectively associated with the first conductor spacer a second conductor pad, in contact with the fourth conductor pad, the first conductor pad, the second conductor pad and the fourth conductor pad inputting a test signal through the corresponding contact probe, and passing the connection The cell provides input of a test signal for the gate line and the data line, and a probe of one contact head is in contact with a drain or a pixel electrode of the thin film transistor in the pixel to perform transistor characteristic test.

In the method, for example, the analog test transistor is tested before the transistor in the test pixel is performed, and a contact head including four probes, wherein the two probes are respectively associated with the second conductor spacer, The three-conductor gasket contacts, the second conductor gasket, the third conductor gasket inputs a test signal through a probe corresponding to the contact, and the probe of the contact head is contacted with the fourth conductor gasket to implement an analog test transistor test.

The transistor characteristic test structure and method provided by the embodiments of the present invention use a plurality of probes on one contact head to contact a plurality of transistor test conductor pads during the transistor characteristic test, thereby connecting the gate lines and the data lines through the connection unit. The input of the test signal is provided, and a contact head is used to contact the drain or pixel electrode of the thin film transistor in the actual pixel to perform transistor characteristic test. Since the conductor pads and the connection unit are connected to the gate lines and the data lines through the transistors, the test signals can be supplied to all of the gate lines and the data lines at the same time, and there is no need to separately move the thin film transistor characteristics of one specified pixel each time. For a contact head, it is only necessary to move one contact head, which makes the thin film transistor characteristic test easier. DRAWINGS In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a schematic diagram of a characteristic test of a thin film transistor in the prior art;

2 is a schematic diagram of a transistor characteristic test structure according to an embodiment of the present invention;

3 is a schematic diagram of another transistor characteristic test structure in an embodiment of the present invention;

4 is a schematic diagram of another transistor characteristic test structure in an embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Unless otherwise defined, technical terms or scientific terms used herein shall be of the ordinary meaning understood by those of ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the specification and claims of the present invention do not denote any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the words "a" or "an" do not denote a quantity limitation, but rather mean that there is at least one. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship is also changed accordingly.

As shown in FIG. 2, an embodiment of the present invention provides a transistor characteristic test structure, including: a connection unit 1 for array detection and a plurality of transistor test conductor pads 2. The plurality of transistor test conductor pads 2 include a transistor gate conductor pad 2a and a transistor source conductor pad 2b.

The object to be tested is, for example, a liquid crystal display panel. As shown in FIG. 2, the array substrate of the display panel includes a plurality of laterally extending gate lines 7 parallel to each other and a plurality of longitudinally extending data lines 8 parallel to each other, respectively. A gate signal and a data signal are applied to the display panel. The gate lines 7 and the data lines 8 are perpendicular to each other and define a plurality of pixel units located in the pixel area 5 (display area). Used to display images. These pixel units constitute an array, and each of the pixel units includes, for example, a thin film transistor as a switching element and a pixel electrode.

The transistor gate conductor spacer 2a and the transistor source conductor spacer 2b are respectively connected through the connection unit

1 is connected to the gate line and the data line.

Detection of the display panel includes array detection and transistor characteristic testing. The connection unit 1 can include a separate signal connection line for the transistor gate conductor spacer 2a and the transistor source conductor spacer

2b is connected to the gate line 7 and the data line 8 through the signal connection line of the connection unit 1; the connection unit 1 and the gate line and the data line in the panel are respectively connected, so that all pixels in the panel are charged and discharged using less bus, To achieve array detection. In the transistor characteristic test, a plurality of probes on one contact head are respectively used to contact a plurality of transistor test conductor pads 2, thereby providing input of test signals for the gate lines 7 and the data lines 8 through the connection unit 1, and another one is used. The contact head is in contact with the pixel electrode in the panel to achieve transistor characteristics testing.

The transistor characteristic test structure provided in this embodiment is connected to the gate lines and the data lines through the transistor test conductor pads and the connection unit, so that the test signals can be supplied to all of the gate lines 7 and the data lines 8 at the same time, thereby eliminating the need to When testing the characteristics of a thin film transistor of a given pixel, the three contact heads are respectively moved, and only one contact head can be moved, thereby making the thin film transistor characteristic test easier.

As shown in FIG. 2, further, the connecting unit 1 may further include a plurality of array detecting conductor pads 11, 12; the array detecting conductor pads 11, 12 are respectively connected to the gate line 7 and the data line 8; The conductor spacer 2 is connected to a plurality of array detection conductor pads.

Further, the transistor gate conductor pad 2a includes a first conductor pad 21 and a second conductor pad 22; the transistor source conductor pad 2b includes a third conductor pad 23 and a fourth conductor pad 24. The plurality of array sense conductor pads includes a plurality of array gate conductor pads 11 and a plurality of array source conductor pads 12. A plurality of array gate conductor pads 11 are connected to the plurality of gate lines 7; a plurality of array source conductor pads 12 are connected to the plurality of data lines 8; the first conductor pads or/and the second conductor pads pass The plurality of array gate conductor pads are connected to the gate lines; the third conductor pads or/and the fourth conductor pads are connected to the data lines by the plurality of array source conductor pads.

Further, the plurality of array gate conductor pads 11 may be two array gate conductor pads; two array gate conductor pads 11a, l ib are respectively connected to the odd gate lines 7 and the even gate lines 7; The conductor spacer 21 and the second conductor spacer 22 are respectively connected to the two array gate conductor spacers l ib, l la . Of course, this is only a preferred example, and it can be ensured that the transistor characteristic test is performed without affecting the array detection, that is, the existing connection unit for array detection is fully utilized. The transistor gate conductor pad 2a and the array gate conductor pad 11 can be connected in a variety of combinations. For example, the first conductor pad 21 may be idle, the second conductor pad 22 is simultaneously connected to the two array gate conductor pads l ib, 11a; or, the gate line is divided into three gate line groups, and the array gate The conductor pad 11 has three array gate conductor pads respectively connected to the three gate line groups. At this time, the first conductor pad 21 simultaneously connects two of the array gate conductor pads, and the second conductor pad Sheet 22 is attached to the remaining array gate conductor pads.

Further, the plurality of array source conductor pads 12 may be two array source conductor pads; the two array source conductor pads 12a, 12b are respectively connected to the odd data lines and the even data lines; 23 and fourth conductor pads 24 are connected to the two array source conductor pads 12b, 12a, respectively.

It can be understood that the transistor gate conductor pad 2a and the array gate conductor pad 11 can be connected in various combinations, and the transistor source conductor pad 2b and the array source conductor pad 12 can also have various combinations. Connection method.

Further, the above-mentioned conductor pad may be formed using a metal layer for forming a gate line, a metal layer for forming a data line, or a transparent conductive layer (for example, indium tin oxide) for forming a pixel electrode; It can be fabricated using a metal layer for forming gate lines or data lines. Therefore, it is possible to form the conductor pads and the connecting wires at the periphery while forming the array structure in the pixel region without increasing the number of existing exposures. For example, the first conductor pad 21 and the even-numbered gate conductor pad 1 ib may be made of a transparent conductive layer (for example, indium tin oxide), and the inner pixel electrode is made of the same layer, and the spacer is at the uppermost layer, and is not covered again. An insulating layer to facilitate contact; a connection line between the second conductor pad 22 and the odd gate conductor pad 11a is obtained by forming a metal layer of the data line to avoid short circuit with the even gate line.

Specifically, in conducting the thin film transistor characteristic test, a contact head including four probes is in positional contact with the above four transistor test conductor pads. The probes on the first conductor pad 21 and the second conductor pad 22 release a large voltage (for example, generally greater than 15V) signal, and the voltage signal enters the panel through the connection unit to turn on all the thin film transistors; the third conductor pad The probes on the sheet 23 and the fourth conductor pad 24 release the data signal, and the data signal enters the inside of the panel through the connecting unit, so that all the pixels inside the panel can become the characteristics of the thin film transistor to be measured; using another contact head and any pixel Electrode contact, feedback the received signal to the device for analysis, and thus can be obtained The thin film transistor characteristics of this pixel.

The transistor characteristic test structure provided by the embodiment of the present invention can be connected to all the gate lines and the data lines at the same time because the test conductor pads and the connection unit are connected to the gate lines and the data lines through the transistors, so that it is not necessary to test one at a time. When the characteristics of the thin film transistor of a given pixel are shifted, three contact heads are respectively moved, and only one contact head needs to be moved. Thus, this embodiment makes the thin film transistor characteristic test easier; thus, it is not necessary to provide via holes for contacting the probes on the gate lines and the data lines. In addition, for smaller sized panels, the three-contact head hardware size cannot be moved in place for testing, but the transistor characterization test structure in this embodiment enables testing of smaller sized panels. Moreover, the transistor characteristic test structure in this embodiment utilizes the existing connection unit on the display panel, but does not cause interference to the original array detection.

Further, in order to correspond to other structural connection units, for example, as shown in FIG. 3, the plurality of array source conductor pads 12 are three array sources respectively connecting data lines of three different color (for example, RGB) sub-pixels. The conductor pad, the transistor characteristic test structure may further include: a plurality of source test signal switch tubes 32 and a plurality of gate test signal switch tubes 31; and drains of the plurality of source test signal switch tubes 32 are respectively connected to Array source conductor pads 12; the drains of the plurality of gate test signal switches 31 are respectively connected to the plurality of array gate conductor pads 11.

Further, the first conductor pad 21 is connected to the source of the plurality of gate test signal switch tubes 31; the second conductor pad 22 is connected to the gates of the plurality of gate test signal switch tubes 31; 23 is connected to the source of the plurality of source test signal switch tubes 32; the fourth conductor pad 24 is connected to the gates of the plurality of source test signal switch tubes 32.

It should be noted that the connection manner of the gate test signal switch tube 31 and the source test signal switch tube 32 can be used in various combinations. For example, the source test signal switch tube 32 can be used alone in FIG. 3, and the transistor gate conductor pad 2a and the array gate conductor pad 11 can be connected in the manner of FIG. For example, in FIG. 3, the gate test signal switch tube 31 can be used alone, and the transistor source conductor pad 2b and the array source conductor pad 12 can also be connected by the connection method of FIG. test.

It should be noted that the switching transistor may be a switching device such as a MOS transistor. Preferably, the switching transistor is a thin film transistor, and the manufacturing process of the thin film transistor may be the same as the manufacturing process of the thin film transistor of the pixel in the panel. For example, the trace between the gate of the plurality of gate test signal switch tubes and the conductor pads is completed at the gate layer, that is, a plurality of gate test signal switch tubes are formed to share a connection line. Similar to the gate line; other structures other than the switch tube structure are formed in the source/drain metal layer, that is, only relevant wiring is required, and other processes can be completely completed in the existing TFT-LCD fabrication process. Other structures are the same as those of the transistor characteristic test structure in the above embodiment, and are not described herein again.

Specifically, in conducting the thin film transistor characteristic test, a contact head including four probes is in positional contact with the above four transistor test conductor pads. The probes on the second conductor pad 22 and the fourth conductor pad 24 release a large voltage (for example, generally greater than 15V), and the plurality of gate test signal switch tubes 31 and the plurality of source test signal switch tubes 32 are turned on. The probe on the first conductor pad 21 releases a large voltage (for example, generally greater than 15V) signal, and the voltage signal enters the panel through the connection unit to turn on all the thin film transistors; the probe on the third conductor pad 23 The data signal is released, and the data signal enters the inside of the panel through the connecting unit, so that all the pixels inside the panel can become the characteristics of the thin film transistor to be measured; using another contact head to contact any pixel electrode, and the received signal is fed back to the device for analysis. The thin film transistor characteristics of the pixel can be obtained.

It should be noted that, for a panel of four colors (for example, RGBY), that is, each pixel unit includes four sub-pixel units, the plurality of array source conductor pads may be respectively connected to data lines on four different color sub-pixels. The four arrays of source conductor spacers, other structures and test methods are similar to the above embodiments, and will not be described herein. That is, the transistor characteristic test structure provided by the embodiment of the present invention can be used for the panels of various structures.

The transistor characteristic test structure provided by the embodiment of the invention is connected to the gate line and the data line through the transistor test conductor pad and the connection unit, so that the test signal can be provided to all the gate lines and the data line at the same time, thereby eliminating the need for each test. When a thin film transistor characteristic of a given pixel is moved, three contact heads are respectively moved, and only one contact head can be moved. Thus, this embodiment makes the thin film transistor characteristic test easier, and thus there is no need to provide via holes for contacting the probes on the gate lines and the data lines. In addition, for smaller sized panels, the size of the three contact heads cannot be moved in place for testing, but the transistor characterization test structure in this embodiment enables testing of panels of smaller dimensions. At the same time, the transistor characteristic test structure in this embodiment utilizes the existing connection unit of the display surface, but does not cause interference to the original array detection.

As shown in FIG. 4, in order to utilize the existing analog test transistor, the embodiment of the present invention further provides a transistor characteristic test structure, which has a structure similar to that of the above embodiment, but the difference is that the method further includes: the analog test transistor 4 . For example, the analog test transistor is a thin film transistor fabricated around the panel and has the same process as the internal pixel structure of the panel. The test result of the analog test transistor can be The actual condition of the inside of the panel is evaluated; the third conductor pad 23 is connected to the gate of the analog test transistor 4; the second conductor pad 22 and the fourth conductor pad 24 are respectively connected to the source and drain of the analog test transistor 4 The second conductor pad 22 is connected to the source of the plurality of gate test signal switches 31; the fourth conductor pad 24 is connected to the source of the plurality of source test signal switch tubes 32; the first conductor pad 21 The gates of the plurality of source test signal switch tubes 32 and the gate test signal switch tubes 31 are connected.

Other structures are the same as those of the transistor characteristic test structure in the above embodiment, and are not described herein again. In this embodiment, when the transistor characteristic test in the pixel is performed, since the structure of the existing analog test transistor is used, the existing contact head including four probes and the above four transistor test conductors can be directly used. The gasket is in positional contact. The probe on the first conductor pad 21 releases a large voltage (for example, generally greater than 15V), and the plurality of gate test signal switch tubes 31 and the plurality of source test signal switch tubes 32 are turned on; the second conductor spacer 22 The upper probe releases a large voltage (for example, generally greater than 15V) signal, and the voltage signal enters the panel through the connection unit to turn on all the thin film transistors; the probe on the fourth conductor pad 24 releases the data signal, and the data signal passes. The connecting unit enters the inside of the panel, so that all the pixels inside the panel can become the characteristics of the thin film transistor to be measured; using another contact head to contact any pixel electrode, and feeding the received signal to the device for analysis, the thin film transistor of the pixel can be obtained. characteristic. The third conductor spacer 23 is not used in the above process, and when the analog transistor characteristic test is performed, only the second conductor spacer 22, the third conductor spacer 23, and the fourth conductor spacer 24 are used, and the second portion is not used. A conductor spacer 21.

The transistor characteristic test structure provided by the embodiment of the invention is connected to the gate line and the data line through the transistor test conductor pad and the connection unit, so that the test signal can be provided to all the gate lines and the data line at the same time, thereby eliminating the need for each test. When a thin film transistor characteristic of a given pixel is moved, three contact heads are respectively moved, and only one contact head can be moved. Thus, this embodiment makes the thin film transistor characteristic test easier, and therefore there is no need to provide via holes for contacting the probes on the gate lines and the data lines. In addition, for smaller-sized panels, the three-contact head hardware size cannot be moved in place for testing, and the transistor characteristic test structure in this embodiment can be tested for smaller-sized panels. At the same time, the transistor characteristic test structure in this embodiment utilizes the existing connection unit and analog test transistor structure, but does not interfere with the original array detection and analog test transistor test.

The embodiment further provides a transistor characteristic test method, which uses the transistor characteristic test structure of any one of the present application, the transistor characteristic test structure comprising: a connection unit for array detection; a plurality of transistor test conductor pads; the plurality of transistor test conductor pads including a transistor gate conductor pad and a transistor source conductor pad; the transistor gate conductor pad and the transistor source conductor pad The connection units are respectively connected to the gate lines and the data lines.

A plurality of probes are in contact with the plurality of transistor test conductor pads, and an input of a test signal is provided for the gate lines and the data lines through the connection unit, and a probe of the contact head and a thin film transistor in the pixel are additionally used The drain or pixel electrode is contacted to achieve transistor characterization. The transistor test conductor spacers input test signals through the corresponding contact probes.

Further, the above test method can employ any of the transistor characteristic test structures provided by the present invention.

Further, the probes used in the above test methods can be combined with the transistor characteristics test structure provided by the present invention.

Further, in performing the thin film transistor characteristic test, a contact head including four probes is in positional contact with the four transistor test conductor pads, that is, the four probes of the contact head respectively contact the first conductor pads 21 a second conductor pad 22, a third conductor pad 23, and a fourth conductor pad 24, wherein the four conductor pads respectively input test signals through the four probes corresponding to the contacts, and pass through the connection unit The gate line and the data line provide an input of the test signal, and a probe of one contact head is used to contact the drain or the pixel electrode of the thin film transistor in the pixel to perform transistor characteristic test.

Further, when the pixel transistor characteristic test is performed in a structure having an analog test transistor, a contact head having three probes can be used in alignment with three transistor test conductor pads, that is, three probes of the contact head are respectively Contacting the first conductor pad 21, the second conductor pad 22 and the fourth conductor pad 24; it is also possible to directly use the existing contact head including four probes, but only the three probes of the contact head respectively Contacting the first conductor pad 21, the second conductor pad 22, and the fourth conductor pad 24, the third conductor pad 23 is idle without contact with the probe; the existing contact including four probes can also be directly used. The head is in positional contact with the four transistor test conductor pads, except that the probe contacting the third conductor pad 23 does not input a test signal, and the remaining transistor test conductor pads are input with a test signal through the corresponding contact probe, and pass through the The connecting unit provides an input of a test signal for the gate line and the data line, and the probe of one contact head is in contact with the drain or the pixel electrode of the thin film transistor in the pixel. Test implement pixel transistor characteristics.

Further, the analog test transistor is tested before testing the transistor in the pixel, and a contact head including four probes, wherein the two probes are respectively associated with the second conductor spacer, and the third The conductor pad contacts, the second conductor pad, the third conductor pad inputs a test signal through a probe corresponding to the contact, and the probe of the contact head is contacted with the fourth conductor pad to implement the analog test transistor test. .

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

claims

1. A transistor characteristic testing structure, including:

Connection unit for array detection;

Multiple transistor test conductor pads;

Wherein, the plurality of transistor test conductor pads include transistor gate conductor pads and transistor source conductor pads; the transistor gate conductor pads and transistor source conductor pads are respectively connected to the gate through the connection unit. lines and data lines.

2. The transistor characteristic testing structure according to claim 1, wherein,

The connection unit includes a plurality of array detection conductor pads;

The plurality of array detection conductor pads are respectively connected to gate lines and data lines;

The plurality of transistor test conductor pads are connected to the plurality of array detection conductor pads.

3. The transistor characteristic testing structure according to claim 2, wherein,

The transistor gate conductor pad includes a first conductor pad and a second conductor pad; the transistor source conductor pad includes a third conductor pad and a fourth conductor pad; the plurality of array detection conductor pads The sheet includes a plurality of array gate conductor pads and a plurality of array source conductor pads;

The plurality of array gate conductor pads are adapted to be connected to a plurality of gate lines;

The plurality of array source conductor pads are adapted to be connected to a plurality of data lines;

The first conductor pad and/or the second conductor pad are adapted to be connected to the gate line through the plurality of array gate conductor pads;

The third conductor pad and/or the fourth conductor pad are adapted to be connected to the data line through the plurality of array source conductor pads.

4. The transistor characteristic testing structure according to claim 3, wherein,

The plurality of array gate conductor pads are two array gate conductor pads;

The two array gate conductor pads are adapted to be connected to odd gate lines and even gate lines respectively; the first conductor pad and the second conductor pad are respectively connected to the two array gate conductor pads.

5. The transistor characteristic testing structure according to claim 4, wherein,

The plurality of array source conductor pads are two array source conductor pads; The two array source conductor pads are adapted to be connected to odd-numbered data lines and even-numbered data lines respectively; the third conductor pad and the fourth conductor pad are respectively connected to the two array source conductor pads.

6. The transistor characteristic testing structure according to claim 3, further comprising:

Multiple source test signal switch tubes or multiple gate test signal switch tubes;

The drains of the plurality of source test signal switch tubes are respectively connected to the plurality of array source conductor pads;

The drains of the plurality of gate test signal switch tubes are respectively connected to the plurality of array gate conductor pads;

The first conductor pad is connected to the sources of the plurality of gate test signal switch tubes; the second conductor pad is connected to the gate electrodes of the plurality of gate test signal switch tubes; the third The conductor pad is connected to the sources of the plurality of source test signal switch tubes; the fourth conductor pad is connected to the gate electrodes of the plurality of source test signal switch tubes.

7. The transistor characteristic testing structure according to claim 3, further comprising:

Multiple source test signal switch tubes and multiple gate test signal switch tubes;

8. The transistor characteristic testing structure according to claim 7, further comprising:

Analog test transistors;

The third conductor pad is connected to the gate of the analog test transistor;

The second conductor pad and the fourth conductor pad are respectively connected to the source and drain of the analog test transistor;

The second conductor pad is connected to the source electrodes of the plurality of gate test signal switch tubes; the fourth conductor pad is connected to the source electrodes of the plurality of source test signal switch tubes; The first conductor pad is connected to the gates of a plurality of the source test signal switch tubes and the gate test signal switch tubes.

9. A testing method using the transistor characteristic testing structure as claimed in claim 1, wherein a plurality of probes are brought into contact with the plurality of transistor testing conductor pads, and gate lines and The data line provides the input of the test signal, and a probe of the contact head is used to contact the drain or pixel electrode of the thin film transistor in the pixel to implement transistor characteristic testing.

10. The testing method according to claim 9, wherein a contact head including four probes is connected to the first conductor pad, the second conductor pad, the third conductor pad and the fourth conductor pad. Contact respectively, the four conductor pads input test signals respectively through the four probes of the corresponding contacts, and provide test signal input for the gate line and the data line through the connection unit, in addition, a probe with a contact head is used Contact with the drain or pixel electrode of the thin film transistor in the pixel to test the transistor characteristics.

11. The testing method according to claim 9, wherein when testing the transistor characteristics in the pixel in a structure with an analog test transistor, a contact head including four probes is used, wherein three probes are respectively connected to the The first conductor pad, the second conductor pad, and the fourth conductor pad are in contact, and the first conductor pad, the second conductor pad, and the fourth conductor pad input test signals through the corresponding contact probes. , and provide test signal input to the gate line and data line through the connection unit, and use a probe of a contact head to contact the drain or pixel electrode of the thin film transistor in the pixel to implement transistor characteristic testing.

12. The testing method according to claim 11, wherein to test the analog test transistor before testing the transistor in the pixel, a contact head including four probes, two of which are respectively connected to the first The two conductor pads and the third conductor pad are in contact. The second conductor pad and the third conductor pad input test signals through the corresponding contact probes. In addition, a contact head probe is used to connect the fourth conductor pad contact to implement analog test transistor testing.