CN101174038B - LCD device - Google Patents
LCD device Download PDFInfo
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- CN101174038B CN101174038B CN200610063422A CN200610063422A CN101174038B CN 101174038 B CN101174038 B CN 101174038B CN 200610063422 A CN200610063422 A CN 200610063422A CN 200610063422 A CN200610063422 A CN 200610063422A CN 101174038 B CN101174038 B CN 101174038B
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Abstract
The invention relates to a liquid crystal display which can eliminate a power-off remnant shade, which comprises a liquid crystal display panel, a scanning drive circuit and a data drive circuit. The liquid crystal display panel comprises a pixel array, a short circuit test circuit and a control unit. The scanning drive circuit is used to scan the liquid crystal display panel, and the data drive circuit is used to provide a grey scale voltage for the liquid crystal display panel when the liquid crystal display panel is scanned. The control unit and the short circuit test circuit are formed into a discharge circuit, when the liquid crystal display is powered off, and charge stored inside the liquid crystal display panel is released rapidly through the discharge circuit.
Description
Technical field
The present invention relates to a kind of LCD.
Background technology
Because advantages such as LCD has gently, approaches, power consumption is little, so be widely used on the modernized information equipments such as TV, notebook computer, mobile phone, personal digital assistant.Usually, in the demonstration time of a frame picture, LCD utilizes the storage capacitors store charge to keep the demonstration of picture.When this LCD shutdown, if the stored electric charge of storage capacitors can not in time discharge then the picture residual phenomena can occur.
Seeing also Fig. 1, is a kind of equivalent circuit diagram of prior art LCD.This LCD 100 comprises a display panels (not indicating), scan driving circuit 110 and a data drive circuit 120.This scan drive circuit 110 and this data drive circuit 120 are that (chip on glass, COG) technology is fitted on this display panels by glass flip chip.This scan drive circuit 110 is used for scanning this display panels, and this data drive circuit 120 is used for providing when this display panels is scanned gray scale voltage to arrive this display panels.
This display panels comprises a pel array 130 and a short-circuit test circuit 140.This short-circuit test circuit 140 is commonly used to detect this display panels when the display panels manufacture process later stage does not mount driving circuit.This pel array 130 comprises many parallel scanning beams 111, many parallel and data line 121 and a plurality of pixel cell 150 that intersect with these sweep trace 111 insulation.Each pixel cell 150 is positioned at the minimum rectangular area that this multi-strip scanning line 111 and these many data lines 121 are defined.This sweep trace 111 is connected with this scan drive circuit 110, and this data line 121 is connected with this data drive circuit 120.
This pixel cell 150 comprises a thin film transistor (TFT) 151, a storage capacitors 152 and a public electrode 153.The grid of this thin film transistor (TFT) 151 is connected with this sweep trace 111, and source electrode is connected with this data line 121, and drain electrode is connected with an end of this storage capacitors 152.The other end of this storage capacitors 152 is connected to this public electrode 153.This thin film transistor (TFT) 151 is as the gauge tap of these storage capacitors 152 chargings, discharge.
This short-circuit test circuit 140 comprises a plurality of switching thin-film transistors (switch thinfilm transistor) 141, test control line 142 and one first test lead 1401, one second test lead 1402, one the 3rd test lead 1403, one the 4th test lead 1404, one the 5th test lead 1405.Each odd line interlace line 111 is connected to the 3rd test lead 1403 via drain electrode, the source electrode of a switching thin-film transistor 141 respectively.Each even number line sweep trace 111 is connected to the 4th test lead 1404 via drain electrode, the source electrode of a switching thin-film transistor 141 respectively.Each odd column data line 121 is connected to this first test lead 1401 via source electrode, the drain electrode of a switching thin-film transistor 141 respectively.Each even column data line 121 is connected to this second test lead 1402 via source electrode, the drain electrode of a switching thin-film transistor 141 respectively.The 5th test lead 1405 is connected with the grid of these a plurality of switching thin-film transistors 141 successively via this test control line 142, and is connected to this scan drive circuit 110.The structure of above-mentioned short-circuit test circuit 140 is also referred to as the 2G2D structure.
Whether this short-circuit test circuit 140 is commonly used to detect this multi-strip scanning line 111 when the display panels manufacture process later stage does not mount driving circuit intact with these many data lines 121.When carrying out the display panels detection, above-mentioned each test lead is distinguished an external test signal separately.The 5th test lead 1405 applies a high voltage signal, makes this a plurality of switching thin-film transistor 141 conductings.The 3rd test lead 1403 and the 4th test lead 1404 apply a high voltage respectively to each odd line interlace line 111 and each even number line sweep trace 111 and the pairing thin film transistor (TFT) 151 of conducting.This first test lead 1401 and this second test lead 1402 write corresponding storage capacitors 152 via each odd column data line 121 and each even column data line 121 with gray scale voltage, thereby demonstrate test pictures on panel.By this method, whether this short-circuit test circuit 140 to can be used to detect the sweep trace 111 and the data line 121 of display panels intact.And after display panels mounts scan driving circuit 110, can apply a low-voltage during these scan drive circuit 110 work via the grid of this test control line 142 to all switching thin-film transistors 141, this short-circuit test circuit 140 was lost efficacy.
After these LCD 100 energized, this scan drive circuit 110 applies a high voltage successively to this multi-strip scanning line 111, makes a plurality of thin film transistor (TFT)s 151 conductings that are connected with this sweep trace 111.This data drive circuit 120 applies a gray scale voltage to this storage capacitors 152 via corresponding data line 121 and the thin film transistor (TFT) 151 that is in conducting state successively, and these storage capacitors 152 charging backs store certain electric charge.Before this data drive circuit 120 write gray scale voltage next time, it is constant that this storage capacitors 152 is kept above-mentioned electric charge.
When these LCD 100 deenergizations, when promptly stopping 100 power supplies of this LCD, these a plurality of storage capacitors 152 residual a large amount of electric charges can't in time discharge, thereby cause still having on the display screen afterimage, i.e. power-off ghost shadow phenomenon.
Summary of the invention
For solving the problem of the power-off ghost shadow that LCD exists in the prior art, be necessary to provide a kind of LCD of effective elimination power-off ghost shadow.
A kind of LCD, it comprises a display panels, scan driving circuit and a data drive circuit.This display panels comprises a pel array, a short-circuit test circuit and a control module.This scan drive circuit is used for scanning this display panels, and this data drive circuit is used for providing when this display panels is scanned gray scale voltage to arrive this display panels.This control module and this short-circuit test circuit constitute a discharge circuit, and during deenergization, the electric charge of this display panels internal reservoir discharges rapidly.
Compared to prior art, LCD of the present invention comprises the discharge circuit that a control module and short-circuit test circuit constitute, behind powered-down, the electric charge of this display panels internal reservoir can discharge rapidly via this discharge circuit, effectively eliminates power-off ghost shadow in this LCD.
Description of drawings
Fig. 1 is a kind of equivalent circuit diagram of prior art LCD.
Fig. 2 is the equivalent circuit diagram of LCD one better embodiment of the present invention.
Embodiment
Seeing also Fig. 2, is the equivalent circuit diagram of LCD one better embodiment of the present invention.This LCD 200 comprises a display panels (not indicating), scan driving circuit 210 and a data drive circuit 220.This scan drive circuit 210 and this data drive circuit 220 are to fit on this display panels by glass flip chip technology.This scan drive circuit 210 is used for scanning this display panels, and this data drive circuit 220 is used for providing when this display panels is scanned gray scale voltage to this display panels.
This display panels comprises a pel array 230, a short-circuit test circuit 240 and a control module 290.This short-circuit test circuit 240 constitutes a discharge circuit with this control module 290, and during these LCD 200 deenergizations, the inner stored a large amount of electric charges of this display panels discharge rapidly via this discharge circuit.
This pixel cell 270 comprises a thin film transistor (TFT) 271, a storage capacitors 272 and a public electrode 273.The grid of this thin film transistor (TFT) 271 is connected with this sweep trace 211, and source electrode is connected with this data line 221, and drain electrode is connected with an end of this storage capacitors 272.The other end of this storage capacitors 272 is connected to this public electrode 273.This thin film transistor (TFT) 271 is as the gauge tap of these storage capacitors 272 charge and discharge.
This short-circuit test circuit 240 comprises a plurality of switching thin-film transistors 241, a test control line 242 and one first test lead 2401, one second test lead 2402, one the 3rd test lead 2403, one the 4th test lead 2404, one the 5th test lead 2405.Each odd line interlace line 211 is connected to the 3rd test lead 2403 via drain electrode, the source electrode of a switching thin-film transistor 271 respectively.Each even number line sweep trace 211 is connected to the 4th test lead 2404 via drain electrode, the source electrode of a switching thin-film transistor 271 respectively.Each odd column data line 221 is connected to this first test lead 2401 via source electrode, the drain electrode of a switching thin-film transistor 271 respectively.Each even column data line 221 is connected to these second test lead, 2402, the five test leads 2405 via the source electrode of a switching thin-film transistor 271, drain electrode respectively and connects with the grid of these a plurality of switching thin-film transistors 241 successively via this test control line 242.When this display panels did not mount driving circuit, this short-circuit test circuit 240 received the external detection signal and detects this display panels from these five test leads 2401,2402,2403,2404 and 2405.After mounting driving circuit, these first test lead 2401 and these second test lead, 2402 ground connection, this test control line 242 is connected to this scan drive circuit 210.
This scan drive circuit 210 comprises a power-off protecting circuit 212, and this power-off protecting circuit 212 disconnects being connected of this scan drive circuit 210 and this test control line 242 in powered-down moment.
This control module 290 comprises an on-off circuit 250, a charge storage circuit 260, one first direct-flow input end 252 and one second direct-flow input end 254.This on-off circuit 250 comprises a P-channel metal-oxide-semiconductor field effect transistor (p-channel metal oxidesemiconductor field effect transistor, P-MO SFET) 251 and one stake resistance 256.This charge storage circuit 260 comprises one first end 262, one second end 264 and a plurality of electric capacity 261 that is parallel between this first end 262 and this second end 264.The grid of this P-MOSFET 251 is connected to this first direct-flow input end 252, and via these stake resistance 256 ground connection.The drain electrode of this P-MOSFET 251 is connected to the 3rd test lead 2403, the 4th test lead 2404 and the 5th test lead 2405.The source electrode of this P-MOSFET 251 is connected to this second direct-flow input end 254, and is connected to this first end 262.These second end, 264 ground connection.
The workflow of this LCD 200 is as follows: this LCD 200 is after energized, one 10V direct supply voltage vcc is applied to this first direct-flow input end 252, the one 10V voltage Vgh from this scan drive circuit 210 is applied to this second direct-flow input end 254, therefore grid and the voltage Vgs between the source electrode of this P-MO SFET 251 are no-voltage, the source electrode of this P-MOSFET 251 and the not conducting that drains.260 chargings of 254 pairs of these charge storage circuit of this second direct-flow input end.
This scan drive circuit 210 applies a high voltage successively to this multi-strip scanning line 211, makes a plurality of thin film transistor (TFT)s 271 conductings that are connected with this sweep trace 211.This data drive circuit 220 applies a gray scale voltage to this storage capacitors 272 via corresponding data line 221 and the thin film transistor (TFT) 271 that is in conducting state successively, and these storage capacitors 272 charging backs store certain electric charge.To keep above-mentioned electric charge constant for this storage capacitors 272 before this data drive circuit 220 writes gray scale voltage next time.
Behind these LCD 200 deenergizations, the 10V direct supply voltage V that this first direct-flow input end 252 is connected
CcThe 10V voltage V that is connected with second direct-flow input end 254
GhDisconnect.The grid of this P-MOSFET 251 is via these stake resistance 256 ground connection.Again, before this charge storage circuit 260 was recharged and kept the voltage of 10V, and the source electrode of this P-MOSFET 251 is the voltage of 10V, so the grid of this P-MOSFET 251 and the voltage V between the source electrode
GsBe the negative voltage of-10V, these P-MOSFET 251 conductings.This charge storage circuit 260 applies the P-MOSFET 251 and five test lead 2405 grid to this a plurality of switching thin-film transistors 241 of a high voltage via this conducting, makes this a plurality of switching thin-film transistor 241 conductings.This electric charge storage unit 260 applies high voltage and arrives this multi-strip scanning line 211 via the 3rd test lead 2403, the 4th test lead 2404, makes this a plurality of thin film transistor (TFT) 271 conductings.So the electric charge that is stored in each storage capacitors 272 discharges rapidly via corresponding thin film transistor (TFT) 271, data line 221, this first test lead 2401 and this second test lead, 2402 ground connection, and then effectively eliminates the power-off ghost shadow phenomenon.
Compared with prior art, LCD 200 of the present invention does not need to change the internal circuit configuration of scan drive circuit 210 and data driving circuit 220.Utilize the structure of the short-circuit test circuit 240 in display panels manufacture process later stage, effectively eliminate ghost when electric capacity, resistance and the switch that increases some again can be realized shutting down.
Claims (10)
1. LCD, it comprises a display panels, one scan drive circuit and that is used for scanning this display panels is used for providing when this display panels is scanned gray scale voltage to arrive the data drive circuit of this display panels, this display panels comprises a pel array and a short-circuit test circuit, it is characterized in that: this display panels further comprises a control module, this control module and this short-circuit test circuit constitute a discharge circuit, when this LCD deenergization, the electric charge of this display panels internal reservoir discharges rapidly by this discharge circuit.
2. LCD as claimed in claim 1 is characterized in that: this control module comprises an on-off circuit and a charge storage circuit, and this short-circuit test circuit is connected and ground connection successively with this on-off circuit, this charge storage circuit.
3. LCD as claimed in claim 2, it is characterized in that: this control module also comprises one first direct-flow input end and one second direct-flow input end, this on-off circuit comprises a P-channel metal-oxide-semiconductor field effect transistor and a stake resistance, the drain electrode of this P-channel metal-oxide-semiconductor field effect transistor is connected to this short-circuit test circuit, grid is connected to this first direct-flow input end and via this ground resistance earth, source electrode is connected to this charge storage circuit and this second direct-flow input end.
4. LCD as claimed in claim 3 is characterized in that: this charge storage circuit comprises one first end and one second end, and this first end is connected to the source electrode of this P-channel metal-oxide-semiconductor field effect transistor, this second end ground connection.
5. LCD as claimed in claim 4 is characterized in that: this charge storage circuit also comprises a plurality of electric capacity that are parallel between this first end and this second end.
6. LCD as claimed in claim 3, it is characterized in that: this short-circuit test circuit comprises a test control line, a plurality of switching thin-film transistors and one first test lead, one second test lead, one the 3rd test lead, one the 4th test lead, one the 5th test lead, this first test lead, the second test lead ground connection, the 3rd test lead, the 4th test lead, the 5th test lead is connected to the drain electrode of this P-channel metal-oxide-semiconductor field effect transistor, the 5th test lead is connected with the grid of these a plurality of switching thin-film transistors successively via this test control line, and is connected to this scan drive circuit.
7. LCD as claimed in claim 6 is characterized in that: this scan drive circuit comprises a power-off protecting circuit, and this power-off protecting circuit cuts off being connected of this scan drive circuit and this test control line when this LCD deenergization.
8. LCD as claimed in claim 6, it is characterized in that: this pel array comprises many sweep traces that are parallel to each other, many data line and a plurality of pixel cells that are parallel to each other and intersect with the insulation of this sweep trace, each pixel cell is positioned at the minimum rectangular area that this multi-strip scanning line and this many data lines are defined, each odd line interlace line is connected to the 3rd test lead, each even number line sweep trace is connected to the 4th test lead, each odd column data line is connected to this first test lead, and each even column data line is connected to this second test lead.
9. as LCD as described in the claim 8, it is characterized in that: this pixel cell comprises a thin film transistor (TFT), a storage capacitors and a public electrode, the grid of this thin film transistor (TFT) is connected with this sweep trace, source electrode is connected with this data line, drain electrode is connected with an end of this storage capacitors, and the other end of this storage capacitors is connected with this public electrode.
10. as LCD as described in the claim 9, it is characterized in that: during this LCD energized, this first direct-flow input end is connected a 10V DC voltage, this second direct-flow input end is connected a 10V DC voltage, the source electrode of this P-channel metal-oxide-semiconductor field effect transistor and the not conducting that drains, a plurality of shunt capacitances chargings that the DC voltage that this second direct-flow input end is connected is included to this charge storage circuit; During this LCD deenergization, this first direct-flow input end and this second direct-flow input end disconnect the 10V DC voltage of being connected, this charge storage circuit has high voltage, the source electrode of this P-channel metal-oxide-semiconductor field effect transistor and drain electrode conducting, this charge storage circuit is discharged and is applied a high voltage to the 3rd via this P-channel metal-oxide-semiconductor field effect transistor, the the 4th and the 5th test lead, make the thin film transistor (TFT) conducting successively that included all switching thin-film transistors of this short-circuit test circuit and each pixel cell are included, and then the storage capacitors of this a plurality of pixel cells this first test lead and this second test lead by ground connection discharges.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610063422A CN101174038B (en) | 2006-11-01 | 2006-11-01 | LCD device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610063422A CN101174038B (en) | 2006-11-01 | 2006-11-01 | LCD device |
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| Publication Number | Publication Date |
|---|---|
| CN101174038A CN101174038A (en) | 2008-05-07 |
| CN101174038B true CN101174038B (en) | 2010-05-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200610063422A Expired - Fee Related CN101174038B (en) | 2006-11-01 | 2006-11-01 | LCD device |
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| CN (1) | CN101174038B (en) |
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| US8907335B2 (en) | 2008-10-03 | 2014-12-09 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
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| CN101174038A (en) | 2008-05-07 |
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