TWI433083B - Liquid crystal display and control method thereof - Google Patents

Description

Liquid crystal display and control method thereof

The present invention relates to a method of controlling a liquid crystal display, and more particularly to a method of preventing a liquid crystal display from generating a flicker phenomenon after returning from a power saving mode.

Please refer to Figure 1. Fig. 1 is a circuit diagram showing a discharge signal generating circuit 100 of the prior art. The discharge signal generating circuit 100 is configured to discharge the pixels of the liquid crystal display when the liquid crystal display is turned off to prevent the pixels of the liquid crystal display from being damaged by the DC bias for a long time. Discharge signal generating circuit 100 includes a voltage dividing circuit 110, the CMP comparator, transistor Q ₁ and the resistor R _1. The transistor Q ₁ comprises a first end (1), a second end (2), and a control end (C). The first end of the transistor Q ₁ is coupled to the resistor R ₁ for generating a discharge signal S _XON . The second end of the transistor Q ₁ is coupled to the ground. The control terminal C of the transistor Q ₁ is coupled to the comparator CMP. One end of the resistor R ₁ is coupled to the first end of the transistor Q ₁ , and the other end of the resistor R ₁ is coupled to the voltage source V _{TCON — PW} , wherein the voltage source V _{TCON — PW is} used to provide the voltage V _{TCON — PW} as one of the liquid crystal displays Displays the power of the controller. The voltage dividing circuit 110 includes resistors R ₂ and R ₃ . The resistors R ₂ and R _{3 are} coupled between the voltage source V _{TCON — PW} and the ground. The voltage dividing circuit 110 is used to generate a voltage V _{DET_PW} which is equal to one of the voltages V _{TCON — PW} . The comparator CMP compares the voltage V _{DET_PW} with a reference voltage V _REF . When the voltage V _{DET_PW is} greater than the reference voltage V _REF , it indicates that the power supply V _{TCON_PW of the} display controller is not turned off. In this case, the comparator CMP through the transistor Q ₁ controls the control terminal of the transistor Q ₁ C nonconductive. Thus, the voltage source through resistors R _{1 V} TCON_PW voltage on a first end of the transistor Q ₁ pulled to a high potential, the transistor Q ₁ of generating a first end indicates "not discharged" the discharge signal S _XON. When the voltage V _{DET_PW is} less than the reference voltage V _REF , it means that the power supply V _{TCON_PW} of the display controller of the liquid crystal display is turned off. Since the liquid crystal display is turned off when the power supply V _{TCON_PW} of the display controller of the liquid crystal display is turned off, the comparator CMP controls the transistor Q _{1 to be} turned on through the control terminal C of the transistor Q ₁ at this time. Thus, the ground terminal generates a discharge signal S _XON indicating "discharge" at the first end of the transistor Q ₁ by pulling the voltage on the first terminal of the transistor Q ₁ to a low potential. When the gate driving circuit of the liquid crystal display receives the discharge signal S _XON indicating "discharge", the gate driving circuit simultaneously enables all the gate lines of the liquid crystal display to discharge the pixels of the liquid crystal display. In this way, the pixels of the liquid crystal display can be prevented from being damaged by DC bias for a long time.

However, when the display controller of the liquid crystal display communicates with an external graphic processing unit (GPU) through the display port interface, the external drawing processing unit can directly control the display through the display interface. The device issues a command to control the liquid crystal display to enter the power saving mode, and maintains the power of the display controller (V _{TCON_PW} ) when the liquid crystal display enters the power saving mode. Therefore, the discharge signal generating circuit 100 of the prior art does not generate the discharge signal S _XON at this time. In other words, when the external graphics processing unit controls the liquid crystal display to enter the power saving mode through the display interface, the gate driving circuit does not discharge the pixels of the liquid crystal display. Thus, when the liquid crystal display is in the power saving mode, the pixels in the liquid crystal display may be damaged by DC stress for a long time, and cause a flicker phenomenon when the liquid crystal display returns from the power saving mode.

The present invention provides a method of controlling a liquid crystal display. The method includes, when a backlight module of a liquid crystal display is turned off, accumulating a count value, comparing the count value with a predetermined shutdown time to generate a comparison result, and based on the comparison result, the plurality of liquid crystal displays The pixels are discharged. In this way, it is possible to prevent the liquid crystal display from flickering after returning from the power saving mode, and to prevent the plurality of pixels from being damaged by the DC bias.

The invention further provides a liquid crystal display. The liquid crystal display comprises a display panel, a backlight module, a display controller, and a discharge signal generating circuit. The display panel includes a gate driving circuit, a plurality of gate lines, a plurality of data lines, and a plurality of pixels. When the gate driving circuit enables one of the plurality of gate lines, the pixels coupled to the gate line of the plurality of pixels receive the data through the corresponding data lines. The backlight module is used to provide backlight to the display panel. The display controller is configured to accumulate a count value when the backlight module is turned off, and compare the count value with a predetermined shutdown time to generate a control signal. The discharge signal generating circuit is configured to receive a first voltage according to the control signal and the display controller to generate a discharge signal. When the gate driving circuit receives the discharge signal indicating discharge, the gate driving circuit simultaneously drives the plurality of gate lines to discharge the plurality of pixels. In this way, it is possible to prevent the liquid crystal display from flickering after returning from the power saving mode, and to prevent the plurality of pixels from being damaged by the DC bias.

Please refer to Figure 2. Fig. 2 is a schematic view showing a liquid crystal display 200 of the present invention. The liquid crystal display 200 includes a display panel 210, a backlight module 220, a display controller 230, and a discharge signal generating circuit 240. The display panel 210 includes a gate driving circuit 211, a data drive circuit 212, the gate lines G ₁ ~ G _N, the data lines D ₁ ~ D _M and a plurality of pixels. The structure of the plurality of pixels can be exemplified by the pixel PIX ₁ . The pixel PIX ₁ includes a transistor Q, a liquid crystal capacitor C _{LS ,} and a storage capacitor C _ST . The transistor Q includes a first end (1), a second end (2), and a control end (C). The first end of the transistor Q is coupled to the data line D ₁ , the second end of the transistor Q is coupled to the liquid crystal capacitor C _LS and the storage capacitor C _ST , and the control terminal of the transistor Q is coupled to the gate line G ₁ . The liquid crystal capacitor C _LS is coupled in parallel with the storage capacitor C _ST between the second end of the transistor Q and the ground. When the gate driving circuit 211 enabling the gate lines G _1, the transistor Q is turned on, the data driving circuit 212 may write data to the pixels PIX ₁ of the storage _capacitor C _ST via the data line D and the transistor Q. Therefore, it can be seen from the above description that when the gate driving circuit 211 enables one of the gate lines G ₁ G G _N in the gate line, the pixels coupled to the gate line of the plurality of pixels can pass through the corresponding data lines. D ₁ ~ D _M receive data. The backlight module 220 is used to provide backlight to the display panel 210. Display controller 230 is used to communicate with an external graphics processing unit 201. The graphics processing unit 201 can send commands to the display controller 230 to control the liquid crystal display 200 to enter a power saving mode. For example, the graphics processing unit 201 communicates with the display controller 230 through the display interface. When the drawing processing unit 201 sends a command through the display interface to control the liquid crystal display 200 to enter the power saving mode, the drawing processing unit 201 simultaneously controls the backlight module 220 to be turned off. Therefore, when the backlight module 220 is turned off, the display controller 230 can be turned off. A count value is accumulated, and the count value is compared with a predetermined shutdown time. When the count value is greater than the predetermined shutdown time, it indicates that the liquid crystal display 200 enters the power saving mode. At this time, the display controller 230 generates a control signal S _C indicating a logic "1" to control the discharge signal generating circuit 240 to generate a discharge signal S _XON indicating "discharge". Thus, the gate driving circuit 211 in accordance with the time represented by "discharging" the discharge signal S _XON, while enabling the gate lines G ₁ ~ G _N, in order to discharge the plurality of pixel 200 of a liquid crystal display. The structure and operation of the display controller 230 and the discharge signal generating circuit 240 will be further explained below.

Please refer to Figure 3. FIG. 3 is a schematic diagram illustrating the display controller 230 and the discharge signal generating circuit 240. In FIG. 3, it is assumed that the backlight module 220 is a Light-Emitting Diode (LED) backlight module. The backlight module 220 comprises a plurality of light-emitting diodes, the backlight and the backlight module 220 receives a supply voltage V _LED, the backlight module 220 to drive the plurality of light emitting diodes. When the backlight module 220 is turned off, the display controller 230 accumulates the count value N _C and compares the count value N _C with the predetermined shutdown time N _OFF to generate the control signal S _C . The display controller 230 includes a detection circuit 231, counter 232, the comparator CMP _1, and a delay circuit 233. The detecting circuit 231 generates an enable signal S _EN according to the backlight power supply voltage V _DET and a threshold voltage V _TH . The detection circuit 231 includes a voltage dividing circuit 2311 and a comparator CMP ₂ . The voltage dividing circuit 2311 includes resistors R ₄ and R ₅ . One end of the resistor R ₄ receives the backlight power supply voltage V _LED , and the other end of the resistor R ₄ is coupled to the resistor R ₅ . One end of the resistor R ₅ is coupled to the resistor R ₄ , and the other end of the resistor R ₅ is coupled to the ground end. Thus, the voltage dividing circuit 2311 can generate the detection voltage V _DET1 which is equal to the backlight power supply voltage V _LED . The comparator CMP _{2 is} used to compare the detection voltage V _DET1 with a threshold voltage V _TH . When the detection voltage V _DET1 is greater than the threshold voltage V _TH, denotes a backlight module 220 is not closed. At this time, the comparator CMP ₂ generates an enable signal S _EN indicating "not enabled". When the detection voltage V _{DET1 is} less than the threshold voltage V _TH , it indicates that the backlight module 220 is turned off. At this time, the comparator CMP ₂ generates an enable signal S _EN indicating "enable". Counter 232 receives the enable signal S _EN . When the enable signal S _EN indicates "enable", the counter 232 accumulates and outputs a count value N _C . For example, the counter 232 can accumulate the count value N _C according to the clock signal S _CLK received by the display controller 230. Whenever the counter 232 receives a clock signal S _CLK , the counter 232 increments the count value N _C by one. The comparator CMP _{1 is} used to compare the count value N _C with a predetermined shutdown time N _OFF . When the count value N _{C is} less than the predetermined shutdown time N _OFF , the comparator CMP ₁ generates a control signal S _C indicating a logic "0". When the count value N _C is accumulated over a predetermined shutdown time N _OFF, line 200 represents a liquid crystal display device is not shut down, but the power saving mode. At this time, the comparator CMP ₁ generates a control signal S _C indicating a logic "1". The delay circuit 233 is configured to generate a reset signal S _RST after a delay time after receiving the control signal S _C indicating the predetermined logic "1". The counter 232 resets the count value N _C according to the reset signal S _RST . Thus, when the backlight module 220 is turned off next time, the counter 232 can reaccumulate the count value N _C .

The discharge signal generating circuit 240 is configured to generate a discharge signal S _XON according to the control signal S _C and a voltage V _{TCON_PW} received by the display controller 230 (where V _{TCON_PW} is the power source of the display controller 230). Discharge signal generating circuit 240 comprises a voltage dividing circuit 241, the comparator CMP _3, resistors R _1, transistor Q _1, and the OR gate 242. The transistor Q ₁ comprises a first end (1), a second end (2), and a control end (C). The first end of the transistor Q ₁ is coupled to the resistor R ₁ for generating a discharge signal S _XON . The second end of the transistor Q ₁ is coupled to the ground. The control terminal C of the transistor Q ₁ is coupled to the OR gate 242. One end of the resistor R ₁ is coupled to the first end of the transistor Q ₁ , and the other end of the resistor R ₁ is coupled to the voltage source V _{TCON — PW} . The voltage dividing circuit 241 includes resistors R ₂ and R ₃ . The resistors R ₂ and R _{3 are} coupled between the voltage source V _{TCON — PW} and the ground. The voltage dividing circuit 241 is used to generate a voltage V _{DET_PW} which is equal to one of the voltages V _{TCON — PW} . The comparator CMP ₃ compares the voltage V _{DET_PW} with a reference voltage V _REF . When the voltage V _{DET_PW is} greater than the reference voltage V _REF , it indicates that the power supply V _{TCON — PW of the} display controller 230 is not turned off. At this time, the comparator CMP ₃ generates a comparison signal S _CMP indicating a logic "0". When the voltage V _{DET_PW is} less than the reference voltage V _REF , it indicates that the power supply V _{TCON — PW of the} display controller 230 is turned off. At this time, the comparator CMP ₃ generates a comparison signal S _CMP indicating a logic "1". The OR gate 242 includes inputs I ₁ and I ₂ and an output terminal O. The input terminal I _{1 is} used to receive the control signal S _C , the input terminal I _{2 is} used to receive the comparison signal S _CMP , and the output terminal O is coupled to the control terminal of the transistor Q ₁ . When the comparison signal S _CMP and the control signal S _{C both} indicate logic "0", it indicates that the power supply V _{TCON_PW of the} display controller 230 and the backlight module are not turned off. In other words, the liquid crystal display 200 is not turned off and does not enter the power saving mode. At this time, OR gate 242 to close the control transistor Q through the control terminal C of the transistor ₁ Q _1. Thus, the voltage source V _{TCON_PW} pulls the voltage on the first terminal of the transistor Q ₁ to a high potential through the resistor R ₁ , and causes the discharge signal S _{XON to} indicate "no discharge". When the comparison signal S _CMP indicates a logic "1", it indicates that the power supply V _{TCON_PW of the} display controller 230 is turned off. In other words, the liquid crystal display 200 may be turned off or enter a power saving mode. At this time, OR gate 242 controls the transistor Q ₁ is turned on through a control terminal of the transistor Q ₁ of C. Thus, the terminal resistors R ₁ through the first terminal of the voltage on the transistor Q ₁ is pulled to low level, the discharge signal S _XON indicates "discharge." When the control signal S _C indicates a logic "1", it indicates that the backlight module 220 is turned off for more than the predetermined shutdown time N _OFF , and the power supply V _{TCON_PW of the} display controller 230 is not turned off. In other words, the liquid crystal display 200 enters the power saving mode. For example, the graphics processing unit 201 sends a command through the display interface to control the liquid crystal display 200 to enter the power saving mode. Thus, this case OR gate 242 controls transistor Q ₁ is turned on through a control terminal of the transistor Q ₁ of C. Thus, the terminal resistors R ₁ through the first terminal of the voltage on the transistor Q ₁ is pulled to low level, the discharge signal S _XON indicates "discharge." When the gate driving circuit 211 receives a discharge signal S _XON "discharge", the gate drive circuit 211 simultaneously enabling a liquid crystal gate line display 200 of G ₁ ~ G _N, in order to discharge the pixels of the liquid crystal display 200.. In this way, the pixels of the liquid crystal display 200 can be prevented from being damaged by the DC bias for a long time, and the flicker phenomenon can be avoided after the liquid crystal display 200 recovers from the power saving mode.

In summary, in the liquid crystal display 200, when the backlight module 220 is turned off, the display controller 230 accumulates the count value N _C , and the display controller 230 compares the count value N _C with the predetermined shutdown time N _OFF to generate A comparison of the results. The discharge signal generating circuit 240 generates a discharge signal S _XON based on the comparison result to discharge a plurality of pixels of the liquid crystal display 200. More specifically, when the comparison result indicates that the count value N _{C is} greater than the predetermined shutdown time N _OFF , it indicates that the liquid crystal display 200 is not turned off, but enters the power saving mode. Therefore, the display controller 230 generates a control signal S _C indicating a logic "1". The delay circuit 233 generates a reset signal S _RST to reset the count value N _C after a delay time elapses based on the control signal S _C indicating the logic "1". Discharge signal generating circuit 240 and the OR gate 242 controls the transistor Q ₁ turns on according to represent a logic "1" of the control signal S _C. Thus, the end of the pull-through voltage on a first end of transistor Q ₁ the transistor Q ₁ to the low potential, so that a first end of transistor Q ₁ represents a discharge signal generating S _XON "discharge" of. In other words, at this time, the discharge signal generating circuit 240 controls the gate driving circuit 211 to simultaneously enable the gate lines G ₁ -G _N coupled to the plurality of pixels in the liquid crystal display 200 to discharge the pixels in the liquid crystal display 200. . In this way, the flicker phenomenon of the liquid crystal display 200 of the present invention after recovery from the power saving mode can be avoided, and the pixels in the liquid crystal display 200 of the present invention are prevented from being damaged by the DC bias for a long time.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1, 2, C. . . End point

110, 2311, 241. . . Voltage dividing circuit

200. . . LCD Monitor

201. . . Drawing processing unit

210. . . Display panel

211. . . Gate drive circuit

212. . . Data drive circuit

220. . . Backlight module

230. . . Display controller

232. . . counter

233. . . Delay circuit

240, 100. . . Discharge signal generating circuit

242. . . Gate

C _LC . . . Liquid crystal capacitor

C _ST . . . Storage capacitor

CMP, CMP ₁ ~ CMP ₃ . . . Comparators

D ₁ ~D _M . . . Data line

G ₁ ~G _N . . . Gate line

I ₁ , I ₂ . . . Input

N _C . . . Count value

N _OFF . . . Scheduled shutdown time

O. . . Output

PIX ₁ . . . Pixel

Q, Q ₁ . . . Transistor

R ₁ ~ R ₅ . . . resistance

S _C . . . control signal

S _CLK . . . Clock signal

S _CMP . . . Comparison signal

S _RST . . . Reset signal

S _XON . . . Discharge signal

V _DET1 . . . Detection voltage

V _{DET_PW} . . . Voltage

V _REF . . . Reference voltage

V _{TCON_PW} . . . power source

V _TH . . . Threshold voltage

Fig. 1 is a circuit diagram showing a discharge signal generating circuit of the prior art.

Fig. 2 is a schematic view showing a liquid crystal display of the present invention.

Fig. 3 is a view showing the display controller and the discharge signal generating circuit of the present invention.

1, 2, C. . . End point

200. . . LCD Monitor

201. . . Drawing processing unit

210. . . Display panel

211. . . Gate drive circuit

212. . . Data drive circuit

220. . . Backlight module

230. . . Display controller

240. . . Discharge signal generating circuit

C _LC . . . Liquid crystal capacitor

C _ST . . . Storage capacitor

D ₁ ~D _M . . . Data line

G ₁ ~G _N . . . Gate line

PIX ₁ . . . Pixel

Q. . . Transistor

S _C . . . control signal

S _XON . . . Discharge signal

V _{TCON_PW} . . . power source

Claims (9)

A method for controlling a liquid crystal display, wherein a backlight module of the liquid crystal display receives a backlight power supply voltage to drive the backlight module, the method comprising: when the backlight module is turned off, generating a voltage proportional to the backlight power supply a detecting voltage; when the detecting voltage is less than a threshold voltage, accumulating a count value of the clock of the clock signal according to a clock signal received by the display controller of the liquid crystal display; comparing the count value with a predetermined shutdown time to generate a comparison result; and discharging a plurality of pixels of the liquid crystal display according to the comparison result. The method of claim 1, wherein the backlight module comprises a plurality of light-emitting diodes (LEDs), and the backlight power supply voltage is used to drive the plurality of light-emitting diodes. The method of claim 1, wherein discharging the plurality of pixels of the liquid crystal display according to the comparison result comprises: when the comparison result indicates that the count value is greater than the predetermined shutdown time, the plurality of pixels of the liquid crystal display Discharge. The method of claim 3, wherein when the comparison result indicates that the count value is greater than the predetermined shutdown time, discharging the plurality of pixels of the liquid crystal display comprises: Controlling a gate driving circuit of the liquid crystal display while enabling a plurality of gate lines coupled to the plurality of pixels in the liquid crystal display to discharge the plurality of pixels. The method of claim 1, further comprising: when the comparison result indicates that the count value is greater than the predetermined shutdown time, resetting the count value after a delay time elapses. A liquid crystal display comprising: a display panel comprising a gate driving circuit, a plurality of gate lines, a plurality of data lines, and a plurality of pixels, wherein the gate driving circuit enables one of the plurality of gate lines In the case of the polar line, the pixels coupled to the gate line of the plurality of pixels receive data through the corresponding data line; a backlight module is configured to provide backlight to the display panel, and the backlight module receives a backlight power supply voltage, To drive the backlight module; a display controller comprising: a detection circuit comprising: a voltage dividing circuit for generating a detection voltage equal to one of the backlight power supply voltages; and a second comparator Comparing the detected voltage with a threshold voltage, when the detected voltage is less than the threshold voltage, the second comparator generates a consistent energy signal indicating activation; and a counter is used to enable the enable signal to be enabled When the display control is accumulated a count value of a clock of a clock signal received by the controller; and a first comparator for comparing the count value with a predetermined shutdown time, when the count value is less than the predetermined shutdown time, the first comparison The controller generates the control signal indicating a first predetermined logic, and when the count value is greater than the predetermined shutdown time, the first comparator generates the control signal indicating a second predetermined logic; and a discharge signal generating circuit, And receiving, according to the control signal, a first voltage received by the display controller to generate a discharge signal; wherein when the gate driving circuit receives the discharge signal indicating discharge, the gate driving circuit simultaneously drives the plurality of strips a gate line for discharging the plurality of pixels. The liquid crystal display of claim 6, wherein the backlight module comprises a plurality of light-emitting diodes (LEDs), and the backlight power supply voltage is used to drive the plurality of light-emitting diodes. The liquid crystal display of claim 6, wherein the display controller further comprises: a delay circuit, when the delay circuit receives the control signal indicating the second predetermined logic, after a delay time, the delay circuit generates a delay circuit a reset signal; wherein the counter resets the count value according to the reset signal. The liquid crystal display of claim 6, wherein the discharge signal generating circuit comprises: a voltage dividing circuit for generating a second voltage proportional to one of the first voltages; a third comparator, configured to generate a comparison signal according to the second voltage and a reference voltage, when the second voltage is greater than the reference voltage, the comparison signal represents the first predetermined logic, and when the second voltage is less than The reference voltage, the comparison signal represents the second predetermined logic; a resistor comprising a first end for receiving the first voltage, and a second end for outputting the discharge signal; a transistor comprising a first The second end is coupled to the second end of the resistor, the second end is coupled to the ground end, and a control end; and an OR gate includes a first input terminal for receiving the control signal, and a second input terminal for Receiving the comparison signal, and an output coupled to the control end of the transistor, when the comparison signal or the control signal indicates the second predetermined logic, the OR gate controls the transistor to be turned on to cause the discharge signal The discharge is indicated, and when the comparison signal and the control signal both indicate the first predetermined logic, the OR gate controls the transistor to be turned off so that the discharge signal indicates no discharge.