KR20170079347A - Power supply device and display device - Google Patents

Abstract

The present invention provides a power supply device that supplies a voltage higher than a gate high voltage or a gate high voltage to the display panel continuously for a predetermined time even when the power is turned off so that the residual voltage remaining on the display panel, And can be completely discharged.

Description

[0001] POWER SUPPLY DEVICE AND DISPLAY DEVICE [0002]

The present invention relates to a power supply apparatus and a display apparatus including the same.

The display device is a device for displaying images or information. A liquid crystal display device among display devices displays an image by adjusting the light transmittance of a liquid crystal using an electric field.

The liquid crystal display includes at least one driver for generating at least one control signal and a liquid crystal display panel for displaying an image based on a control signal from the driver.

The driving unit of the liquid crystal display includes a power supply unit, a timing controller, a gate driver, a data driver, and a gamma generator.

The power supply unit includes a reference voltage (VCC) for driving a timing control unit, a gate driver and a data driver, a reference voltage (VDD) used for generating a gamma voltage in the gamma generation unit, and a gate signal (VGH, VGL).

The power supply unit includes a power cutoff unit that detects power off and disconnects the power supply of each component.

The power cutoff unit senses the voltage level of the reference voltage VCC and determines that the power is off when the voltage level of the reference voltage VCC falls below the under voltage lock-out (UVLO) voltage. UVLO can be set to a value smaller than the reference voltage (VCC).

When the power is interrupted, the gate high voltage VGH is temporarily supplied to all the gate lines of the liquid crystal display panel. In response to the gate high voltage VGH, the thin film transistor is turned on on each gate line, The residual voltage of the pixel region, that is, the DC voltage, can be discharged through each data line.

However, in the conventional case, when the power is cut off, the gate high voltage VGH is temporarily supplied to the liquid crystal display panel so that the residual voltage of each pixel region is discharged, but the voltage level of the gate high voltage is also rapidly The thin film transistor connected to each gate line is changed from the turn-on state to the turn-off state so that the residual voltage of each pixel region can no longer be discharged.

Therefore, in the conventional liquid crystal display device, the residual voltage of each pixel region of the liquid crystal display panel is discharged due to the gate high voltage (VGH) temporarily supplied to the liquid crystal display panel even in the power-off state, , A still image quality defect such as a residual image due to the residual voltage is still generated.

The present invention is directed to solving the above-mentioned problems and other problems.

It is another object of the present invention to provide a display device capable of minimizing image quality defects by causing discharge of each pixel region of a display panel to last longer.

According to an aspect of the present invention, there is provided a power supply apparatus including a first voltage generator for generating a first voltage, a power generator for generating a power off signal when the first voltage is equal to or lower than a first reference voltage, Blocking portion; A second voltage generator for generating a second voltage higher than the first voltage based on the first voltage, and a second voltage generator for generating a second voltage from the second voltage generator for a predetermined period of time from the time when the power- And a delay unit for delaying and outputting the second voltage.

With this configuration, the discharge gate high voltage (VGH) supplied to the display panel can be leveled down for as long as possible even when the level of the reference voltage (VCC) supplied to each component at the time of power- So that the image quality defect can be minimized.

According to another aspect of the present invention, a display device includes: a display panel for displaying an image; A power supply for generating a first voltage and a second voltage; A gate driver that is driven by the first voltage and supplies the second voltage supplied from the power supply unit to the display panel; And a data driver driven by the first voltage and supplying a data voltage for displaying the image to the display panel. The power supply unit may include a first voltage generator, a power cutoff unit, a second voltage generator, and a delay unit, as described above. In this configuration, particularly, even when the power is turned off by the power supply unit, the gate high voltage VGH having a constant high level for a predetermined time is supplied to the display panel, so that discharge of the display panel can be performed more quickly and completely.

Effects of the display device according to the present invention will be described as follows.

According to at least one of the embodiments of the present invention, even if the power off signal is output from the power cutoff unit, the power is turned on / off repeatedly for a certain period of time after the power off signal from the power cutoff unit is received by the delay unit The turn-on time of the thin film transistor of the liquid crystal display panel is increased by the gate high voltage (VGH) in the original state by causing the gate high voltage (VGH) generated by charging and discharging the inductor and the capacitor to be outputted from the VGH voltage generator, The residual voltage of each pixel region is discharged longer by the increase of the turn-on time of the jitter, so that the image quality defect can be minimized.

According to at least one of the embodiments of the present invention, even if a low-level power-off signal is input from the power cutoff unit to the delay unit, the VGH voltage generating unit, until the pulse generated from the pulse generating unit by the counter of the delay unit becomes the reference number The gate high voltage (VGH) generated by charging and discharging the inductor and the capacitor by repeatedly turning on / off the switch for a predetermined time from the time when the power off signal from the power cutoff unit is received is output from the VGH voltage generating unit, The turn-on time of the thin film transistor of the liquid crystal display panel is increased by the gate high voltage VGH in the original state, so that the residual voltage of each pixel region is discharged by the increase of the turn-on time of the thin film transistor, .

According to at least one of the embodiments of the present invention, when a power off signal is output from the power cutoff unit, the VGH voltage generator generates a high level signal of the pulse signal generated in the pulse generating unit The width and the width of the low level are adjusted to generate and output an OVP voltage that is larger than the gate high voltage VGH so that the voltage drop of the gate high voltage VGH is maximally delayed, It is possible to maximize the discharge of the voltage and to prevent an image quality defect such as afterimage.

Further scope of applicability of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, such as the preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art.

1 is a block diagram showing a liquid crystal display device according to the present invention.
2 is a block diagram showing the power supply unit of FIG.
3 is a circuit diagram showing a power supply unit according to the first embodiment of the present invention.
4 is a block diagram illustrating a power supply unit according to a second embodiment of the present invention.
5 is a waveform diagram showing an output waveform and a discharge waveform of the power supply unit according to the first and second embodiments of the present invention.
6 is a block diagram illustrating a power supply unit according to a third embodiment of the present invention.
7 is a waveform diagram showing an output waveform and a discharge waveform of the power supply unit according to the third embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals are used to designate identical or similar elements, and redundant description thereof will be omitted. The suffix "module" and " part "for the components used in the following description are given or mixed in consideration of ease of specification, and do not have their own meaning or role. In the following description of the embodiments of the present invention, a detailed description of related arts will be omitted when it is determined that the gist of the embodiments disclosed herein may be blurred. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. , ≪ / RTI > equivalents, and alternatives.

1 is a block diagram showing a liquid crystal display device according to the present invention.

1, a liquid crystal display according to the present invention includes a timing controller 20, a gamma generator 40, a gate driver 30, a data driver 50, a liquid crystal display panel 60, and a power supply unit 10 ).

Other elements other than the elements shown in Fig. 1 may be added, but the present invention is not limited thereto.

The power supply unit 10 may generate voltages for driving or driving each of the timing controller 20, the gamma generator 40, the gate driver 30 and the data driver 50.

The power supply unit 10 may generate at least one reference voltage VCC, VDD, a gate high voltage VGH or a gate low voltage VGL, for example. The power supply 10 may further generate voltages for driving the respective components, but the present invention is not limited thereto.

The reference voltage VCC may be 3.3 V, the reference voltage VDD may be 8 V, the gate high voltage VGH may be 25 V, and the gate low voltage VL may be -5 V, for example, It is not limited thereto.

For example, the reference voltage VCC is supplied to the timing controller 20, the gate driver 30 and the data driver 50 and is supplied to the timing controller 20, the gate driver 30 and the data driver 50 may be driven.

For example, the reference voltage VDD is supplied to the gamma generator 40, and a plurality of gamma voltages may be generated based on the reference voltage VDD.

For example, the gate high voltage VGH and the gate low voltage VGL are supplied to the gate driver 30, and the gate high voltage is sequentially supplied to the liquid crystal display panel 60 in units of one horizontal interval from the gate driver 30 . The gate high voltage VGH is supplied on the corresponding gate line of the liquid crystal display panel 60 during one horizontal period of one frame and the gate low voltage VGL is applied on the corresponding gate line of the liquid crystal display panel 60 for the remaining period. Can be supplied.

The timing control section 20 can be driven by the reference voltage VCC supplied from the power supply section 10. [ When the timing control unit 20 is driven, the timing control unit 20 can generate a gate control signal and a data control signal based on the control signals Vsync, Hsync, CLK, and DE received from the outside. The gate control signal may be supplied to the gate driver 30 and the data control signal may be supplied to the data driver 50. [ The timing controller 20 can also receive RGB video signals from outside. The RGB image received by the timing controller 20 may be supplied to the data driver 50 after being subjected to data alignment or data processing.

The gamma generation unit 40 may generate a plurality of gamma voltages based on the reference voltage VDD supplied from the power supply unit 10. [ The gamma voltage may be supplied to the data driver 50.

The gate driver 30 may be driven by the reference voltage VCC supplied from the power supply unit 10. [ When the gate driver 30 is driven, the gate driver 30 outputs the gate high voltage VGH or the gate low voltage VGL supplied from the power supply unit 10 in response to the gate control signal supplied from the timing control unit 20. [ Can be supplied to the liquid crystal display panel (60).

The data driver 50 may be driven by the reference voltage VCC supplied from the power supply unit 10. [ When the data driver 50 is driven, the data driver 50 responds to the RGB video signal by using a plurality of gamma voltages supplied from the gamma generator 40 in response to the data control signal supplied from the timing controller 20 Can be supplied to the liquid crystal display panel (60).

The liquid crystal display panel 60 may include two substrates and a plurality of liquid crystals interposed between the substrates. A plurality of gate lines and data lines intersecting with each other may be disposed on one of the substrates, and a thin film transistor may be connected to each of the gate lines and the data lines. A pixel electrode can be connected to the thin film transistor. The pixel region can be defined by the intersection of the gate line and the data line. A common electrode or a common line may be disposed on one substrate or another substrate of these substrates.

For example, the pixel electrodes are individually arranged for each pixel region, while the common electrodes can be arranged for all pixel regions.

When the gate high voltage VGH is supplied from the gate driver 30 to the gate line, the thin film transistor of each pixel region connected on the gate line by the gate high voltage VGH can be turned on. In this case, the data voltages supplied from the data driver 50 to the plurality of data lines of the liquid crystal display panel 60 may be applied to the corresponding pixel electrodes through the respective thin film transistors.

Therefore, the liquid crystal interposed between the substrates is displaced by the potential difference between the common voltage applied to the common electrode and the data voltage applied to each pixel electrode, so that the amount of light transmitted can be controlled and the image can be displayed. The gradation may be varied depending on the amount of light transmitted, so that an image can be realized.

On the other hand, when the power is turned off, the gate high voltage VGH is temporarily supplied to all the gate lines of the liquid crystal display panel 60 connected to the gate driver 30 for discharging the liquid crystal display panel 60 Can be supplied. In response to the gate high voltage VGH, each thin film transistor connected to each gate line is turned on so that a residual voltage charged in the pixel electrode connected to each thin film transistor, that is, a DC voltage is applied to each thin film transistor and each data line Lt; / RTI >

Even when the level of the reference voltage VCC supplied to each component at the time of power-off is lowered to the ground level, the discharge gate high voltage VGH supplied to the liquid crystal display panel 60 can be level- (level down), so that image quality defects can be minimized.

Hereinafter, a specific configuration for achieving the technical effect of the present invention will be described in detail.

2 is a block diagram showing the power supply unit 10 of FIG.

2, the power supply unit 10 includes a VCC voltage generation unit 110, a VDD voltage generation unit 140, a VGH voltage generation unit 150, a power cutoff unit 120, and a delay unit 130 can do.

Although not shown, the power supply unit 10 may further include a VGL voltage generating unit and a Vcom voltage generating unit, but the present invention is not limited thereto. The VGL voltage generating unit may generate the gate low voltage VGL and the Vcom voltage generating unit may generate the common voltage Vcom. The common voltage Vcom may be, for example, 4 V, but it is not limited thereto.

Although the power supply unit 10 may further include an AC-DC converting unit for converting the external AC voltage into the first DC voltage and a DC-DC converting unit for converting the first DC voltage to the second DC voltage, It is not limited thereto. The external AC voltage may be, for example, 220V. The second DC voltage may be larger or smaller than the first DC voltage.

For convenience of explanation, the VCC voltage generator 110, the VDD voltage generator 140, and the VGH voltage generator 150 may be referred to as first to third voltage generators.

The VCC voltage generating unit 110 generates the reference voltage VCC based on the second DC voltage and the VDD voltage generating unit 140 generates the reference voltage VDD based on the reference voltage VCC, The VGH voltage generator 150 may generate the gate high voltage VGH based on the reference voltage VDD.

Although not shown, the gate high voltage VGH may be generated directly from the reference voltage VCC.

The reference voltage VDD is higher than the reference voltage VCC and the gate high voltage VGH is higher than the reference voltage VDD.

For example, the reference voltage VCC may be 3.3 V, the reference voltage VDD may be 8 V, and the gate high voltage VGH may be 25 V, but the present invention is not limited thereto.

Since the reference voltage VDD is higher than the reference voltage VCC, the reference voltage VCC can be boosted up to generate the reference voltage VDD.

Similarly, since the gate high voltage VGH is larger than the reference voltage VDD, the reference voltage VDD can be stepped up to generate the gate high voltage VGH.

The power cut-off unit 120 detects the power-off and can cut off the outputs of the VDD voltage generating unit 140 and the VGH voltage generating unit 150 when the power-off is detected.

The power cutoff unit 120 may sense a change in the reference voltage VCC and determine whether the power is off. That is, it can be judged whether or not the reference voltage VCC is below the under-voltage lock-out (UVLO). The UVLO can be set to a value smaller than the reference voltage VCC as a reference value of the power-off. For example, UVLO may be 2.5V, but is not limited to this.

When the power-off is detected, the power cutoff unit 120 may supply a power-off signal to the VDD voltage generation unit 140 to cut off the output of the VDD voltage generation unit 140. [

The power off signal may be a low level signal, e.g., "0 ", but is not limited thereto.

A high level signal such as "1" may be transmitted as a power-on signal to the VDD voltage generator 140 and the delay unit 130 when the reference voltage VCC input to the power cut- have.

The power cutoff unit 120 may include a comparator (not shown) to which the reference voltage VCC and UVLO are input. When the reference voltage VCC is higher than UVLO, a high-level power-on signal is output. When the reference voltage VCC is lower than UVLO, a low-level power-off signal may be output.

The power off signal of the power cutoff unit 120 is not directly supplied to the VGH voltage generating unit 150. [ That is, the power-off signal of the power cut-off unit 120 may be supplied to the delay unit 130.

The delay unit 130 does not block the gate high voltage VGH of the VGH voltage generation unit 150 and outputs the output of the VGH voltage generation unit 150 for a predetermined time even if the power off signal is supplied from the power cut- Can be maintained.

Hereinafter, a circuit diagram for continuously maintaining the gate high voltage VGH of the VGH voltage generator 150 for a predetermined time period in spite of the power-off signal will be described with reference to FIGS. 2 and 3. FIG.

3 is a circuit diagram showing a power supply unit according to the first embodiment of the present invention.

Referring to FIG. 3, the output terminal of the VDD voltage generator 140 may be connected to the input terminal of the VGH voltage generator 150.

The VDD voltage generating unit 140 includes a capacitor 145 connected to the rear end of the inductor 143, a switch 142 connected in parallel with the capacitor 145 at the rear end of the inductor 143, And a pulse generator 141 connected to the gate terminal of the switch 144 and the diode 144 to be connected.

The inductor 143 and the capacitor 145 can boost the reference voltage VCC to the reference voltage VDD through charging and discharging of the reference voltage VCC. Charge / discharge of the reference voltage VCC can be performed by turning on / off the switch 142. [ For example, when the switch 142 is turned off, the reference voltage VCC is charged in the capacitor 145, and when the switch 142 is turned on, the voltage charged in the capacitor 145 can be output. For example, when the turn-off time of the switch 142 is made longer than the turn-on time, a voltage larger than the reference voltage VCC, that is, the reference voltage VDD can be generated.

One terminal of the switch 142 is connected between the inductor 143 and the diode 144 and the other terminal of the switch 142 is grounded and the gate terminal of the switch 142 is connected to the pulse generating section 141 .

The switching of the switch 142 can be operated by the pulse signal generated by the pulse generating unit 141. [

A power-off signal of a pie level may be supplied from the power cut-off unit 120 to the pulse generating unit 141 of the VDD voltage generator 140 when the reference voltage VCC falls below UVLO. The pulse generating section 141 can supply a continuous low level output signal to the switch 142 in response to the power off signal. The switch 142 can be continuously turned off in response to the low level output signal. In other words, while the power-on signal is supplied from the power cut-off unit 120 to the delay unit 130, the switch 142 is periodically turned on / off in response to the pulse signal supplied from the pulse generating unit 141, The reference voltage VDD generated by the charging and discharging of the capacitor 153 and the capacitor 155 can be outputted. On the other hand, while the power off signal is supplied from the power cutoff unit 120 to the delay unit 130, the switch 142 is continuously turned off in response to the continuous low level output signal supplied from the pulse generating unit 141 The voltage charged in the capacitor 155 is output, but the voltage charged in the capacitor 145 is lowered as time passes.

The configuration of the VGH voltage generator 150 is also similar to that of the reference voltage (VDD) voltage generator. That is, the VGH voltage generating unit 150 may include an inductor 153, a diode 154, a capacitor 155, a switch 152, and a pulse generating unit 151.

The inductor 153 and the capacitor 155 are connected in series to each other and the switch 152 is connected in parallel with the capacitor 155 at the rear end of the inductor 153 and the diode 154 is connected in series with the inductor 153 And the pulse generating section 151 can be connected to the gate terminal of the switch 152. [

The function of each component is substantially the same as the corresponding component of the VDD voltage generator 140.

However, the amplitude of the high level and / or the amplitude of the low level output from the pulse generator 151 of the VGH voltage generator 150 may be the same as the amplitude of the high level output from the pulse generator of the VDD voltage generator 140 and / / Or the amplitude of the low level. The width of the high level and / or the low level output from the pulse generating unit 151 of the VGH voltage generating unit 150 is a high level width output from the pulse generating unit of the VDD voltage generating unit 140, / / ≪ / RTI >

The delay unit 130 may cause the VGH voltage generation unit 150 to operate normally for a certain period of time after the power off signal is received even if the power off signal is received from the power cutoff unit 120, The gate high voltage VGH may be outputted from the gate of the transistor Q3.

The delay unit 130 may include a comparator 132. The reference voltage VCC may be input to the first input terminal of the comparator 132 and the reference voltage Vref may be input to the second input terminal of the comparator 132.

The reference voltage Vref may be lower than the reference voltage VCC as well as UVLO. For example, when the reference voltage VCC is 3.3V and the UVLO is 2.5V, the reference voltage Vref may be one voltage selected from 2.0V to 2.3V.

In the present invention, it is assumed that the reference voltage Vref is 2.0 V for convenience of explanation.

The pulse generator 151 of the VGH voltage generator 150 can be controlled by the output signal of the delay unit 130. [

The output signal of the delay unit 130 outputs a high level signal, for example, a "1" signal when the reference voltage VCC is higher than the reference voltage Vref and outputs a low level signal when the reference voltage VCC is lower than the reference voltage Vref A low level signal, for example, a "0" signal may be output.

Here, the low level signal may be a switch-off signal and the high-level signal may be a switch-on signal. The switch-off signal is a signal that always turns off the switch, and the output of the pulse generator 151 can always be maintained at a low level by the switch-off signal.

The reference voltage VCC input to the comparator 132 of the delay unit 130 gradually decreases due to the power-off even if the power-off signal is supplied from the power cutoff unit 120 to the delay unit 130, The comparator 132 outputs a switch-on signal of a high level to the pulse generating section 151 because the voltage VCC is higher than the reference voltage Vref and the pulse generating section 151 outputs the switch- In response to the switch-on signal, continuously generates a pulse signal in which the high level and the low level are repeated and outputs the generated pulse signal to the switch 1452. [ Accordingly, the reference voltage VDD is charged and discharged to be boosted as the switch 152 is continuously turned on / off repeatedly, so that the gate high voltage VGH can be outputted.

If the reference voltage VCC becomes lower than the reference voltage Vref due to a further voltage drop due to the power-off discharge, the comparator 132 outputs a low-level switch-off signal to the pulse generator 151, and the pulse generator 151 does not generate a pulse signal in which the high level and the low level are repeated, and only the low level output signal is continuously generated and supplied to the switch 152. Accordingly, the switch 152 is turned off in response to the output signal of the low level continuously so that only the voltage charged in the capacitor 155 is continuously output by the VGH voltage generating unit 150 and the voltage charged in the capacitor 155 Can be continuously dropped by the discharge.

In other words, even if the power-off signal is applied from the power cut-off unit 120, the delay unit 130 keeps the VGH voltage generator 150 constantly in the ON state until the reference voltage VCC becomes smaller than the reference voltage Vref. It is possible to output the high voltage VGH. When the reference voltage VCC becomes smaller than the reference voltage Vref, only the voltage charged in the capacitor 155 is output, and this voltage is continuously lowered to the ground level by the discharge.

According to the first embodiment of the present invention, even if the power off signal is output from the power cutoff unit 120, the delay unit 130 outputs the power off signal for a certain period of time from the time when the power off signal from the power cutoff unit 120 is received. The gate high voltage VGH generated by charging / discharging the inductor 153 and the capacitor 155 due to repeated turn-on / off of the switching element 152 is outputted from the VGH voltage generator 150, The turn-on time of the thin film transistor of the liquid crystal display panel 60 is increased by the gate high voltage VGH, and the residual voltage of each pixel region is discharged longer by the increase of the turn-on time of the thin film transistor, .

The pulse generator 151 included in the pulse generator 141 and / or the VGH voltage generator 150 included in the VDD voltage generator 140 may be included in the delay unit 130 or may be included in the delay unit 130 But the present invention is not limited thereto.

The delay unit 130 may be included in the VGH voltage generation unit 150 or the power cutoff unit 120, but the present invention is not limited thereto.

4 is a block diagram illustrating a power supply unit according to a second embodiment of the present invention.

The second embodiment may omit the pulse generating unit 133 in the VDD voltage generating unit 140 and the VGH voltage generating unit 150 of the power supply unit 10 according to the first embodiment.

The configuration of the delay unit 130 of the second embodiment is different from that of the first embodiment.

The VDD voltage generating unit 140 and the VGH voltage generating unit 150 of the power supply unit 10 of the second embodiment can be easily understood from the first embodiment and therefore detailed description will be omitted.

4, the delay unit 130 may include a counter 132, a pulse generator 133, and an AND gate 134. [

The pulse generating unit 133 may be the same as the pulse generating unit 133 included in the VDD voltage generating unit 140 and the VGH voltage generating unit 150 of the power supply unit 10 according to the first embodiment.

The counter 132 is connected to the pulse generator 133 and can count the number of pulses output from the pulse generator 133.

The counter 132 may be operated in response to a power off signal output from the power cutoff unit 120. [

As described above, the power cut-off unit 120 can output a low-level power off signal when the reference voltage VCC becomes lower than UVLO.

The pulse generating unit 133 can generate a pulse signal in which the high level and the low level are repeated. The pulse signal generated by the pulse generator 133 may be input to the AND gate 134 and the switch 152 included in the VGH voltage generator 150.

The AND gate 134 operates the AND gate 134 to compute the power off signal output from the power cutoff unit 120 and the pulse signal output from the pulse generating unit 133 and outputs a high level signal, Or a low level signal, that is, "0 ".

For example, when a low-level power-off signal is input to the AND gate 134 from the power cutoff unit 120, a low-level power-off signal, i.e., "0" 0 "from the AND gate 134 to the switch 142 included in the VDD voltage generator 140 regardless of the level of the pulse signal output from the pulse generator 133 . Accordingly, since the switch 142 included in the VDD voltage generator 140 is turned off, the voltage charged in the capacitor 145 is output as the reference voltage VDD, but the charging voltage is quickly lowered due to the discharge . Therefore, the reference voltage (VDD) is not supplied to the gamma generator (40 in FIG. 1), and the gamma voltage is not generated from the gamma voltage generator (40 in FIG. 1).

On the other hand, when a low-level power-off signal is input from the power cutoff unit 120 to the counter 132, the counter 132 is operated by the low-level power-off signal and is generated in the pulse generating unit 133 The number of pulses is counted.

When the number of pulses coincides with the reference number, the pulse generation section 133 controls the pulse generation section 133 to output a low level output signal. The output signal of the low level may be input to the gate terminal of the switch 152 included in the VGH voltage generator 150 as well as the AND gate 134. Therefore, since the switch 152 included in the VGH voltage generation unit 150 is turned off in response to the low level output signal output from the pulse generation unit 133, the voltage charged in the capacitor 155 becomes the gate high voltage (VGH).

According to the second embodiment of the present invention, even when a low-level power-off signal is input from the power cutoff unit 120 to the delay unit 130, the counter 132 of the delay unit 130 outputs the pulse- The VGH voltage generator 150 repeatedly turns on / off the switch 152 for a certain period of time from the time when the power off signal from the power cutoff unit 120 is received until the pulse generated from the switch The gate high voltage VGH generated by charging and discharging the inductor 153 and the capacitor 155 is outputted from the VGH voltage generating unit 150 so that the liquid crystal display The turn-on time of the thin film transistor of the panel 60 is increased, and the residual voltage of each pixel region is discharged longer by the increase of the turn-on time of the thin film transistor, so that the image quality defect can be minimized.

If the amplitude or pulse width of the pulse of the pulse generator 133 included in the VDD voltage generator 140 of the power supply unit 10 is greater than the pulse width of the pulse included in the VGH voltage generator 150, The pulse generating unit 133 shown in FIG. 4 generates a pulse for the VDD voltage generating unit 140 and a pulse for the VGH voltage generating unit 150 It may be divided into parts. In this case, the counter 132 is connected only to the pulse generator for the VGH voltage generator 150, and can count the pulses generated by the pulse generator for the VGH voltage generator 150. The output terminal of the pulse generator for the VDD voltage generator 140 is connected to the input terminal of the AND gate 134 and the output terminal of the pulse generator for the VGH voltage generator 150 is connected to the switch included in the VGH voltage generator 150. [ (Not shown).

5 is a waveform diagram showing an output waveform and a discharge waveform of the power supply unit according to the first and second embodiments of the present invention.

5, in the power supply unit 10 according to the first and second embodiments of the present invention, the pulse generation of the VGH voltage generator 150 during the predetermined time t1 from the power- A pulse signal is continuously generated in a pulse generating section (133 in FIG. 3) or a pulse generating section (133 in FIG. 4) of the delay section 130 so that the same level as the gate high voltage (VGH) The gate high voltage VGH of the transistor Q3 can be output. The power-off timing may be the timing at which the low-level power-off signal output from the power cutoff unit 120 is input to the delay unit 130, but the present invention is not limited thereto.

6 is a block diagram illustrating a power supply unit according to a third embodiment of the present invention.

Referring to FIG. 6, the power supply unit 10 may include a VCC voltage generator 110, a VDD voltage generator 140, a VGH voltage generator 150, and a power cutoff unit 120.

The VCC voltage generating unit 110 may generate the reference voltage VCC based on the DC voltage generated from the DC-DC converting unit (not shown).

The VDD voltage generator 140 may generate a reference voltage VDD that is greater than the reference voltage VCC based on the reference voltage VCC from the VCC voltage generator 110. [

The VGH voltage generator 150 may generate the gate high voltage VGH that is larger than the reference voltage VDD based on the reference voltage VDD from the VDD voltage generator 140. [

The power cutoff unit 120 determines whether the reference voltage VCC is less than or equal to the UVLO based on the reference voltage VCC from the VCC voltage generator 110. When the reference voltage VCC is less than the UVLO, Signal to the VDD voltage generating unit 140 and the VGH voltage generating unit 150, respectively.

The outputs of the VDD voltage generator 140 and the VGH voltage generator 150 may be cut off in response to a power off signal from the power cutoff unit 120. [ However, the VGH voltage generator 150 may output an over-voltage protection (OVP) voltage higher than the power gate high voltage VGH for a predetermined time from the power-off time point as the gate high voltage VGH, Will be described in detail.

The VDD voltage generator 140 outputs a low level signal from the pulse generator (141 in FIG. 3) included in the VDD voltage generator 140 in response to the power off signal from the power cutoff unit 120, The switch (142 in FIG. 3) is turned off in response to the low level signal so that the reference voltage (VDD) is no longer generated, and the voltage charged in the capacitor (see 145 in FIG. 3) .

The VGH voltage generator 150 does not stop the voltage of the gate high voltage VGH immediately even if the power off signal from the power cutoff unit 120 is received. In other words, the VGH voltage generator 150 generates a voltage higher than the gate high voltage VGH, for example, an over-voltage protection (OVP) voltage for a certain period of time from when the power off signal from the power cutoff unit 120 is received Can be output. The voltage charged in the capacitor 155 included in the VGH voltage generator 150 may be gradually discharged and output.

More specifically, the VGH voltage generator 150 includes first and second resistors 156 and 157 connected in parallel with each other in series with each other, an inductor 153 connected in parallel with the inductor 153, A capacitor 155 disposed between the inductor 153 and the first resistor 156 and a diode 154 and an inductor 153 connected in series with the inductor 153 and disposed between the inductor 153 and the capacitor 155, And a switch 152 connected between the diodes 154.

The inductor 153 and the capacitor 155 can boost the reference voltage VDD to the gate high voltage VGH by the continuous turn-on / off switching of the switch 152. [

Diode 154 may block the flow of reverse current.

The first and second resistors 156 and 157 can detect and feedback the voltage at the output terminal of the VGH voltage generator 150. The first and second resistors 156 and 157 may be referred to as detectors.

The VGH voltage generator 150 includes a comparator 158, an amplifier 159 connected to the output of the comparator 158, a pulse controller 162 connected to the output of the amplifier 159, and a pulse controller 162 And a pulse generating unit 151 connected to the output terminal.

The first input terminal of the comparator 158 is connected between the first and second resistors 156 and 157 to receive a detected voltage (hereinafter referred to as a feedback voltage) at the output terminal of the VGH voltage generator 150, And the second input terminal of the second transistor 158 may be grounded.

The comparator 158 can output different output values according to the comparison of the reference voltage VCC and UVLO.

For example, when the reference voltage VCC is higher than UVLO, the comparator 158 can output a feedback signal since it is in a power-on state.

For example, when the reference voltage VCC is lower than or equal to the UVLO, the comparator 158 can output the ground voltage since it is in the power off state.

The first input terminal of the amplifier 159 is connected to the output terminal of the comparator 158 and a predetermined voltage is applied to the second input terminal of the amplifier 159. The predetermined voltage is smaller than the feedback voltage and larger than the ground voltage.

When the feedback voltage output from the comparator 158 is input to the first input terminal of the amplifier 159, the amplifier 159 amplifies the feedback voltage and outputs the output voltage from the comparator 158 to the first input terminal of the amplifier 159 When the ground voltage is input, the amplifier 159 can output the ground voltage.

The pulse control unit 162 can control the pulse generation unit 151 based on the output voltage output from the amplifier 159.

For example, when the amplified feedback voltage is outputted from the amplifier 159, the pulse control unit 162 can control the pulse generation unit 151 to maintain the presently generated pulse state.

For example, when the ground voltage is output from the amplifier 159, the pulse control unit 162 increases the width of the low level and the width of the high level in the pulse signal of the high level and the low level, Can be controlled to be reduced. The turn-off time of the switch 152 is increased and the turn-off time of the switch 152 is increased by the high-level and low-level pulse signals whose widths are adjusted as described above. The voltage charged in the capacitor 155 is output during the turn-on time of the switch 152 and the reference voltage VDD can be charged to the capacitor 155 during the turn-off time of the switch 152. [ Accordingly, the OVP voltage that is ultimately higher than the gate high voltage (VGH) can be generated by increasing the charging time of the reference voltage (VDD) to the capacitor (155) and decreasing the output time of the voltage charged to the capacitor have.

During the set period, the pulse generator 162 generates the pulse signal having the adjusted width of the high level and the low level, respectively, under the control of the pulse controller 162 have.

For example, the width of the high level may be gradually decreased and the width of the low level may be controlled to gradually increase during the set period, but the present invention is not limited thereto.

7 is a waveform diagram showing an output waveform and a discharge waveform of the power supply unit according to the third embodiment of the present invention.

7, in the power supply unit 10 according to the third embodiment of the present invention, even if the power is turned off, the pulse generator 151 of the VGH voltage generator 150 for a predetermined time t1 from the power- The width of the high level and the width of the low level of the pulse signal generated by the gate high voltage VGH are adjusted so that the OVP voltage is generated so that the OVP voltage can be output for the time t1. The power-off timing may be the timing at which the low-level power-off signal output from the power cutoff unit 120 is input to the delay unit 130, but the present invention is not limited thereto.

According to the third embodiment of the present invention, when a power off signal is output from the power cutoff unit 120, the VGH voltage generation unit 150 generates a pulse signal for a predetermined time from the time when the power off signal is received, The width of the high level and the width of the pulse signal generated by the gate high voltage VGH are adjusted to generate and output an OVP voltage that is larger than the gate high voltage VGH to thereby delay the voltage drop of the gate high voltage VGH as much as possible, It is possible to maximize the discharge of the residual voltage charged in each pixel region of the panel 60 and to prevent the image quality defect like the afterimage.

Meanwhile, the third embodiment of the present invention can be combined with the first embodiment of the present invention or the second embodiment of the present invention to form a new embodiment, but the present invention is not limited thereto.

According to the new embodiment configured as described above, not only the gate high voltage VGH having a constant high level for a certain time from the power-off time can be output, but also a voltage higher than the gate high voltage VGH, So that it is possible to discharge more completely to the residual voltage charged in each pixel region of the liquid crystal display panel 60, so that image quality defects such as afterimages can be prevented.

The foregoing detailed description should not be construed in all aspects as limiting and should be considered illustrative. The scope of the present invention should be determined by rational interpretation of the appended claims, and all changes within the scope of equivalents of the present invention are included in the scope of the present invention.

10: Power supply
20:
30: gate driver
40: gamma generator
50: Data driver
60: liquid crystal display panel
110: VCC voltage generator
120: Power interruption part
130:
140: VDD voltage generator
150: VGH voltage generator

Claims (11)

A first voltage generator for generating a first voltage;
A power cutoff unit generating a power off signal when the first voltage is lower than a first reference voltage;
A second voltage generator for generating a second voltage greater than the first voltage based on the first voltage, the second voltage being used to discharge a residual voltage of the display device; And
And a delay unit for delaying the second voltage from the second voltage generator for a predetermined time after the power off signal is received from the power cutoff unit. The method according to claim 1,
Wherein the second voltage generator comprises:
Inductors;
A capacitor connected to the inductor; And
And a switch connected in parallel to the capacitor at a rear end of the inductor. 3. The method of claim 2,
Wherein the second voltage generator comprises:
And a pulse generator connected to a gate terminal of the switch,
Wherein the delay unit comprises:
And a comparator to which the first voltage is input to the first input terminal and the second reference voltage that is less than the first reference voltage is input to the second input terminal,
The comparator comprising:
During a period of time from a power-off time when the first voltage becomes equal to or lower than the first reference voltage to a time when the first voltage becomes the second reference voltage, To the pulse generator, a switch-on signal for controlling the pulse signal to be continuously output from the pulse generator. The method of claim 3,
The comparator comprising:
And a switch-off signal for controlling the pulse generator to output a low-level output signal for switching the switch to an off state when the first reference voltage is lower than the second reference voltage, Power supply. 3. The method of claim 2,
Wherein the delay unit comprises:
A pulse generator connected to a gate terminal of the switch; And
A pulse from the pulse generator to continuously output a pulse signal in the pulse generator for a periodic switching operation of the switch for a predetermined time from a power-off time when the first voltage is lower than the first reference voltage; A power supply comprising a counter for counting the number 6. The method of claim 5,
Wherein the predetermined time is when the number of pulses counted by the counter becomes a reference count. 3. The method of claim 2,
Wherein the second voltage generator comprises:
A pulse generator connected to a gate terminal of the switch;
A detector for detecting a voltage of an output terminal of the second voltage generator as a feedback signal;
A comparator for outputting one of the feedback signal and the ground voltage according to a comparison between the first voltage and the first reference voltage;
And a pulse controller for controlling the width of the pulse output from the pulse generator when the ground voltage is output from the comparator. 8. The method of claim 7,
The comparator comprising:
And outputs the ground voltage when the first voltage is lower than the first reference voltage. 8. The method of claim 7,
Wherein the pulse control unit comprises:
Adjusting the pulse width for a predetermined time from the power-
Wherein the predetermined time is preset. 10. The method of claim 9,
Wherein the pulse control unit comprises:
Wherein during the predetermined time, the width of the low level of the pulse is increased and the width of the high level of the pulse is decreased. A display panel for displaying an image;
A power supply for generating a first voltage and a second voltage;
A gate driver that is driven by the first voltage and supplies the second voltage supplied from the power supply unit to the display panel; And
And a data driver driven by the first voltage and supplying a data voltage for displaying the image to the display panel,
The power supply unit,
A first voltage generator for generating a first voltage;
A power cutoff unit generating a power off signal when the first voltage is lower than a first reference voltage;
A second voltage generator for generating a second voltage greater than the first voltage based on the first voltage, the second voltage being used to discharge a residual voltage of the display device; And
And a delay unit for delaying and outputting the second voltage from the second voltage generator for a predetermined time after the power off signal is received from the power cutoff unit.

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