CN115497430A

CN115497430A - Control circuit and control method of display panel and display device

Info

Publication number: CN115497430A
Application number: CN202211282009.7A
Authority: CN
Inventors: 刘冬; 苏国火; 张银龙; 廖燕平; 林准; 陈航宇; 兰箭
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2022-12-20
Anticipated expiration: 2042-10-19
Also published as: CN115497430B

Abstract

The embodiment of the invention provides a control circuit, a control method and display equipment of a display panel. The feedback circuit may generate a feedback signal according to the digital GOA signal output by the timing control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and the timing control circuit may control output of the digital GOA signal and the digital data signal according to the feedback signal. When the voltage conversion circuit is in a protection state and is damaged or the first analog GOA signal and the second analog GOA signal are in the same phase, the time sequence control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal, so that the problem of abnormal display pictures of the display panel is avoided.

Description

Control circuit and control method of display panel and display device

Technical Field

The present invention relates to the field of display control technologies, and in particular, to a control circuit and a control method for a display panel, and a display device.

Background

With the development of display industry and the improvement of material level of people, display systems using display panels as display ports have been increasingly integrated into people's daily life and work. The display panel has the advantages of small volume, low power consumption, no radiation, low manufacturing cost and the like.

In the use process of the display panel, the problem of abnormal picture display can occur in some cases. For example, when a short circuit or a timing disorder occurs inside a GOA (Gate drive on Array) unit of the display panel, when a circuit temperature exceeds a temperature threshold due to a high temperature environment, when two analog GOA signals output by the voltage conversion circuit are in phase, a protection state of the voltage conversion circuit is triggered, or the voltage conversion circuit is damaged, the display screen of the display panel is abnormal.

Disclosure of Invention

An embodiment of the present invention provides a circuit design method, device, apparatus and storage medium for a display panel, so as to avoid the problem of abnormal display screen of the display panel. The specific technical scheme is as follows:

in a first aspect, an embodiment of the present invention provides a control circuit for a display panel, where the control circuit includes a power management circuit, a timing control circuit, a voltage conversion circuit, a source driving circuit, and a feedback circuit, where:

the power management circuit is respectively connected with the sequential control circuit, the voltage conversion circuit and the source driving circuit; the time sequence control circuit is respectively connected with the voltage conversion circuit and the source driving circuit; the voltage conversion circuit and the source drive circuit are respectively connected with the display panel; the feedback circuit is respectively connected with the time sequence control circuit and the voltage conversion circuit;

the feedback circuit is used for generating a feedback signal according to the digital GOA signal output by the time sequence control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and outputting the feedback signal to the time sequence control circuit;

and the time sequence control circuit is used for controlling the output of the digital GOA signal and the digital data signal according to the feedback signal.

Optionally, the feedback circuit includes a comparison circuit, a first in-phase flip-flop, and an edge flip-flop, where:

the input end of the comparison circuit is connected with the output end of the voltage conversion circuit, the input end of the edge trigger is connected with the output end of the time sequence control circuit, the input end of the first in-phase trigger is respectively connected with the output end of the comparison circuit and the output end of the edge trigger, and the output end of the first in-phase trigger is connected with the time sequence control circuit;

the comparison circuit is used for generating a first level signal according to whether the first analog GOA signal and the second analog GOA signal output by the output end of the voltage conversion circuit are in phase or not, and outputting the first level signal to the input end of the first in-phase trigger;

the edge trigger is used for generating a second level signal according to the level change of the digital GOA signal output by the output end of the time sequence control circuit and outputting the second level signal to the input end of the first same-phase trigger;

the first non-inverting flip-flop is configured to generate a feedback signal according to a level difference between the first level signal and the second level signal, and output the feedback signal to the timing control circuit.

Optionally, the comparison circuit includes a first comparator, a second comparator and a second non-inverting flip-flop, where:

the input end of the first comparator is connected with a first analog GOA signal output end of the voltage conversion circuit, the input end of the second comparator is connected with a second analog GOA signal output end of the voltage conversion circuit, the input end of the second in-phase trigger is respectively connected with the output end of the first comparator and the output end of the second comparator, and the output end of the second in-phase trigger is connected with the input end of the first in-phase trigger;

the first comparator is configured to generate a third level signal according to a magnitude relationship between the first analog GOA signal and a preset threshold, and output the third level signal to an input end of the second in-phase flip-flop;

the second comparator is configured to generate a fourth level signal according to a magnitude relationship between the second analog GOA signal and the preset threshold, and output the fourth level signal to an input end of the second in-phase flip-flop;

the second in-phase flip-flop is configured to generate a first level signal according to a level difference between the third level signal and the fourth level signal, and output the first level signal to an input end of the first in-phase flip-flop.

Optionally, the time point when the edge flip-flop is configured to output the second level signal to the input terminal of the first in-phase flip-flop is later than the time point when the level of the digital GOA signal changes;

the second in-phase flip-flop is configured to output the first level signal to an input terminal of the first in-phase flip-flop at a time point later than a time point at which the third level signal and the fourth level signal are generated, and a first time difference is larger than a second time difference;

the first time difference is a difference between a time point when the edge flip-flop outputs the second level signal to the input terminal of the first in-phase flip-flop and a time point when the level of the digital GOA signal changes, and the second time difference is a difference between a time point when the second in-phase flip-flop outputs the first level signal to the input terminal of the first in-phase flip-flop and a time point when the third level signal and the fourth level signal are generated.

Optionally, the control circuit further includes a system end, and the system end is connected to the feedback circuit and the power management circuit respectively;

the feedback circuit is further used for outputting the feedback signal to the system end;

and the system end is used for closing the backlight of the display panel according to the feedback signal.

Optionally, the control circuit further includes a system end, and the system end is connected to the timing control circuit and the power management circuit respectively;

the time sequence control circuit is also used for outputting the feedback signal to the system end;

Optionally, the feedback circuit is integrated inside the voltage conversion circuit.

In a second aspect, an embodiment of the present invention provides a control method for a display panel, which is applied to a timing control circuit in the control circuit of any one of the first aspect, where the method includes:

acquiring a feedback signal output by the feedback circuit;

and controlling the output of the digital GOA signal and the digital data signal according to the feedback signal.

Optionally, the controlling the output of the digital GOA signal and the digital data signal according to the feedback signal includes:

stopping outputting the digital GOA signal;

if the digital data signal is in an output state, adjusting the digital data signal to enable the output data to be black screen image data;

and if the digital data signal is in a non-output state, keeping the digital data signal in the non-output state.

In a third aspect, an embodiment of the present invention provides a display device, where the display device includes the control circuit and the display panel described in any one of the first aspect.

The embodiment of the invention has the following beneficial effects:

in the scheme provided by the embodiment of the invention, the control circuit can comprise a power management circuit, a time sequence control circuit, a voltage conversion circuit, a source drive circuit and a feedback circuit, wherein the power management circuit is respectively connected with the time sequence control circuit, the voltage conversion circuit and the source drive circuit; the time sequence control circuit is respectively connected with the voltage conversion circuit and the source drive circuit; the voltage conversion circuit and the source drive circuit are respectively connected with the display panel; the feedback circuit is respectively connected with the time sequence control circuit and the voltage conversion circuit; the feedback circuit is used for generating a feedback signal according to the digital GOA signal output by the time sequence control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and outputting the feedback signal to the time sequence control circuit; and the time sequence control circuit is used for controlling the output of the digital GOA signal and the digital data signal according to the feedback signal. The feedback circuit can generate a feedback signal according to the digital GOA signal output by the sequential control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and output the feedback signal to the sequential control circuit, and then the sequential control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal. Therefore, when the voltage conversion circuit is in a protection state, the two analog GOA signals output by the voltage conversion circuit are accidentally in phase, or the voltage conversion circuit is damaged, so that the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit are changed, the time sequence control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal, and the problem of abnormal display pictures of the display panel is avoided. Of course, it is not necessary for any product or method to achieve all of the above-described advantages at the same time for practicing the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other embodiments can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a circuit diagram of a control circuit of a display panel according to the related art;

FIG. 2 is a timing diagram of the control circuit of FIG. 1 under normal operating conditions;

FIG. 3 is a timing diagram of the voltage converting circuit shown in FIG. 1 when the protection state is triggered or the voltage converting circuit is damaged;

FIG. 4 is a diagram illustrating a display panel displaying an abnormal image according to the related art;

FIG. 5 is a timing diagram illustrating the analog GOA signal outputted from the voltage converting circuit of the control circuit shown in FIG. 1 in the same phase;

fig. 6 is a circuit diagram of a control circuit of a display panel according to an embodiment of the invention;

FIG. 7 is a circuit diagram of a control circuit including a comparison circuit, a first in-phase flip-flop, and an edge flip-flop, based on the circuit diagram of FIG. 6;

FIG. 8 is a circuit diagram of a comparison circuit based on the circuit diagram shown in FIG. 7;

fig. 9 is a timing diagram corresponding to a normal operating state of the control circuit provided in the present invention;

fig. 10 is a timing diagram corresponding to the protection state of the voltage conversion circuit being triggered or the voltage conversion circuit being damaged according to the present invention;

FIG. 11 is a schematic view of a display screen of a display panel according to an embodiment of the present invention;

FIG. 12 is a timing diagram illustrating the LC _1 signal and the LC _2 signal in phase according to an embodiment of the present invention;

fig. 13 is a circuit diagram of a control circuit including a system terminal according to an embodiment of the present invention;

fig. 14 is a circuit diagram of another control circuit including a system terminal according to an embodiment of the present invention;

fig. 15 is a flowchart illustrating a control method of a display panel according to an embodiment of the invention;

fig. 16 is a schematic diagram of a display device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by one skilled in the art based on the embodiments of the present invention, are within the scope of the present invention.

In the scheme provided by the embodiment of the invention, the display panel can be a liquid crystal display panel and is usually applied to display equipment, and the display equipment is connected with an external power supply and supplies power to the display panel by the external power supply. The display panel may include data lines, a GOA unit, a pixel unit, and the like, and the pixel unit may implement picture display based on the data voltage provided by the control circuit.

The control circuit of the display panel can control the display of the display panel, and the control circuit of the display panel in the related art includes a power management circuit 101, a timing control circuit 102, a voltage conversion circuit 103, and a source driving circuit 104, as shown in fig. 1.

The power management circuit 101 may receive a voltage signal supplied from the system terminal, generate a plurality of voltage signals, and distribute the generated voltage signals to the timing control circuit 102, the voltage conversion circuit 103, and the source drive circuit 104. The voltage signal distributed to the voltage conversion circuit 103 at least includes a VGH (Vgatehigh, high potential of gate level) signal and a VGL (Vgatelow, low potential of gate level) signal, and the voltage signal distributed to the source driving circuit 104 at least includes an analog voltage signal, where the VGH signal is usually much larger than GND (Ground potential), the VGL signal is usually smaller than GND, for example, the VGH signal may have a value of 25V, 32V, etc., and the VGL signal may have a value of-8V, -12V, etc. The analog voltage signal may be an AVDD (analog operating voltage) signal, an HAVDD (half operating voltage) signal, or the like.

The timing control circuit 102 may receive the data signal and each control signal sent by the system side, generate a P2P signal (digital data signal), send the P2P signal to the source driving circuit 104, generate a digital GOA signal, and send the digital GOA signal to the Voltage conversion circuit 103, where the digital GOA signal at least includes an LC _ in signal, and the data signal sent by the system side may be a VBO (V-by-One) signal, an LVDS (Low-Voltage Differential Signaling, low-Voltage Differential signal), or the like.

The voltage conversion circuit 103 may combine the received digital GOA signal, VGH signal, and VGL signal to generate an analog GOA signal, and output the analog GOA signal to the display panel GOA unit, where the analog GOA signal at least includes a first analog GOA signal and a second analog GOA signal, and the first analog GOA signal and the second analog GOA signal are LC _1 and LC _2 in fig. 1.

Specifically, the first analog GOA signal and the second analog GOA signal may be generated based on the LC _ in signal, the VGH signal, and the VGL signal, and the first analog GOA signal and the second analog GOA signal are in an inverted state under a normal operation state of the control circuit.

The source driving circuit 104 may combine the received P2P signal with the analog voltage signal to generate a data voltage signal, and transmit the data voltage signal to the pixel unit through the data line of the display panel.

The GOA units in the display panel 105 can be configured to receive the analog GOA signals output by the voltage conversion circuit 103 and generate gate driving signals to turn on the pixel units, and the data lines can be configured to receive the data voltage signals output by the source driving circuit 104 and output the data voltage signals to the pixel units, so that the pixel units display pictures.

Fig. 2 is a timing diagram of the control circuit shown in fig. 1 under a normal operating state, wherein, for example, a first signal of the LC _ in signal is a digital high level signal, and the first analog GOA signal and the second analog GOA signal are triggered to be inverted, when the LC _ in signal is first changed from a digital low level signal to a digital high level signal, the first analog GOA signal is a high level signal, the second analog GOA signal is a low level signal, when the LC _ in signal is first changed from a digital high level signal to a digital low level signal, the second analog GOA signal is a high level signal, the first analog GOA signal is a low level signal, and potentials of the first analog GOA signal and the second analog GOA signal may change with the high-low level switching of the LC _ in signal.

In a power-on stage, namely a stage from power-on to system stability and normal operation, the power-on time of the VGH signal is generally later than that of the VGL signal, the time when the LC _ in signal is changed from the digital low-level signal to the digital high-level signal for the first time is later than the time when the power-on of the VGH signal is completed, and the difference time between the two times is T1, wherein T1 is a value greater than 0.

The first analog GOA signal and the second analog GOA signal are set high together with the VGH signal in the initial stage of the power-on phase, and when the voltage converting circuit 103 receives the LC _ in signal sent by the first timing control circuit 102, taking the LC _ in signal as an example from a digital low level signal to a digital high level signal, the first analog GOA signal and the second analog GOA signal are inverted, that is, the first analog GOA signal keeps a high level signal, and the second analog GOA signal is switched to a low level signal. Of course, the first analog GOA signal and the second analog GOA signal may be inverted such that the first analog GOA signal is switched to a low level signal and the second analog GOA signal remains a high level signal. In a state that the control circuit normally works, the first analog GOA signal and the second analog GOA signal are always switched in phase with the high-low level switching of the LC _ in signal, and are kept in an inverted state.

In fig. 2, T3 is a duration during which the first analog GOA signal and the second analog GOA signal are at a high level, T4 is a duration during which the first analog GOA signal and the second analog GOA signal are at a low level, and T3 and T4 are generally in the order of seconds.

The time when the timing control circuit 102 sends the P2P signal is later than the time when the LC _ in signal is first switched from the digital low level signal to the digital high level signal, and the difference between the two times is T2, where T2 is a value greater than 0. That is, the timing control circuit 102 first sends the LC _ in signal to the voltage conversion circuit 103, so that the voltage conversion circuit 103 generates the first analog GOA signal and the second analog GOA signal and sends them to the display panel GOA unit, and then sends the P2P signal to the source driving circuit 104, so that the source driving circuit 104 generates the data voltage signal to the display panel data line.

In the power-off stage, that is, the system is disconnected from the power supply, the VGL signal, the first analog GOA signal and the second analog GOA signal are simultaneously raised to the high level signal corresponding to the VGH signal and are powered down along with the VGH signal. During the power-down period, the LC _ in signal will stop outputting, while the P2P signal will generally stop outputting before the VGH signal is powered down, and the data voltage signal will also stop outputting along with the P2P signal.

As shown in the timing chart corresponding to the protection state shown in fig. 3, when the protection state of the voltage conversion circuit 103 is triggered or damaged, and the voltage conversion circuit 103 has no output, taking the case of over-current protection as an example, when the over-current protection, that is, the current flowing through the voltage conversion circuit 103 is greater than the threshold, the protection state of the voltage conversion circuit 103 is triggered, the voltage conversion circuit 103 stops outputting the first analog GOA signal and the second analog GOA signal, and the first analog GOA signal and the second analog GOA signal gradually return to GND.

Since the VGH signal and the VGL signal are controlled by the power management circuit 101, the LC _ in signal and the P2P signal are controlled by the timing control circuit 102, the data voltage signal is controlled by the source driving circuit 104, and only the voltage conversion circuit 103 stops outputting when the protection state of the voltage conversion circuit 103 is triggered or damaged, the VGH signal, the VGL signal, the LC _ in signal, the P2P signal and the data voltage still maintain the output state.

Since the voltage converting circuit 103 stops outputting the analog GOA signal to the GOA unit of the display panel, the GOA unit is in floating state, and when there is more charges remaining therein, the gate driving signal is still generated to turn on the pixel unit, which is more obvious when the GOA unit is fabricated by using oxide process. Because there is no analog GOA signal, the on or off state of the pixel units is not controlled, which results in the synchronous on of multiple rows of pixels, so that the data voltage signal can enter into multiple rows of pixel units at the same time, and the display panel can display abnormal pictures.

As shown in fig. 4, the display screen of the display panel may be shown as a display panel 401, a display panel 402, a display panel 403, and a display panel 404. The display panel 401 and the display panel 402 are in a normal condition, and the display content of the display panel is switched from "HELLO" shown by the display panel 401 to "ABCD" shown by the display panel 402. If the voltage conversion circuit is triggered, the analog GOA signal stops outputting, which results in synchronous turning on of multiple rows of pixels, that is, synchronous turning on of pixel units in the same row as the pixel units corresponding to "HELLO" shown in the display panel 401 and "ABCD" shown in the display panel 402, the data voltage signals can simultaneously enter the multiple rows of pixel units, which further results in the display panel displaying an abnormal picture in stripe pattern, that is, the picture shown in the display panel 401 is changed to the picture shown in the display panel 403, and the picture shown in the display panel 402 is changed to the picture shown in the display panel 404. Since the pixel unit displays the image after receiving the data voltage signal, the abnormal condition of the image displayed by the display panel changes along with the change of the data voltage signal.

As shown in fig. 5, when the voltage converting circuit 103 is accidentally abnormal, and the first analog GOA signal and the second analog GOA signal are not affected by the LC _ in signal and keep in phase, the first analog GOA signal and the second analog GOA signal are at high level at the same time.

Because the GOA unit requires to keep the first analog GOA signal and the second analog GOA signal in an inverted state during normal operation, the first analog GOA signal and the second analog GOA signal are continuously in the same phase to cause the timing sequence of the GOA unit to be disordered, so that the output current of the voltage conversion circuit 103 is increased, and the overcurrent protection is triggered when the output current is greater than the threshold value. The difference between the trigger time of the overcurrent protection and the time when the timing control circuit 102 outputs the P2P signal is T5, and when the trigger time of the overcurrent protection is after the timing control circuit 102 outputs the P2P signal, that is, the value of T5 is greater than 0, the display image of the display panel shown in fig. 4 is also abnormal.

In order to solve the problem of abnormal display pictures of a display panel, embodiments of the present invention provide a control circuit and a control method for a display panel, and a display device. First, a control circuit of a display panel according to an embodiment of the present invention will be described.

As shown in fig. 6, a control circuit of a display panel includes a power management circuit 101, a timing control circuit 102, a voltage conversion circuit 103, a source driving circuit 104, and a feedback circuit 601, wherein:

the power supply management circuit is respectively connected with the sequential control circuit, the voltage conversion circuit and the source driving circuit; the time sequence control circuit is respectively connected with the voltage conversion circuit and the source drive circuit; the voltage conversion circuit and the source drive circuit are respectively connected with a display panel; the feedback circuit is respectively connected with the time sequence control circuit and the voltage conversion circuit;

It can be seen that, in the control circuit provided in the embodiment of the present invention, the control circuit may include a power management circuit, a timing control circuit, a voltage conversion circuit, a source driving circuit, and a feedback circuit, where the power management circuit is connected to the timing control circuit, the voltage conversion circuit, and the source driving circuit respectively; the time sequence control circuit is respectively connected with the voltage conversion circuit and the source drive circuit; the voltage conversion circuit and the source drive circuit are respectively connected with the display panel; the feedback circuit is respectively connected with the time sequence control circuit and the voltage conversion circuit; the feedback circuit is used for generating a feedback signal according to the digital GOA signal output by the time sequence control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and outputting the feedback signal to the time sequence control circuit; and the time sequence control circuit is used for controlling the output of the digital GOA signal and the digital data signal according to the feedback signal. The feedback circuit can generate a feedback signal according to the digital GOA signal output by the sequential control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and output the feedback signal to the sequential control circuit, and then the sequential control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal. Therefore, when the voltage conversion circuit is in a protection state or is damaged to cause the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit to change, the time sequence control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal, and therefore the problem that the display picture of the display panel is abnormal is avoided.

When short circuit or time sequence disorder occurs inside a GOA unit of the display panel, when the circuit temperature exceeds a temperature threshold due to a high-temperature environment, two analog GOA signals output by the voltage conversion circuit are in phase, the voltage conversion circuit is damaged, and the like, the display screen of the display panel is abnormal.

When the voltage conversion circuit is in the above condition, the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit may be different from the normal operation state, and therefore, in order to monitor whether the above condition occurs, a feedback circuit may be provided.

The feedback circuit is respectively connected with the sequential control circuit and the voltage conversion circuit, so that the feedback circuit can monitor a digital GOA signal output by the sequential control circuit and a first analog GOA signal and a second analog GOA signal output by the voltage conversion circuit, and further can generate a feedback signal according to the digital GOA signal, the first analog GOA signal and the second analog GOA signal and output the feedback signal to the sequential control circuit.

Since the feedback signal is generated according to the digital GOA signal, the first analog GOA signal and the second analog GOA signal, the feedback signal can reflect the level states of the digital GOA signal, the first analog GOA signal and the second analog GOA signal. After receiving the feedback signal, the timing control circuit can control the output of the digital GOA signal and the digital data signal according to the level states of the digital GOA signal, the first analog GOA signal and the second analog GOA signal reflected by the feedback signal. Therefore, under the condition that the abnormal display picture of the display panel possibly occurs, the time sequence control circuit can change the output digital GOA signal and the digital data signal, and further the problem of the abnormal display picture of the display panel is avoided.

For example, the timing control circuit may stop outputting the digital GOA signal and adjust the digital data signal to make the output data be black screen picture data, so that the picture seen by the user is a full black picture, and an abnormal picture in a stripe pattern as shown in fig. 4 does not occur, so that the viewing experience of the user is better.

In this embodiment of the present invention, the feedback circuit may generate the feedback signal according to the digital GOA signal output by the timing control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and output the feedback signal to the timing control circuit, and then the timing control circuit may control the output of the digital GOA signal and the digital data signal according to the feedback signal. Thus, when the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit change due to the above-mentioned abnormal situation of the display screen of the display panel, the timing control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal, thereby avoiding the abnormal situation of the display screen of the display panel.

As an implementation manner of the embodiment of the present invention, as shown in fig. 7, the feedback circuit 601 may include a comparison circuit 701, a first in-phase flip-flop 702, and an edge flip-flop 703, where:

the input end of the comparison circuit 701 is connected with the output end of the voltage conversion circuit, the input end of the edge trigger 703 is connected with the output end of the timing control circuit, the input end of the first in-phase trigger 702 is respectively connected with the output end of the comparison circuit 701 and the output end of the edge trigger 703, and the output end of the first in-phase trigger 702 is connected with the timing control circuit;

the comparing circuit 701 is configured to generate a first level signal according to whether the first analog GOA signal and the second analog GOA signal output by the output end of the voltage converting circuit are in-phase, and output the first level signal to the input end of the first in-phase flip-flop 702;

the edge flip-flop 703 is configured to generate a second level signal according to a level change of the digital GOA signal output by the output end of the timing control circuit, and output the second level signal to the input end of the first non-inverting flip-flop 702;

the first non-inverting flip-flop 702 is configured to generate a feedback signal according to a level difference between the first level signal and the second level signal, and output the feedback signal to the timing control circuit.

When the control circuit is in a normal working state, the state of the LC _ in signal is a continuous output square wave signal, after the LC _ in signal changes from low to high for the first time, the first analog GOA signal and the second analog GOA signal can be in an inverted state, and then the first analog GOA signal and the second analog GOA signal are always in an inverted state. In the case where the display screen of the display panel may be abnormal, the voltage converting circuit stops outputting the voltage signal, and the first analog GOA signal and the second analog GOA signal gradually return to GND, or the first analog GOA signal and the second analog GOA signal are occasionally in phase, in which case the first analog GOA signal and the second analog GOA signal are both in phase.

Based on this, the feedback circuit 601 needs to be able to monitor the changes of the LC _ in signal, the first analog GOA signal and the second analog GOA signal. In one embodiment, the feedback circuit 601 may include a comparison circuit 701, a first in-phase flip-flop 702, and an edge flip-flop 703.

The comparing circuit 701 can output different level signals based on different level conditions of the two input signals, and thus can be used to monitor changes of the first analog GOA signal and the second analog GOA signal. Then, the input terminal of the comparing circuit 701 may be connected to the output terminal of the voltage converting circuit, so as to obtain the first analog GOA signal and the second analog GOA signal outputted by the output terminal of the voltage converting circuit. And generates a first level signal based on whether the first analog GOA signal and the second analog GOA signal are in phase.

The edge flip-flop 703 may output a level signal based on a level change of an input signal. Since the LC _ in signal is a square wave signal, there is an edge change, and then the edge flip-flop 703 can be used to monitor the state of the LC _ in signal. The input of edge flip-flop 703 may be connected to the output of the timing control circuit.

The first non-inverting flip-flop 702 may output a different level signal based on whether the levels of the two input signals are the same. The inputs of which may be connected to the output of the comparator circuit 701 and the output of the edge flip-flop 703, respectively. Thus, as long as one of the two level signals received by the input terminal of the first in-phase flip-flop 702 changes under the condition that the display screen of the display panel may be abnormal, the first in-phase flip-flop 702 may output a signal different from the level signal output by the control circuit in the normal operating state.

In order to enable the first in-phase flip-flop 702 to monitor the abnormal condition of the display screen of the display panel, the level of the second level signal output by the edge flip-flop 703 needs to be kept unchanged. In one embodiment, the edge flip-flop 703 may be a rising edge flip-flop, so that after the LC _ in signal first changes from low to high, the edge flip-flop 703 continuously outputs the second level signal with the same level.

The output terminal of the first in-phase flip-flop 702 is connected to the timing control circuit, so that the first in-phase flip-flop 702 can output a feedback signal to the timing control circuit after generating the feedback signal according to the level difference between the first level signal and the second level signal. The timing control circuit can control the output of the digital GOA signal and the digital data signal based on the feedback signal.

For example, the comparing circuit 701 may be configured to output a high level signal if the input signal is simultaneously greater than the threshold voltage or simultaneously less than the threshold voltage, otherwise output a low level signal, and then when the first analog GOA signal and the second analog GOA signal are in phase, the first level signal output by the comparing circuit 701 is a high level signal.

Therefore, in the embodiment of the invention, the input end of the comparison circuit can be connected with the output end of the voltage conversion circuit, the input end of the edge trigger is connected with the output end of the time sequence control circuit, the input end of the first in-phase trigger is respectively connected with the output end of the comparison circuit and the output end of the edge trigger, and the output end of the first in-phase trigger is connected with the time sequence control circuit; the comparison circuit is used for generating a first level signal according to whether the first analog GOA signal and the second analog GOA signal output by the output end of the voltage conversion circuit are in phase or not and outputting the first level signal to the input end of the first in-phase trigger; the edge trigger is used for generating a second level signal according to the level change of the digital GOA signal output by the output end of the time sequence control circuit and outputting the second level signal to the input end of the first same-phase trigger; and the first same-phase trigger is used for generating a feedback signal according to the level difference between the first level signal and the second level signal and outputting the feedback signal to the time sequence control circuit. In the above situation, when the display image of the display panel may be abnormal, the first analog GOA signal and the second analog GOA signal are in phase from the inverse phase during normal operation, and the comparing circuit may generate the first level signal according to whether the first analog GOA signal and the second analog GOA signal are in phase. Since the LC _ in signal is a square wave signal and there is an edge variation, the edge flip-flop may output a second level signal to monitor the state of the LC _ in signal. Under the condition that the display picture of the display panel is possibly abnormal, the level signals output by the first level signal and the second level signal are in phase, so that the first in-phase trigger can generate a feedback signal according to the first level signal and the second level signal and output the feedback signal to the time sequence control circuit, and the problem that the display picture of the display panel is abnormal is avoided.

As an implementation manner of the embodiment of the present invention, as shown in fig. 8, the comparison circuit 701 may include a first comparator 801, a second comparator 802, and a second non-inverting flip-flop 803, where:

an input end of the first comparator 801 is connected to a first analog GOA signal output end of the voltage conversion circuit, an input end of the second comparator 802 is connected to a second analog GOA signal output end of the voltage conversion circuit, an input end of the second in-phase flip-flop 803 is respectively connected to an output end of the first comparator 801 and an output end of the second comparator 802, and an output end of the second in-phase flip-flop 803 is connected to an input end of the first in-phase flip-flop;

the first comparator 801 is configured to generate a third level signal according to a magnitude relationship between the first analog GOA signal and a preset threshold, and output the third level signal to an input end of the second in-phase flip-flop 803;

the second comparator 802 is configured to generate a fourth level signal according to a magnitude relationship between the second analog GOA signal and the preset threshold, and output the fourth level signal to an input end of the second in-phase flip-flop 803;

the second in-phase flip-flop 803 is configured to generate a first level signal according to a level difference between the third level signal and the fourth level signal, and output the first level signal to an input terminal of the first in-phase flip-flop.

In the above situation, which may cause the display panel to display an abnormal picture, the first analog GOA signal and the second analog GOA signal are in phase, so the comparing circuit 701 may monitor whether the first analog GOA signal and the second analog GOA signal are in phase based on the level difference therebetween. Specifically, the comparison circuit 701 may include a first comparator 801, a second comparator 802, and a second in-phase flip-flop 803.

Under the condition that the control circuit works normally, the first analog GOA signal and the second analog GOA signal are in an inverted state, and the first analog GOA signal and the second analog GOA signal are not larger than a preset threshold value or smaller than the preset threshold value at the same time. In the above situation, which may cause an abnormal display frame of the display panel, the first analog GOA signal and the second analog GOA signal are in phase, and both of them may be greater than the preset threshold or smaller than the preset threshold.

Based on this, the first analog GOA signal and the second analog GOA signal can be monitored based on the first comparator 801 and the second comparator 802, respectively, and the preset threshold of the first comparator 801 and the second comparator 802 can be the same and is a value between the maximum value and the minimum value of the first analog GOA signal and the second analog GOA signal. Since the first analog GOA signal and the second analog GOA signal may return to the GND level if the voltage converting circuit enters the protection state or is damaged under the condition that the display screen of the display panel may be abnormal, the predetermined threshold may not be 0.

For example, the first comparator 801 and the second comparator 802 may be set such that if the input signal is greater than a preset threshold, the third level signal generated by the first comparator 801 and the fourth level signal generated by the second comparator 802 are high level signals, otherwise, the third level signal generated by the first comparator 801 and the fourth level signal generated by the second comparator 802 are low level signals. The second in-phase flip-flop 803 may be set to generate the first level signal as a high level signal when the input signal is both a high level signal or both low level signals, otherwise, the generated first level signal is a low level signal.

Then, if the control circuit is in a normal operating state, the first analog GOA signal and the second analog GOA signal are inverted, and the magnitude relationship between the two signals and the preset threshold value is that one signal is larger than the preset threshold value, and the other signal is smaller than the preset threshold value. Accordingly, one of the third level signal and the fourth level signal is a high level signal, and the other is a low level signal. After the third level signal and the fourth level signal are input into the second in-phase flip-flop 803, the first level signal generated by the second in-phase flip-flop 803 is a low level signal, that is, the first analog GOA signal and the second analog GOA signal are in opposite phases, thereby obtaining that the control circuit is in a normal operating state.

Under the condition that the display picture of the display panel is possibly abnormal, the first analog GOA signal and the second analog GOA signal are in the same phase, and the magnitude relation between the first analog GOA signal and the second analog GOA signal and the preset threshold is larger than the preset threshold or smaller than the preset threshold at the same time. Accordingly, the third level signal and the fourth level signal are both a high level signal or a low level signal. After the third level signal and the fourth level signal are input into the second in-phase flip-flop 803, the first level signal generated by the second in-phase flip-flop 803 is a high level signal, that is, the first analog GOA signal and the second analog GOA signal are in phase, which may cause an abnormal display image of the display panel.

In the embodiment of the present invention, an input end of a first comparator is connected to a first analog GOA signal output end of a voltage conversion circuit, an input end of a second comparator is connected to a second analog GOA signal output end of the voltage conversion circuit, an input end of a second in-phase flip-flop is connected to an output end of the first comparator and an output end of the second comparator, respectively, and an output end of the second in-phase flip-flop is connected to an input end of the first in-phase flip-flop; the first comparator is used for generating a third level signal according to the magnitude relation between the first analog GOA signal and a preset threshold value and outputting the third level signal to the input end of the second in-phase trigger; the second comparator is used for generating a fourth level signal according to the magnitude relation between the second analog GOA signal and a preset threshold value and outputting the fourth level signal to the input end of the second in-phase trigger; and the second in-phase trigger is used for generating a first level signal according to the level difference between the third level signal and the fourth level signal and outputting the first level signal to the input end of the first in-phase trigger. Under the condition that the display picture of the display panel is abnormal, the first analog GOA signal and the second analog GOA signal are in phase, so that the first analog GOA signal and the second analog GOA signal can be compared with a preset threshold value respectively based on the first comparator and the second comparator, a third level signal generated by the first comparator and a fourth level signal generated by the second comparator are input into the second in-phase trigger, the second in-phase trigger can generate a first level signal according to the level difference between the third level signal and the fourth level signal, and further judge whether the first analog GOA signal and the second analog GOA signal are in phase, so that the level difference between the first analog GOA signal and the second analog GOA signal can be accurately monitored, and the display picture abnormality of the display panel can be avoided.

As an implementation manner of the embodiment of the present invention, the time point when the edge flip-flop outputs the second level signal to the input terminal of the first non-inverting flip-flop is later than the time point when the level of the digital GOA signal changes;

the first time difference is a difference between a time point when the edge flip-flop outputs the second level signal to the input terminal of the first in-phase flip-flop and a time point when the level of the digital GOA signal changes, and the second time difference is a difference between a time point when the second in-phase flip-flop outputs the first level signal to the input terminal of the first in-phase flip-flop and a time point when the third level signal and the fourth level signal are generated. As shown in fig. 9, which is a timing diagram corresponding to the control circuit provided by the present invention in a normal operating state, the edge flip-flop may be configured to delay triggering, i.e., the first time difference is greater than 0. The first time difference is T6 in the figure.

For example, the edge flip-flop is a rising edge flip-flop, and the second level signal generated by the edge flip-flop is a high level signal. When the LC _ in signal is changed from a digital low-level signal to a digital high-level signal for the first time, the second level signal generated by the edge trigger is a high-level signal, and the level of the second level signal does not change along with the change of the LC _ in signal from a digital high-level signal to a digital low-level signal. When the LC _ in signal changes from the digital low level signal to the digital high level signal again, the second level signal still keeps the high level signal.

The time point when the second in-phase trigger outputs the first level signal to the input end of the first in-phase trigger is later than the time point when the third level signal and the fourth level signal are generated, namely the second time difference is larger than 0. The second time difference, i.e., T7 in the figure, and the time point when the first analog GOA signal and the second analog GOA signal change may be regarded as the time point when the third level signal and the fourth level signal are generated.

For example, when the input end of the second in-phase flip-flop is in-phase, the output first level signal is a high level signal, and when the output of the first comparator and the output of the second comparator are both high level signals or both low level signals, the output first level signal of the second in-phase flip-flop is a high level signal, otherwise, the output low level signal is output.

If the first time difference is smaller than the second time difference, the second in-phase flip-flop outputs the second level signal to the input end of the first in-phase flip-flop already when the second in-phase flip-flop outputs the first level signal under the normal working state of the circuit. In this way, the first time difference is greater than the second time difference in order to avoid that the first level signal and the second level signal in the normal operating state of the circuit are simultaneously identified as the feedback signal corresponding to the protection state of the voltage conversion circuit or the trigger protection state of the failed circuit in the normal operating state of the circuit.

It can be seen that, in the embodiment of the present invention, the time point when the edge flip-flop outputs the second level signal to the input terminal of the first in-phase flip-flop is later than the time point when the level of the digital GOA signal changes; the second in-phase flip-flop is configured to output the first level signal to the input terminal of the first in-phase flip-flop at a time point later than a time point at which the third level signal and the fourth level signal are generated, and the first time difference is greater than the second time difference; the first time difference is a difference value between a time point when the edge flip-flop outputs the second level signal to the input end of the first in-phase flip-flop and a time point when the level of the digital GOA signal changes, and the second time difference is a difference value between a time point when the second in-phase flip-flop outputs the first level signal to the input end of the first in-phase flip-flop and a time point when the third level signal and the fourth level signal are generated. Because the first time difference is larger than the second time difference, the edge trigger does not output the second level signal to the input end of the first in-phase trigger when the second in-phase trigger outputs the first level signal in the normal working state of the circuit, and thus, the first level signal and the second level signal are not high level signals or low level signals simultaneously, and the feedback circuit can accurately feed back whether the state of the voltage conversion circuit is the normal working state or the state triggered by the protection state.

Fig. 9 shows a timing chart corresponding to the normal operation of the control circuit provided by the present invention. When the circuit is in a power-on stage, the LC _1 signal and the LC _2 signal change to be smaller than a preset threshold value or larger than the preset threshold value simultaneously along with the VGH signal, and the second in-phase trigger outputs a high-level signal.

Points a, B, and C in fig. 9 are level changes at points a, B, and C in fig. 8. The LC _ in signal is output as a low level signal at the point a, so the LC _ in signal outputs a low level at the point C, and at this time, the timing control circuit does not perform special control on the output digital GOA signal and the digital data signal.

When the LC _ in signal is changed from a digital low-level signal to a digital high-level signal for the first time, the LC _1 signal is a high-level signal, the LC _2 signal is a low-level signal, the output of the first comparator is a high-level signal, the output of the second comparator is a low-level signal, and the output of the second in-phase trigger is changed to a low-level signal, namely a B-point signal. Meanwhile, the a point signal becomes a high level signal because the LC _ in signal changes from a digital low level signal to a digital high level signal. Since T6 is greater than T7, the signal at point B becomes a low level signal before the signal at point a becomes a high level signal, and the signal at point C continues to be a low level signal.

In the subsequent period, the LC _1 signal and the LC _2 signal are always kept in an inverted state, the B point signal continuously outputs a low level signal, and the A point signal is in a high level signal and is not changed, so that the C point also continuously outputs a low level signal, namely the normal operation of the display panel is not influenced.

Fig. 10 shows a timing chart corresponding to the voltage conversion circuit being in a protection state or the voltage conversion circuit being damaged. When the overcurrent protection occurs, the voltage conversion circuit stops outputting the analog GOA signal, the LC _1 signal and the LC _2 signal are changed into GND signals, namely the first comparator and the second comparator both output low-level signals, and the second in-phase trigger outputs high-level signals, namely the B point signal is a high-level signal. The output of the first non-inverting flip-flop is a high level signal, i.e. the signal at point C is a high level signal. The time sequence control circuit stops outputting the LC _ in signal and adjusts the output content of the P2P signal into a full-screen black picture.

Fig. 11 is a schematic diagram of a display screen of the display panel when the protection state of the voltage converting circuit is triggered. The display screen of the display panel may be shown by a display panel 1101, a display panel 1102, a display panel 1103, and a display panel 1104. The display panel 1101 and the display panel 1102 are in a normal state, and the display content of the display panel is switched from "HELLO" shown by the display panel 1101 to "ABCD" shown by the display panel 1102. If the protection state is triggered, the analog GOA signal stops outputting, which may cause synchronous start of multiple rows of pixels, that is, synchronous start of pixel units in the same row as the pixel unit corresponding to "HELLO" shown in the display panel 1101, and the data voltage signal may enter the multiple rows of pixel units at the same time, which may cause the display panel to display an abnormal picture in a stripe pattern, that is, the picture shown in the display panel 1101 is changed to the picture shown in the display panel 1103. Since the feedback circuit sends the feedback signal to the timing control circuit, and the timing control circuit controls the digital data signal and the analog GOA signal according to the feedback signal, the picture shown by the display panel 1102 becomes the picture shown by the display panel 1104, and a black screen picture can be output when the display panel outputs an abnormal picture.

Fig. 12 is a timing chart of when the voltage conversion circuit outputs the LC _1 signal and the LC _2 signal in the same phase. For example, when the LC _ in signal is first changed from a digital low level signal to a digital high level signal, the LC _1 signal and the LC _2 signal are not inverted, the signal at point a is changed to a high level signal, the signal at point B is also a high level signal, and the signal at point C is also a high level signal. Wherein, the C point signal is the feedback signal.

In this way, the feedback circuit may send the feedback signal to the timing control circuit before the LC _1 signal is in phase with the LC _2 signal and the voltage conversion circuit does not trigger the protection state, the timing control circuit stops outputting the LC _ in signal, the LC _ in signal changes from a digital high level signal to a digital low level signal, both the LC _1 signal and the LC _2 signal change to low level signals, and the B point signal keeps the high level signal unchanged. Because T6 is less than T2, no P2P signal is output at this time, the time sequence control circuit keeps on keeping the non-output state, so the display panel is always in the non-display state;

compared with the prior art, the scheme provided by the embodiment of the application can enable the display panel to display a black screen picture before the protection state of the voltage conversion circuit is triggered when the LC _1 signal and the LC _2 signal are in phase occasionally, and the picture abnormity does not occur yet.

As an implementation manner of the embodiment of the present invention, as shown in fig. 13, the control circuit may further include a system terminal 1301, where the system terminal 1301 is connected to the feedback circuit 601, the power management circuit 101, and the timing control circuit 102 respectively;

the feedback circuit 601 is further configured to output the feedback signal to the system terminal 1301;

the system terminal 1301 is configured to turn off the backlight of the display panel according to the feedback signal.

The feedback circuit 601 may also send a feedback signal to the system side 1301. In this way, in the case that the above-mentioned abnormality may occur on the display screen of the display panel, the feedback circuit 601 may send the feedback signal to the timing control circuit 102 and the system section 1301, the timing control circuit 102 may control the output of the digital GOA signal and the digital data signal according to the feedback signal, and the system terminal 1301 may turn off the backlight of the display panel according to the feedback signal.

For example, if the system side 1301 is set to turn off the backlight of the display panel after receiving the feedback signal of high level, when the feedback signal received by the system side 1301 is a signal of high level, the system side 1301 may perform the operation of turning off the backlight of the display panel.

Obviously, in the embodiment of the present invention, the control circuit may further include a system end, and the system end is connected to the feedback circuit and the power management circuit, respectively; the feedback circuit can also be used for outputting a feedback signal to the system end; and the system end is used for closing the backlight of the display panel according to the feedback signal. Therefore, the backlight of the display panel can be turned off on the basis that the time sequence control circuit controls the output of the digital GOA signal and the digital data signal to enable the display panel to display a black screen picture, and the user experience of a user when the display panel displays an abnormal picture is further improved.

As an implementation manner of the embodiment of the present invention, as shown in fig. 14, the control circuit may further include a system terminal 1301, where the system terminal 1301 is connected to the timing control circuit 102 and the power management circuit 101 respectively;

the timing control circuit 102 is further configured to output the feedback signal to the system terminal 1301;

After receiving the feedback signal, the timing control Circuit 102 may output the feedback signal to the system side 1301 in an I2C (Inter-Integrated Circuit, bi-directional two-wire synchronous serial bus) communication manner, so that the system side 1301 closes the backlight of the display panel according to the feedback signal.

Therefore, in the embodiment of the present invention, the control circuit may further include a system end, and the system end is respectively connected to the timing control circuit and the power management circuit; the time sequence control circuit is also used for outputting a feedback signal to a system end; and the system end is used for closing the backlight of the display panel according to the feedback signal. The time sequence control circuit can output the feedback signal output by the feedback circuit to the system end, so that wiring between the feedback circuit and the system end is omitted, and wiring of the control circuit can be reduced while the problem that a display picture is abnormal on the display panel is avoided.

As an implementation manner of the embodiment of the present invention, the feedback circuit may be integrated inside the voltage conversion circuit.

The feedback circuit can be integrated into the voltage conversion circuit and is integrated.

Therefore, in the embodiment of the invention, the feedback circuit can be integrated inside the voltage conversion circuit. Because the feedback circuit is integrated into the voltage conversion circuit, the circuit board composing space of the control circuit can be reduced while the problem that the display panel has abnormal display pictures is avoided.

Corresponding to the control circuit of the display panel, an embodiment of the present invention further provides a control method of the display panel, and the following describes the control method of the display panel provided by the embodiment of the present invention.

As shown in fig. 15, a control method of a display panel is applied to a timing control circuit in any one of the above control circuits, and the method includes:

s1501, acquiring a feedback signal output by the feedback circuit;

the feedback signal may identify whether the voltage conversion circuit triggers a protection state, whether the voltage conversion circuit is damaged, or whether the first analog GOA signal and the second analog GOA signal are in phase, so that the timing control circuit may obtain the feedback signal output by the feedback circuit.

S1502, controlling the output of the digital GOA signal and the digital data signal according to the feedback signal.

The feedback circuit may send the feedback signal to the timing control circuit, and the timing control circuit controls the output of the digital GOA signal and the digital data signal according to the feedback signal.

Therefore, in the control method provided by the embodiment of the invention, the timing control circuit can obtain the feedback signal output by the feedback circuit; and controlling the output of the digital GOA signal and the digital data signal according to the feedback signal. The feedback circuit can generate a feedback signal according to the digital GOA signal output by the sequential control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and output the feedback signal to the sequential control circuit, and then the sequential control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal. Therefore, when the voltage conversion circuit triggers a protection state, is damaged or the first analog GOA signal and the second analog GOA signal are in phase, and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit are changed, the time sequence control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal, so that the problem of abnormal display pictures of the display panel is avoided.

As an implementation manner of the embodiment of the present invention, the step of controlling the output of the digital GOA signal and the digital data signal according to the feedback signal may include:

stopping outputting the digital GOA signal;

because the first analog GOA signal and the second analog GOA signal are generated based on the digital GOA signal, the VGH signal, and the VGL signal, the output of the digital GOA signal can be stopped, and the output of the first analog GOA signal and the second analog GOA signal can be stopped, so as to prevent the display panel from displaying abnormal pictures.

when the digital data signal is in an output state, the time sequence control circuit can adjust the digital data signal according to the feedback signal, so that the output data is black screen image data.

When the digital data signal is in a non-output state, the timing control circuit can keep the digital data signal in the non-output state because the digital data signal is not output.

Therefore, in the embodiment of the invention, the time sequence control circuit can stop outputting the digital GOA signal; if the digital data signal is in an output state, adjusting the digital data signal to enable the output data to be black screen image data; and if the digital data signal is in a non-output state, keeping the digital data signal in the non-output state. If the digital GOA signal and the digital data signal are in the output state when the voltage conversion circuit triggers the protection state, the damage occurs or the first analog GOA signal and the second analog GOA signal are in the same phase, the display panel will display an abnormal picture. Therefore, the time sequence control circuit can stop outputting the GOA signal according to the feedback signal, make the output data be the black screen picture data when the digital data signal is in the output state, and keep the digital data signal in the non-output state when the digital data signal is in the non-output state, thereby avoiding the problem that the display panel displays the black screen picture.

An embodiment of the present invention further provides a display device, as shown in fig. 16, including:

a control circuit 1601 for controlling the display panel to display pictures according to the digital analog signal and the data voltage signal;

the display panel 1602 is used for receiving the signal sent by the control circuit and displaying a picture.

The control circuit 1601 may be the control circuit described in any of the above embodiments.

It can be seen that, in the display device provided in the embodiment of the present invention, the feedback circuit may generate the feedback signal according to the digital GOA signal output by the timing control circuit and the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit, and output the feedback signal to the timing control circuit, and then the timing control circuit may control the output of the digital GOA signal and the digital data signal according to the feedback signal. Therefore, when the voltage conversion circuit is in a protection state, the two analog GOA signals output by the voltage conversion circuit are accidentally in phase, or the voltage conversion circuit is damaged, so that the first analog GOA signal and the second analog GOA signal output by the voltage conversion circuit are changed, the time sequence control circuit can control the output of the digital GOA signal and the digital data signal according to the feedback signal, and the problem of abnormal display pictures of the display panel is avoided.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the system embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.

Claims

1. A control circuit of a display panel is characterized in that the control circuit comprises a power management circuit, a time sequence control circuit, a voltage conversion circuit, a source driving circuit and a feedback circuit, wherein:

the power management circuit is respectively connected with the sequential control circuit, the voltage conversion circuit and the source driving circuit; the time sequence control circuit is respectively connected with the voltage conversion circuit and the source drive circuit; the voltage conversion circuit and the source drive circuit are respectively connected with the display panel; the feedback circuit is respectively connected with the time sequence control circuit and the voltage conversion circuit;

2. The control circuit of claim 1, wherein the feedback circuit comprises a comparison circuit, a first non-inverting flip-flop, and an edge flip-flop, wherein:

the comparison circuit is used for generating a first level signal according to whether a first analog GOA signal and a second analog GOA signal output by the output end of the voltage conversion circuit are in phase or not, and outputting the first level signal to the input end of the first in-phase trigger;

3. The control circuit of claim 2, wherein the comparison circuit comprises a first comparator, a second comparator, and a second non-inverting flip-flop, wherein:

the first comparator is used for generating a third level signal according to the magnitude relation between the first analog GOA signal and a preset threshold value and outputting the third level signal to the input end of the second in-phase trigger;

the second in-phase flip-flop is configured to generate a first level signal according to a level difference between the third level signal and the fourth level signal, and output the first level signal to an input terminal of the first in-phase flip-flop.

4. The control circuit of claim 3, wherein the edge flip-flop is configured to output the second level signal to the input terminal of the first non-inverting flip-flop at a time point later than a time point at which the level of the digital GOA signal changes;

5. The control circuit according to any one of claims 1-3, further comprising a system terminal, the system terminal being connected to the feedback circuit and the power management circuit, respectively;

6. The control circuit according to any one of claims 1-3, wherein the control circuit further comprises a system terminal, the system terminal is connected to the timing control circuit and the power management circuit, respectively;

7. The control circuit of any of claims 1-3, wherein the feedback circuit is integrated within the voltage conversion circuit.

8. A control method for a display panel, applied to a timing control circuit in the control circuit of any one of claims 1 to 7, the method comprising:

acquiring a feedback signal output by the feedback circuit;

9. The method of claim 8, wherein said controlling the output of the digital GOA signal and the digital data signal according to the feedback signal comprises:

stopping outputting the digital GOA signal;

10. A display device characterized in that the display device comprises the control circuit of any one of claims 1 to 7 and a display panel.