KR20150002036A - Power supplying apparatus and display apparatus including the same - Google Patents

Abstract

The present invention provides a power supply apparatus and a display apparatus using the same, capable of stably performing an operation even though input power is low. The power supply apparatus according to the present invention includes a DC-DC converter which converts the input power into a DC voltage according to the switching of a switching device, a low voltage locking control unit which generates a low voltage locking signal according to the voltage drop of the input power, and a switching control unit which controls the switching of the switching device based on the low voltage locking signal. The low voltage locking control unit generates the low voltage locking signal of a first logic state to compulsorily turn off the switching device for preset delay time when the input power is reduced to a first reference low voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a power supply apparatus and a display apparatus including the power supply apparatus.

The present invention relates to a power supply apparatus and a display apparatus including the power supply apparatus.

Generally, the power supply device rectifies and rectifies a DC voltage using an AC voltage, or boosts or downsteps a DC voltage to a required voltage to generate a DC voltage necessary for various devices (e.g., a display device, a light emitting diode) to provide.

1 is a view for explaining a conventional power supply apparatus.

Referring to FIG. 1, a conventional power supply includes a DC-DC converter 10, a low voltage detection unit 20, and a switching control unit 30.

The DC-DC converter 10 converts an input voltage Vin into a DC voltage and outputs the DC voltage. The DC-DC converter 10 includes an inductor L, a diode D, a switching element Psw, and a capacitor C. The DC-DC converter 10 converts the input power source Vin into a DC voltage in accordance with the switching of the switching element Psw in response to the pulse width modulation signal S _PWM supplied from the switching controller 30. That is, when the switching element Psw is turned on, a current flows in the inductor L by the input power supply Vin, and energy is accumulated. When the switching element Psw is turned off, the energy stored in the inductor L is added to the input power supply Vin, passes through the diode D, and is smoothed to a DC voltage by the capacitor C, And output as the voltage Vout.

When the voltage of the input power source Vin is lower than the set voltage, the low voltage detection unit 20 detects an under voltage lock for forcibly turning off the power supply unit to increase the stability of the integrated circuit (IC) Out signal UVLO to the switching control unit 30. [

Specifically, the low voltage detection unit 20 divides the voltage of the input power supply Vin, compares the voltage-divided input voltage with a predetermined reference low voltage using a comparator (not shown) having a constant hysteresis value, Generates an under voltage lockout signal (UVLO) according to the result and supplies it to the switching control section (30). 2, when the voltage-divided input voltage reaches a set reference low voltage Vref, the low-voltage detection unit 20 detects the switching element Psw of the DC-DC converter 10, Voltage lock signal (UVLO) in a high state for turning off the switch SW1.

The switching control unit 30 generates a pulse width modulation signal S _PWM by feedback of the output voltage Vout of the DC-DC converter 10 and outputs the pulse width modulation signal S _PWM from the low voltage detection unit 20 to the low- The output voltage Vout of the DC-DC converter 10 is constantly controlled by the pulse width modulation signal S _PWM only when the low voltage lock signal UVLO is supplied.

In such a conventional power supply device, there is a problem that the DC-DC converter 10 is repeatedly turned on and off when the voltage-divided input voltage reaches the set reference low voltage Vref.

2, when the voltage-divided input voltage reaches a set reference low voltage Vref, a low voltage lock signal UVLO in a high state is generated in the low voltage detector 20, The switching element Psw of the converter 10 is turned off, and the operation of the DC-DC converter 10 is thereby stopped. At this time, when the operation of the DC-DC converter 10 is stopped, the input power Vin is raised by the energy stored in the inductor L and the input power supply (Vin) line. When the voltage of the rising input power Vin becomes higher than the hysteresis value of the low voltage detector 20, a low voltage lock signal UVLO in a low state is generated in the low voltage detector 20, The switching element Psw of the converter 10 is turned on and the input power supply Vin is supplied to the DC-DC converter 10 so that the voltage of the input power supply Vin is lowered to the set reference low voltage Vref. By repeating the above process, the DC-DC converter 10 is repeatedly turned on and off.

Therefore, in a display device using a conventional power supply device as a power supply device, the on / off state of the DC-DC converter 10 generated when the input voltage reaches the set reference low voltage Vref ) Flicker phenomenon occurs due to repetition phenomenon.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a power supply apparatus which stably operates even when the input power is low, and a display apparatus using the same.

According to an aspect of the present invention, there is provided a power supply apparatus including: a DC-DC converter converting an input power to a DC voltage in response to switching of a switching device; A low voltage lock control unit for generating a low voltage lock signal according to a voltage drop of the input power supply; And a switching control unit for controlling switching of the switching device based on the low voltage lock signal, wherein the low voltage lock control unit forcibly turns off the switching device for a predetermined delay time when the input power source is lowered to the first reference low voltage, And generates a low-voltage lock signal of a first logic state for turning off the power source.

Wherein the low voltage lock control unit generates a low voltage lock signal in the first logic state when the input power source is lower than a second reference low voltage lower than the first reference low voltage, And generates a second logic low voltage lock signal for turning on the switching element when the voltage is not lower than the second reference low voltage.

According to an aspect of the present invention, there is provided a display device including: a display panel including pixels formed in pixel regions defined by intersections of a gate line and a data line; A panel driver for driving the pixel; And a power supply unit for converting the input power to a DC voltage and supplying the DC power to the panel driving unit, and the power supply unit may include the power supply unit.

Wherein the panel driving unit comprises: a reference gamma voltage generator for generating a plurality of reference gamma voltages; A data driving circuit for converting pixel data inputted using the plurality of reference gamma voltages into data voltages and supplying the data voltages to the data lines; A gate driving circuit for supplying a gate signal to the gate line; And a timing control unit for controlling driving of the data driving circuit unit and the gate driving circuit unit and supplying pixel data to the data driving circuit unit, wherein the power supply unit supplies the reference gamma voltage generating unit, the data driving circuit unit, And a DC voltage required for driving at least one of the driving circuit section and the timing control section is generated.

The display device includes a backlight unit for emitting light to the display panel; And a backlight driving unit driving the backlight unit, wherein the power supply unit further generates a DC voltage required for driving at least one of the backlight unit and the backlight driver.

According to the solution of the above-mentioned problems, the present invention has the following effects.

First, when the voltage of the input power source is lowered to the first reference low voltage, the switching element of the DC-DC converter is turned off during the set delay time, and the DC- The switching element of the DC converter is turned off, so that even if the input power source is lowered, there is an effect that it operates stably without causing malfunction.

Second, since the power supply device including the power supply device that operates stably even when the input power is decreased, the on / off repetition phenomenon of the DC-DC converter generated when the input power reaches the set reference low voltage It is possible to prevent the flicker phenomenon.

1 is a view for explaining a conventional power supply apparatus.
2 is a waveform diagram for explaining a low voltage locking operation of a conventional power supply apparatus.
3 is a view for explaining a power supply apparatus according to an embodiment of the present invention.
4 is a circuit diagram for explaining the low voltage lock control unit shown in FIG.
5 and 6 are waveform diagrams for explaining the operation waveform of the power supply device according to the embodiment of the present invention.
7 is a simulation waveform diagram of a power supply apparatus according to an embodiment of the present invention.
8 is a view for explaining a display device according to an embodiment of the present invention.

The meaning of the terms described herein should be understood as follows.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms.

It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one.

Hereinafter, preferred embodiments of a power supply apparatus and a display apparatus including the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a view for explaining a power supply apparatus according to an embodiment of the present invention, and FIG. 4 is a circuit diagram for explaining a low voltage lock control unit shown in FIG.

Referring to FIGS. 3 and 4, a power supply 100 according to an embodiment of the present invention includes a DC-DC converter 110, a low voltage lock controller 120, and a switching controller 130.

The DC-DC converter 110 converts an input power supply Vin into a DC voltage and outputs the DC voltage. The DC-DC converter 110 may include an inductor L, a diode D, a switching element Psw, and a capacitor C. The DC-DC converter 110 converts the input power source Vin into a DC voltage according to the switching of the switching element Psw according to the pulse width modulation signal S _PWM supplied from the switching controller 130 . That is, when the switching element Psw is turned on, the inductor L is accumulated by the input power supply Vin. When the switching element Psw is turned off, the energy stored in the inductor L is added to the input power supply Vin, passes through the diode D, and is smoothed to a DC voltage by the capacitor C, And output as the voltage Vout.

When the voltage of the input power supply Vin is lower than the set voltage, the low voltage lock control unit 120 controls the low voltage lock control unit 120 to turn off the power supply unit for the purpose of forcibly turning off the power supply unit to increase the stability of the integrated circuit (IC) Lock Out (UVLO) signal to the switching control unit 30. That is, when the voltage of the input power source Vin is lowered to the first reference low voltage Vref1, the low voltage lock control unit 120 turns off the first switching element Psw for a predetermined delay time, To generate a logic low voltage lock signal (UVLO). During the delay time, when the input voltage Vin is lowered to a second reference lower voltage Vref2 or lower than the first reference low voltage Vref1, the low voltage lock control unit 120 turns off the low voltage lock of the first logic state Supplies a signal UVLO to the switching controller 130 and turns on the switching element Psw when the voltage of the input power supply Vin is not lowered below the second reference low voltage Vref2 Voltage lock signal UVLO in the second logic state for supplying the low-voltage lock signal UVLO to the switching control unit 130. The low voltage lock control unit 120 is reset when the input voltage Vin rises to the reference reset voltage Ref_Reset higher than the first reference low voltage Vref1.

Specifically, the low voltage lock control unit 120 according to the present invention includes a first low voltage detection unit 121, a second low voltage detection unit 123, a delay circuit unit 125, and a low voltage lock signal generation unit 127 .

The first low voltage detection unit 121 generates a first low voltage detection signal LDS1 by comparing the voltage of the input power supply Vin with the set first reference low voltage Vref1 and outputs the generated first low voltage detection signal LDS1, To the low voltage lock signal generating unit 127. [ To this end, the first low voltage detector 121 according to one embodiment may include a first comparator 121a and a first inverter 121b.

The first comparator 121a is configured to have a constant hysteresis value and compares the voltage of the input power source Vin with the first reference lower voltage Vref1 to determine a first logic state L or a second logic state L And generates and outputs the first comparison signal CS1 in the logic state H. For example, the first comparator 121a compares the first comparison signal CS1 of the first logic state L when the voltage of the input power source Vin is equal to or less than the set first reference lower voltage Vref1 And outputs it. The first comparator 121a generates the first comparison signal CS1 of the second logic state H when the voltage of the input power source Vin is higher than the set first reference lower voltage Vref1, do. Here, the input power Vin input to the first comparator 121a may be a voltage-divided voltage by a voltage divider circuit (not shown).

The first inverter 121b inverts the logic state of the first comparison signal CS1 input from the first comparator 121a to generate the first low voltage detection signal LDS1.

The second low voltage detection unit 123 compares the voltage of the input power source Vin with the second reference low voltage Vref2 set to a voltage lower than the second reference low voltage Vref1 and outputs the second low voltage detection signal LDS2, And supplies the generated second low voltage detection signal LDS2 to the low voltage lock signal generation unit 127. [ For this, the second low voltage detector 123 according to one embodiment may include a second comparator 123a and a second inverter 123b.

The second comparator 123a compares the voltage of the input power supply Vin with the second reference lower voltage Vref2 to generate a second comparison signal of the first logic state L or the second logic state H CS2). For example, the second comparator 123a may compare the second comparison signal CS2 of the first logic state L when the voltage of the input power source Vin is equal to or smaller than the set second reference low voltage Vref2 And outputs it. The second comparator 123a generates the second comparison signal CS2 of the second logic state H when the voltage of the input power supply Vin is higher than the set second reference lower voltage Vref2, do. Here, the input power Vin input to the second comparator 123a may be a voltage-divided voltage by a voltage divider circuit (not shown).

The second inverter 123b inverts the logic state of the second comparison signal CS2 input from the second comparator 123a to generate the second low voltage detection signal LDS2.

The delay circuit unit 125 generates a delay signal DS having a pulse width set in accordance with the first low voltage detection signal LDS1 of the second logic state H output from the first low voltage detection unit 121 Voltage lock signal generating unit 127. The low- The delay circuit unit 125 is reset according to the first comparison signal CS1 of the second logic state H output from the first comparator 121a of the first low voltage detection unit 121. [ The delay circuit 125 includes a first transistor T1, a resistor Rd, a capacitor Cd, a second transistor T2, a third comparator 125a, and a third inverter 125b. And the like.

The first transistor T1 is turned on only when the first low voltage detection signal LDS1 of the second logic state H is supplied from the first low voltage detection unit 121 to the driving voltage Vcc through the resistor (Rd). The first transistor T1 includes a gate terminal connected to an output terminal of the first low voltage detector 121, a source terminal connected to the driving voltage Vdd line, And a drain terminal connected at one end.

The resistor Rd is connected between the drain terminal of the first transistor T1 and the common node Nc. The capacitor Cd is connected between the common node Nc and the base power supply. The resistor Rd and the capacitor Cd charge the driving voltage Vcc supplied from the driving voltage Vcc line in accordance with the switching of the first transistor T1 based on the RC time constant.

The second transistor T2 is turned on according to the first comparison signal CS1 of the second logic state H output from the first comparator 121a of the first low voltage detector 121, Cd to the base power supply, thereby resetting the capacitor Cd and resetting the delay circuit 125. The second transistor T2 has a gate terminal connected to the output terminal of the first comparator 121a, a source terminal connected to the common node Nc, and a drain terminal connected to the base power source, . ≪ / RTI >

The third comparator 125a compares the voltage on the common node Nc with the set delay reference voltage Vref3 and outputs the third comparison signal CS3 of the first logic state L or the second logic state H, And outputs it. For example, the third comparator 125a may be turned on by the voltage charged in the capacitor Cd as the first transistor T1 is turned on while the second transistor T2 is turned off. And generates and outputs the third comparison signal CS3 of the first logic state L when the voltage on the common node Nc is equal to or smaller than the set delay reference voltage Vref3. The third comparator 125a generates the third comparison signal CS3 of the second logic state H when the voltage on the common node Nc is larger than the set delay reference voltage Vref3, do.

The third inverter 125b inverts the logic state of the third comparison signal CS3 input from the third comparator 125a to generate a delay reference signal DRS.

The low voltage lock signal generator 127 generates first and second low voltage detection signals LDS1 and LDS2 from the first and second low voltage detectors 121 and 123 and the first and second low voltage detection signals LDS1 and LDS2, Voltage lock signal UVLO of the first logic state L or the second logic state H based on the delay reference signal DRS and provides the low voltage lock signal UVLO to the switching controller 130. For example, the low voltage lock signal generator 127 according to the present invention may include a first logic gate 127a, a third transistor T3, and a second logic gate 127b.

The first logic gate 127a outputs a logic state of the first low voltage detection signal LDS1 supplied from the first low voltage detection section 121 and the delay reference signal DRS supplied from the delay circuit section 125, And generates a first logic state L or a delay signal DS of a second logic state to supply the generated signal to the second logic gate 127b. For example, the first logic gate 127a may include an exclusive NOT OR gate to perform an exclusive NOR operation on the first undervoltage detection signal LDS1 and the delay signal DS, So that the delay signal DS can be generated.

The third transistor T3 is switched according to a delay reference signal DRS of a second logic state H supplied from the delay circuit 125 and is supplied with a second low voltage detection And supplies the signal LDS2 to the second logic gate 127b. The third transistor T3 has a gate terminal connected to the output terminal of the delay circuit 125, a source terminal connected to the output terminal of the second low voltage detector 123, And a drain terminal connected to the drain terminal 127b.

The second logic gate 127b outputs a logic state of each of the delay signal DS supplied from the first logic gate 127a and the second low voltage detection signal LDS2 supplied from the third transistor T3, And generates a first logic state L or a second logic low voltage lock signal UVLO to provide the switching control unit 130 with the generated low voltage lock signal UVLO. For example, the second logic gate 127b may be a NOR gate and may include a delayed signal DS from the first logic gate 127a and a second low voltage from the third transistor T3 turned on. The detection signal LDS2 may be NORed to generate the low voltage lock signal UVLO.

The switching control unit 130 generates a pulse width modulation signal S _PWM by feedback FB of the output voltage Vout of the DC-DC converter 110, When the low voltage lock signal UVLO of the state H is supplied, the pulse width modulation signal S _PWM is output to switch the switching element Psw of the DC-DC converter 110, The output voltage Vout of the transistor Q1 is constantly controlled. On the other hand, when the low voltage lock signal UVLO of the first logic state L is supplied from the low voltage lock control unit 120, the switching control unit 130 stops the output of the pulse width modulation signal S _PWM And turns off the switching element Psw of the DC-DC converter 110. For this, the switching controller 130 may include a pulse width controller 132 and a switch SW.

The pulse width controller 132 receives the feedback voltage FB of the output voltage Vout of the DC-DC converter 110 and generates a pulse width modulation signal S _PWM having a predetermined duty ratio. Further, the pulse width controller 132 may generate a pulse width modulated signal S _PWM having a duty ratio corresponding to the duty data supplied from the outside.

The switch SW is turned on according to the low voltage lock signal UVLO of the second logic state H supplied from the low voltage lock control unit 120 and is supplied with the pulse width modulation signal S _PWM is supplied to the switching element Psw of the DC-DC converter 110. On the other hand, the switch SW is turned off according to the low-voltage lock signal UVLO of the first logic state L supplied from the low-voltage lock control unit 120 and is supplied from the pulse width control unit 132 to the DC- The switching element Psw of the DC-DC converter 110 is turned off by blocking the pulse width modulation signal S _PWM supplied to the switching element Psw of the DC-DC converter 110. [ The switch SW has a gate terminal connected to the output terminal of the low voltage lock control unit 120, a source terminal connected to the output terminal of the pulse width control unit 132, And a drain terminal connected to the terminal.

The switching element Psw of the DC-DC converter 110, the low voltage lock control part 120, and the switching control part 130 may be incorporated in one integrated circuit (IC).

FIG. 5 is a waveform diagram for explaining an operation waveform of the power supply device according to the embodiment of the present invention, which explains the operation process of the power supply device according to the present invention when the input power source is lowered to the first reference low voltage Fig.

3 to 5, when the input power source Vin is lowered to the first reference low voltage Vref1, the power supply device according to the present invention switches the DC-DC converter 110 for a predetermined delay time Td, The element Psw is forcibly turned off.

Specifically, when the input power supply Vin is lowered to the first reference low voltage Vref1, the first comparator 121 of the low voltage lock control unit 120 outputs the first low voltage detection signal of the second logic state H The delay circuit 125 generates the delay reference signal RDS of the second logic state H having the delay time Td set by the RC time constant and outputs the delayed reference signal RDS to the second comparator 123, the second low voltage detection signal LDS2 of the first logic state L is generated. In the delay circuit 125, the first transistor T1 is turned on by the first low voltage detection signal LDS1 of the second logic state H and the first transistor T1 is turned on. The driving voltage Vdd is charged into the capacitor Cd by supplying the driving voltage Vdd to the capacitor Cd through the resistor Rd and the capacitor Cd charged to less than the delay reference voltage Vref3, The delay reference signal RDS of the second logic state H is generated by the operation of the third comparator 125a and the third inverter 125b by the voltage V _Cd of the second logic state H. The low voltage lock signal generating unit 127 of the low voltage lock control unit 120 generates the first low voltage detection signal LDS1 of the second logic state H and the delay reference signal DRS The delay signal DS of the second logic state H is generated by the exclusive NOR operation of the first logic state H and the delay signal DS of the second logical state H generated and the first logic state L The low voltage lock signal UVLO of the first logic state L is generated by a NOR operation of the second low voltage detection signal LDS2 of the first logic state L. Therefore, the switching controller 130 forcibly switches the switching element Psw of the DC-DC converter 110 for the delay time Td set in accordance with the low-voltage lock signal UVLO in the first logic state L Off.

Then, during the delay time Td or after the delay time Td, the input power supply Vin lowered to the first reference low voltage Vref1 is not lowered to the second reference low voltage Vref2, or the low voltage lock reset voltage (Vreset), the power supply device according to the present invention switches the switching element Psw of the DC-DC converter 110. In this case, the first comparator 121 of the low voltage lock control unit 120 generates the first low voltage detection signal LDS1 of the second logic state H, and the delay circuit unit 125 of the first logic state The second comparator 123 generates the second low voltage detection signal LDS2 of the first logic state L while the delay reference signal RDS of the first logic state L is generated. Since the driving voltage Vdd is continuously supplied to the capacitor Cd through the first transistor T1 and the resistor Rd that are turned on in the delay circuit unit 125, The delay reference signal RDS of the first logic state L is generated by the operation of the third comparator 125a and the third inverter 125b by the voltage V _Cd of the capacitor Cd to be charged . The low voltage lock signal generating unit 127 of the low voltage lock control unit 120 detects the first low voltage detection signal LDS1 of the second logic state H and the delay reference signal DRS The delay signal DS of the first logic state L is generated by an exclusive NOR operation of the first logic state L and the generated delay signal DS of the first logic state L and the first logic state L The low voltage lock signal UVLO of the second logic state H is generated by a NOR operation of the second low voltage detection signal LDS2 of the second logic state H. Therefore, the switching controller 130 outputs the pulse width modulation signal S _PWM according to the low voltage lock signal UVLO of the second logic state H, and outputs the pulse width modulation signal S _PWM to the switching element Psw of the DC- ) So that the output voltage Vout is output from the DC-DC converter 110.

FIG. 6 is a waveform diagram for explaining an operation waveform of the power supply device according to the embodiment of the present invention. When the input power is lowered below the first reference lower voltage, Fig.

Referring to FIGS. 3, 4, and 6, when the input power supply Vin is lowered to the first reference lower voltage Vref1, the power supply apparatus according to the present invention, as described above, The switching element Psw of the DC-DC converter 110 is forcibly turned off.

When the input power supply Vin is lowered below the first reference lower voltage Vref1 during the delay time Td, the power supply device according to the present invention is switched to the switching device of the DC-DC converter 110 Psw) are forcibly turned off. Specifically, when the input power supply Vin is lower than the second reference low voltage Vref2 during the delay time Td, the first comparison unit 121 of the low voltage lock control unit 120 outputs a second logic state The second comparator 123 generates the first low voltage detection signal LDS1 of the first logic state H and the delay circuit 125 generates the second reference signal RDS of the second logic state H, The second low voltage detection signal LDS2 of the logic state H is generated.

The low voltage lock signal generating unit 127 of the low voltage lock control unit 120 generates the first low voltage detection signal LDS1 of the second logic state H and the delay reference signal DRS The delay signal DS of the second logic state H is generated by the exclusive NOR operation of the first logic state H and the second logic state H of the generated second logic state H, The low voltage lock signal UVLO of the first logic state L is generated by a NOR operation of the second low voltage detection signal LDS2 of the first logic state L.

Accordingly, when the delay time Td becomes lower than the first reference lower voltage Vref1, the switching element Psw of the DC-DC converter 110 is turned off, Is forcibly turned off for the delay time Td set by the low voltage lock signal UVLO in the logic state L. [

Then, when the input power supply Vin lowered below the second reference low voltage Vref2 is turned off during the delay time Td, the power supply apparatus according to the present invention is turned off, The switching element Psw is turned off. Specifically, when the input power supply Vin lowered to the second reference low voltage Vref2 is turned off during the delay time Td, the first comparison unit 121 of the low voltage lock control unit 120 outputs the input The first low voltage detection signal LDS1 of the first logic state L is generated due to the power Vin being off and the delay circuit 125 generates the delay reference signal of the second logic state H And the second comparator 123 generates the second low voltage detection signal LDS2 of the second logic state H at the same time.

The low voltage lock signal generating unit 127 of the low voltage lock control unit 120 detects the first low voltage detection signal LDS1 of the first logic state L and the delay reference signal DRS The delay signal DS of the first logic state L is generated by the exclusive logical NOR operation of the first logic state L and the second logic state H of the generated first logic state L, The low voltage lock signal UVLO of the first logic state L is generated by a NOR operation of the second low voltage detection signal LDS2 of the first logic state L.

Therefore, when the input power supply Vin lowered below the second reference undervoltage Vref2 is turned off during the delay time Td, the switching element Psw of the DC-DC converter 110 is switched to the low- And is turned off by the low voltage lock signal UVLO of the first logic state L generated in the controller 120. [

3, the power supply 100 according to the present invention includes one DC-DC converter 110 and one switching controller 130. However, the present invention is not limited to this, The supply apparatus 100 includes a plurality of DC-DC converters 110 and a plurality of switching control units 130. The supply apparatus 100 operates according to the low voltage lock signal UVLO supplied from the one low voltage lock control unit 120 do. In this case, some of the plurality of DC-DC converters 110 may be a step-up DC-DC converter that outputs an output voltage Vout of a voltage level higher than the voltage level of the input power supply Vin, DC converter that outputs an output voltage Vout of a voltage level lower than the voltage level of the power source Vin.

As described above, the power supply device 100 according to the embodiment of the present invention can be used as a power supply device of a flat panel display device including a liquid crystal display device, an organic light emitting display device, or a plasma display device, It is possible to apply the present invention to a power supply apparatus for various information devices that require a variety of information devices.

7 is a simulation waveform diagram of a power supply apparatus according to an embodiment of the present invention. It is a waveform diagram of a first and a second low voltage detection signal, a delay reference signal, a delay time, and a pulse width modulation signal Fig.

7, when the input power Vin is lowered to the first reference low voltage Vref1, the switching element Psw of the DC-DC converter 110 is turned off for a predetermined delay time, When the input power supply Vin lowered to the first reference low voltage Vref1 does not become lower than the second reference low voltage Vref2, the switching element Psw of the DC-DC converter 110 is turned on again , The switching element Psw of the DC-DC converter 110 is turned off again when the input power supply Vin is lowered to the second reference low voltage Vref2 or lower and the input lower than the second reference low voltage Vref2 It can be confirmed that the switching element Psw of the DC-DC converter 110 is turned on again when the power supply Vin becomes higher than the low voltage lock reset voltage Vreset.

The power supply apparatus 100 according to the embodiment of the present invention as described above is configured such that when the voltage of the input power source Vin is lowered to the first reference lower voltage Vref1, the DC / DC converter 110 The switching element Psw is turned off only when the input power supply Vin drops to the second reference lower voltage Vref2 or lower after the delay time Td, So that it operates stably even if the input power is lowered.

8 is a view for explaining a display device according to an embodiment of the present invention.

8, a display device according to an exemplary embodiment of the present invention includes a display panel 200, a panel driver 300, a power supply 400, a backlight unit 500, and a backlight driver 600 .

The display panel 200 includes a plurality of pixels P formed in regions defined by a plurality of gate lines GL and a plurality of data lines DL. Each of the plurality of pixels P includes a thin film transistor (not shown) connected to the gate line GL and the data line DL, and a liquid crystal cell connected to the thin film transistor. The display panel 200 displays an image by adjusting the transmittance of the light emitted from the backlight unit 500 by forming an electric field in the liquid crystal cell according to the data voltage supplied to each pixel P. [

The panel driving unit 300 includes a reference gamma voltage generating unit 310, a data driving circuit unit 320, a gate driving circuit unit 330, and a timing control unit 340.

The reference gamma voltage generator 310 may be implemented as a programmable gamma integrated circuit (IC) that generates a plurality of different reference gamma voltages RGV. The reference gamma voltage generator 310 generates a reference gamma voltage Vdd for generating a reference gamma voltage Vdd and a low-potential DC voltage from the power supply 400 according to the gamma voltage setting data, Level and supplies the reference gamma voltages RGV to the data driving circuit unit 320. [ The reference gamma voltage generator 310 may generate a plurality of reference gamma voltages RGV commonly used for each pixel P of the unit pixel, It is possible to generate a plurality of reference gamma voltages RGV for each color used independently. Here, the gamma voltage setting data may be stored in the memory or may be supplied from the timing controller 340.

The data driving circuit 320 generates a plurality of positive / negative polarity gradation voltages by subdividing the plurality of reference gamma voltages RGV supplied from the reference gamma voltage generator 310, G and B input from the timing controller 340 in accordance with a supplied data control signal DCS and outputs the latched pixel data using the plurality of positive / Polarity data voltage, and then supplies the data voltages to the data lines DL by selecting the positive / negative polarity data voltages corresponding to the polarity control signals.

The gate driving circuit unit 330 generates a gate signal according to a gate control signal GCS supplied from the timing controller 340 and sequentially supplies the gate signal to the gate lines GL. Here, the gate driving circuit portion 330 may be formed on the substrate simultaneously with the formation of the thin film transistor.

The timing controller 340 arranges the input data RGB input from the outside into the pixel data R, G, and B so as to be suitable for driving the display panel 200, and supplies the data to the data driving circuit unit 320.

The timing control unit 340 receives the data control signal DCS and the gate control signal DCS for controlling the operation timing of the data driving circuit unit 320 and the gate driving circuit unit 330 using the input timing synchronization signal TSS, (GCS). Here, the timing synchronization signal TSS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a dot clock, and the like.

The timing controller 340 generates a backlight dimming signal DIM for controlling the brightness of the backlight unit 500 according to the brightness of the image of one frame and supplies the backlight dimming signal DIM to the backlight unit 500. Here, the timing controller 340 analyzes the input data (RGB) of one frame, calculates an average image level, and generates a backlight dimming signal (DIM) according to the calculated average image level. For example, when the image of one frame is determined as a relatively bright image according to the average image level, a backlight dimming signal DIM for reducing the brightness of the backlight unit 500 is generated, The backlight dimming signal DIM for increasing the brightness of the backlight unit 500 can be generated when the image of one frame is determined to be a relatively dark image.

The power supply unit 400 generates and outputs a voltage required for driving the display device.

The power supply unit 400 according to an exemplary embodiment generates the reference gamma voltage generation high-potential direct-current voltage Vdd having a constant DC voltage level using the input power supply Vin, . The power supply unit 400 includes the power supply device 100 described above with reference to FIGS. 3 to 7, and thus a detailed description thereof will be omitted.

The power supply unit 400 according to another embodiment generates a constant voltage Vcc having a constant DC voltage level using the input power supply Vin as well as the high potential DC voltage Vdd for generating the reference gamma voltage, Can be supplied to the driving unit 600. In this case, the power supply unit 400 includes the power supply device 100 described with reference to FIGS. 3 to 7, a DC-DC converter for generating the constant voltage Vcc and a switching controller are added, The added DC-DC converter and the switching controller operate according to the low-voltage lock signal output from the low-voltage lock control unit 120 described above. Similarly, the power supply unit 400 may generate and supply a driving voltage required for driving the data driving circuit unit 320, the gate driving circuit unit 330, and the timing control unit 340, respectively.

The backlight unit 500 irradiates the display panel 200 with light using the light emission of a plurality of light emitting diodes. The backlight unit 500 includes at least one light emitting diode array including a plurality of light emitting diodes connected in series. Here, the backlight unit 500 may be an edge-type backlight unit or a direct-type backlight unit.

The backlight driver 600 modulates the pulse width and / or amplitude of the backlight driving voltage V _LED according to the backlight dimming signal DIM based on the constant voltage Vcc supplied from the power supply unit 400 And drives the backlight unit 500, that is, the light emitting diode array, so that light of brightness corresponding to the backlight dimming signal DIM is irradiated on the display panel 200. [

The above-described display device includes the backlight unit 500, and thus can be a liquid crystal display device. However, the display device according to the present invention is not limited to the above-described liquid crystal display device, but may be an organic light emitting display device, a plasma display device, or the like. In this case, the above-described backlight unit 500 and backlight driver 600 are omitted.

As described above, the display device according to the embodiment of the present invention includes the power supply device 100 that operates stably even when the input power is low, so that the input power Vin reaches the set reference low voltage Vref It is possible to prevent a flicker phenomenon caused by an on / off repetition phenomenon of the DC-DC converter 110 generated in the case where the DC-DC converter 110 is turned on.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

100: power supply 110: DC-DC converter
120: low voltage lock control unit 121: first low voltage detection unit
123: second low voltage detection unit 125: delay circuit unit
127: Low voltage lock signal generating unit 130:
200: display panel 300: panel driver
400: Power supply unit 500: Backlight unit
600: back light driver

Claims (11)

A DC-DC converter for converting an input power source into a DC voltage in accordance with switching of a switching element and outputting the DC voltage;
A low voltage lock control unit for generating a low voltage lock signal according to a voltage drop of the input power supply; And
And a switching control unit for controlling switching of the switching device based on the low voltage lock signal,
Wherein the low voltage lock control unit generates a first logic low voltage lock signal for forcibly turning off the switching device for a predetermined delay time when the input power source is lowered to the first reference low voltage. Device. The method according to claim 1,
Wherein the low-
Voltage lock signal of the first logic state when the input power source is lower than a second reference undervoltage lower than the first reference undervoltage,
And generates a second logic low voltage lock signal for turning on the switching device when the input power decreased to the first reference low voltage is not lower than the second reference low voltage. . The method according to claim 1,
Wherein the low-
A first low voltage detection unit for comparing the input power source and the first reference low voltage to generate a first low voltage detection signal;
A second low voltage detection unit for generating a second low voltage detection signal by comparing the input power supply with a second reference low voltage lower than the first reference low voltage;
A delay circuit for generating a delay reference signal corresponding to the delay time according to an output signal of the first low voltage detector; And
And a low voltage lock signal generator for generating a low voltage lock signal in the first logic state or the second logic state according to the first and second low voltage detection signals and the delay reference signal. The method of claim 3,
Wherein the first low-
A first comparator for comparing the input power supply with the first reference lower voltage and generating a first comparison signal according to a comparison result; And
And a first inverter for inverting a logic state of the first comparison signal to generate the first undervoltage detection signal. The method of claim 3,
The second low voltage detection unit includes:
A second comparator for comparing the input power supply with the second reference undervoltage and generating a second comparison signal according to a comparison result; And
And a second inverter for inverting a logic state of the second comparison signal to generate the second low voltage detection signal. 5. The method of claim 4,
The delay circuit unit includes:
A first transistor which is turned on according to the first low voltage detection signal to output a driving voltage;
A resistor connected to the first transistor;
A capacitor connected between the resistor and the electromotive power source and charged by a drive voltage supplied through the first transistor and the resistor;
A second transistor connected in parallel to the capacitor, the second transistor being turned on according to the first comparison signal to discharge a voltage stored in the capacitor;
A third comparator for comparing the set delay reference voltage with the voltage of the capacitor to generate a third comparison signal; And
And a third inverter for inverting a logic state of the third comparison signal to generate the delay reference signal. The method of claim 3,
The low-voltage lock signal generating unit includes:
A first logic gate for performing a first logic operation on the first undervoltage detection signal and the delay reference signal to generate a delay signal;
A third transistor that is turned on according to the delay reference signal and outputs the second low voltage detection signal; And
And a second logic gate for performing a second logic operation on the second low voltage detection signal supplied from the third transistor turned on and the delay signal to generate a low voltage lock signal in the first logic state or the second logic state Wherein the power supply is a power supply. 8. The method of claim 7,
Wherein the first logical operation is an exclusive logical NOR operation,
And the second logical operation is a NOR operation. A display panel including a pixel formed in a pixel region defined by intersection of a gate line and a data line;
A panel driver for driving the pixel; And
And a power supply unit for converting input power into direct current voltage and supplying the direct current voltage to the panel driver,
Wherein the power supply unit includes the power supply unit according to any one of claims 1 to 8. A display apparatus comprising: 10. The method of claim 9,
Wherein the panel-
A reference gamma voltage generator for generating a plurality of reference gamma voltages;
A data driving circuit for converting pixel data inputted using the plurality of reference gamma voltages into data voltages and supplying the data voltages to the data lines;
A gate driving circuit for supplying a gate signal to the gate line; And
And a timing control section for controlling driving of the data driving circuit section and the gate driving circuit section and supplying pixel data to the data driving circuit section,
Wherein the power supply unit generates a DC voltage necessary for driving at least one of the reference gamma voltage generating unit, the data driving circuit unit, the gate driving circuit unit, and the timing control unit. 10. The method of claim 9,
A backlight unit for emitting light to the display panel; And
And a backlight driver for driving the backlight unit,
Wherein the power supply unit further generates a DC voltage required for driving at least one of the backlight unit and the backlight driver.

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