CN109104200B - 近似参数自适应 - Google Patents

近似参数自适应 Download PDF

Info

Publication number
CN109104200B
CN109104200B CN201810636877.8A CN201810636877A CN109104200B CN 109104200 B CN109104200 B CN 109104200B CN 201810636877 A CN201810636877 A CN 201810636877A CN 109104200 B CN109104200 B CN 109104200B
Authority
CN
China
Prior art keywords
channel parameters
adaptive algorithm
input signal
detector
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810636877.8A
Other languages
English (en)
Other versions
CN109104200A (zh
Inventor
M·马罗
J·贝洛拉多
V·B·阿什
R·阿胡贾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seagate Technology LLC
Original Assignee
Seagate Technology LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology LLC filed Critical Seagate Technology LLC
Publication of CN109104200A publication Critical patent/CN109104200A/zh
Application granted granted Critical
Publication of CN109104200B publication Critical patent/CN109104200B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878Line equalisers; line build-out devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10037A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/58Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
    • G11B5/596Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
    • G11B5/59633Servo formatting
    • G11B5/59666Self servo writing
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12Synchronisation of different clock signals provided by a plurality of clock generators
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/102Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10046Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10222Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10222Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • G11B20/1024Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation wherein a phase-locked loop [PLL] is used
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/48Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed
    • G11B5/58Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
    • G11B5/596Disposition or mounting of heads or head supports relative to record carriers ; arrangements of heads, e.g. for scanning the record carrier to increase the relative speed with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
    • G11B5/59633Servo formatting
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00Networks using digital techniques
    • H03H17/02Frequency selective networks
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131Digitally controlled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/001Analogue/digital/analogue conversion
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4138Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
    • H03M13/4146Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0602Systems characterised by the synchronising information used
    • H04J3/0617Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006Arrangements for removing intersymbol interference
    • H04L25/03012Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019Variable delay
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948Iterative decoding
    • H03M13/2951Iterative decoding using iteration stopping criteria
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/707Spread spectrum techniques using direct sequence modulation
    • H04B1/7097Interference-related aspects
    • H04B1/7103Interference-related aspects the interference being multiple access interference
    • H04B1/7105Joint detection techniques, e.g. linear detectors
    • H04B1/71055Joint detection techniques, e.g. linear detectors using minimum mean squared error [MMSE] detector
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0025Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of clock signal
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/002Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
    • H04L7/0029Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Probability & Statistics with Applications (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Error Detection And Correction (AREA)
  • Digital Magnetic Recording (AREA)
  • Moving Of The Head To Find And Align With The Track (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Lubricants (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

本发明提供了一种装置,所述装置可包括被配置为使用一组信道参数处理输入信号的电路。所述电路可以使用第一自适应算法产生第一组信道参数,以供所述电路使用作为处理所述输入信号时的所述一组信道参数。所述电路可以进一步基于所述第一组信道参数,并且基于使用所述第一自适应算法生成的第三组信道参数和使用所述第二自适应算法生成的第四组信道参数之间的关系来近似第二自适应算法的第二组信道参数,以供所述电路使用作为处理所述输入信号时的所述一组信道参数。此外,所述方法还可包括使用所述第二组信道参数作为所述一组信道参数来执行对所述输入信号的所述处理。

Description

近似参数自适应
发明内容
在某些实施例中,一种装置可包括被配置为使用一组信道参数处理输入信号的电路。该电路可以使用第一自适应算法产生第一组信道参数,以供电路使用作为处理输入信号时的一组信道参数。该电路可以进一步基于第一组信道参数,并且基于使用第一自适应算法生成的第三组信道参数和使用第二自适应算法生成的第四组信道参数之间的关系近似第二自适应算法的第二组信道参数,以供电路使用作为处理输入信号时的一组信道参数。此外,该方法还可包括使用第二组信道参数作为一组信道参数来执行对输入信号的处理。
在某些实施例中,一种系统可包括被配置为使用一组参数处理输入信号的信道电路,以及被配置为使用第一自适应算法产生第一组信道参数以供电路使用作为处理输入信号时的一组信道参数的自适应电路。该自适应电路可以被进一步配置为基于第一组信道参数,并且基于使用第一自适应算法生成的第三组信道参数和使用第二自适应算法生成的第四组信道参数之间的关系来近似第二自适应算法的第二组信道参数,以供信道电路使用作为处理输入信号时的一组信道参数。此外,自适应电路可以被配置为将第二组信道参数输出到信道电路,以用作处理输入信号时的一组信道参数。
在某些实施例中,一种方法可包括通过被配置为使用一组信道参数并且使用第一自适应算法处理输入信号的电路生成第一组信道参数,以供电路使用作为处理输入信号时的一组信道参数。该方法还可包括基于第一组信道参数,并且基于使用第一自适应算法生成的第三组信道参数和使用第二自适应算法生成的第四组信道参数之间的关系近似第二自适应算法的第二组信道参数,以供电路使用作为处理输入信号时的一组信道参数。另外,该方法还可包括使用第二组信道参数作为一组信道参数执行对输入信号的处理。
附图说明
图1是根据本公开的某些实施例的包括近似的参数自适应的通信信道的框图;
图2是根据本公开的某些实施例的近似的参数自适应方法的流程图;
图3是根据本公开的某些实施例的近似的参数自适应方法的流程图;
图4是根据本公开的某些实施例的包括近似的参数自适应的系统的框图。
具体实施方式
在以下对实施例的详细描述中,参考了形成其部分的附图,并且其中以说明的方式示出。应当理解,所述的各种实施例的特征可以组合,可使用其他实施例,并且可在不脱离本公开的范围的情况下进行结构变化。还应当理解,在不脱离本公开的范围的情况下,本文的各种实施例和示例的特征可以组合、交换或移除。
根据各种实施例,本文所述的方法和功能可被实现为在计算机处理器或控制器上运行的一个或多个软件程序。根据另一个实施例,本文所述的方法和功能可被实现为在计算设备(例如,使用磁盘驱动器的个人计算机)上运行的一个或多个软件程序。包括但不限于专用集成电路、可编程逻辑阵列和其他硬件设备的专用硬件具体实施同样可被构造为实现本文所述的方法和功能。此外,本文所述的方法可被实现为包括指令的计算机可读存储介质或设备,所述指令在被执行时使得处理器执行所述方法。
本公开总体上涉及参数自适应,并且在一些实施例中,本公开可涉及基于由第二自适应算法产生的参数的变化针对第一自适应算法近似参数自适应。
某些系统诸如电气、电子、电机驱动、处理或其他系统可接收感兴趣的信号,并且根据参数处理该信号。例如,通信系统或磁记录存储系统的读取信道可以利用自适应参数来处理输入信号。在一些系统中,检测器可以基于均衡样本序列和自适应参数来生成数据序列。自适应组件可包括用于自适应检测器的参数的各种自适应功能或算法。例如,自适应参数可以是软输出维特比算法(SOVA)检测器(例如,有限脉冲响应滤波器(FIR)或SOVA检测器的数据相关FIR(DDFIR))的滤波器电路的系数或抽头,或者是参数诸如SOVA检测器的分支方差或分支偏差。
自适应算法类型的示例可以包括最小误码率(MBER)自适应、最小均方误差(MMSE)自适应、最小均方自适应、递归最小二乘(RLS)自适应,以及类似的自适应算法。
在一些实施例中,可以使用第一自适应算法来在至少一组情形下(例如,在正常操作下)调整一组自适应参数。在至少某些其他情形下,可以基于由第一自适应算法产生的自适应参数集合与由第二自适应算法产生的自适应参数集合之间的预定关系,使用第二自适应算法针对第一自适应算法近似自适应参数集合。例如,可以在第一自适应算法可能不适合处理或其中第一自适应算法可能提供错误更新的情形下执行此类近似。
这种系统的一个示例将在下文参照图1进行论述。
参见图1,示出了包括近似参数自适应的通信信道的框图,并且该通信信道通常被指定为100。系统100可以包括可以联接至均衡器104的模数转换器(ADC)102。均衡器104可以联接至检测器106和自适应组件108。检测器106可以联接至解码器HO和自适应组件108。自适应组件108可连接至检测器106。另外,解码器110可以包括来自通信信道100的输出并且被连接到自适应组件108。自适应组件108可包括用于存储生产数据112或者访问存储在单独存储器(未示出)中的生产数据112的存储器。
ADC 102、均衡器104、检测器106、自适应组件108和解码器HO中的每一者可以是独立电路、片上系统(SOC)、固件、处理器或未列出的其他系统,或它们的任何组合。
如下面详细讨论的,在图1所示的实施例中,调整的参数是检测器106的参数。尽管本文的论述利用读取信道的检测器的参数作为示例,但本发明所公开的技术和系统也可应用于其他电路或参数。根据本公开,许多变型形式对于本领域的普通技术人员而言将是显而易见的。
在操作中,ADC 102可以以一定间隔对连续时间信号x(t)114进行采样,并且可以对该信号进行量化以产生数字化的样本序列x116。
均衡器104可以接收数字化样本序列x116,并且生成均衡样本序列y 118。在一些示例中,均衡器可以操作以缩短信道的码间干扰(ISI)长度或存储器。此外,均衡器102可用于吸收随时间发生的输入信号或噪声统计中的变化。一般来讲,均衡器104可以向检测器106产生一致的已知输入信号,使得检测器106可以基于自适应组件提供的系数或参数p124估计与信号x(t)114相对应的数据序列108。
检测器106可以操作以基于均衡样本序列y 118和由自适应组件108提供的参数或系数p 124确定(或估计)与信号x(t)114相对应的比特值的数据序列bo 120。具体地讲,可以将参数p124提供给检测器用于估计数据序列bo 120。在一些实施例中,数据序列bo 120可以表示每个比特值为0或1的概率。值124可以表示为这些概率的比率的对数,并且可被称为对数似然比或LLR。检测器106可基于信道响应的信息(例如,针对每个可能的写入/传输的数据模式的预期信道输出)来生成LLR值。在一些示例中,检测器108可采用软输出维特比算法(SOVA)。
所生成的数据序列bo 120可以被传递到解码器110,如果数据序列bo120被成功解码,该解码器可以生成解码数据b 122,或者可以生成表示每个比特是0或1的概率的外部信息或EXT(未示出)。解码器110可以基于使用的代码的结构生成解码数据b 122或者EXT。虽然为了便于说明而未示出,但是在一些具体实施中,可以将EXT返回检测器(例如,用于作为由检测器106和解码器HO执行的迭代解码过程的一部分)。
自适应组件108可以操作以接收均衡样本序列y 118、数据序列bo 120和解码数据b 122,并且调整检测器106的参数124。
更具体地讲,检测器106可以是SOVA检测器。在一些实施例中,可以在正常操作中使用最小误码率(MBER)自适应来调整SOVA检测器的参数124。更具体地讲,可以在正常操作中在扇区上运行SOVA检测器参数的MBER自适应,其中在该操作中,解码器HO可以正确解码写入数据(例如,由此重新产生写入数据并将b 122提供给自适应组件)。解码数据b 122可以连同存储的均衡样本序列y 118(或它们的子集)一起被反馈到MBER自适应。
在MBER自适应可能不适合或其中MBER自适应可能提供错误更新的情况下,可基于由LMS自适应算法产生的自适应参数集合,并且基于MBER产生的自适应参数集合和由LMS产生并作为生产数据112存储的自适应参数集合之间的预定关系确定近似的更新MBER参数。例如,当解码器未能对写入数据(b 122)进行解码并且将使用可包括位错误(例如,决策引导的自适应)的检测器判定数据(bo 120)执行自适应时,MBER自适应可能不适合,或者检测器参数的MBER自适应可能提供错误更新。当执行决策引导的自适应时,MBER成本函数可能导致自适应系数以加剧决策错误的方式移动,这可能进一步降低检测器性能。也可使用其他因素或条件触发近似的MBER参数生成。例如,当感兴趣的扇区在经过阈值次数的迭代解码迭代之后未能解码并且具有来自相邻扇区的完全不同的噪声统计时(其中在相邻扇区上的自适应可能无用),可以触发近似的MBER参数生成。
可以在制造期间或在字段的训练过程期间生成制造数据112。就硬盘驱动器或其参数在介质上变化的其他设备而言,可针对每个存储单元(例如,扇区、页面等)或针对可对应于轨道组的较大区域或区(这是下面讨论的示例中的情况)而生成生产数据112。在生成制造数据期间,可以使用已知的写入数据生成MBER和LMS参数集合。可以存储生成的参数集合、关于参数集合之间关系的信息(例如,差值)或两者。
在操作中,当解码器HO未能对存储在扇区中的数据进行解码时,可使用检测器判定120生成当前LMS参数集合。然后,在一些实施例中,在训练中生成并作为制造数据112存储的MBER和LMS参数集合之间的差可被添加到当前LMS参数以生成近似MBER参数。
下面给出了具体地针对分支偏差将该过程应用于示例类型的SOVA检测器参数。
对数域维特比或SOVA中的分支度量值可采取以下形式:
Figure BDA0001701802830000051
其中σ2可以是分支方差,z可以是该分支的DDFIR输出(或者无数据相关滤波情况下的FIR),并且Zt可以是分支偏压。利用LMS自适应中的MMSE成本函数,Zt=zavg=E[z](例如,分支均值的前提可以是该分支为正确分支)。然而,在存在复杂噪声统计的情况下,利用MBER成本函数进行调整可能会使zt与zavg分离,以最小化BER。
在制造期间,对于每个区域,可以确定MBER参数集合Zt和测量的MMSE参数集合zavg。制造参数集合可以表示为zt (m)和zavg (m)
当解码器HO未能在字段操作中解码特定扇区时,更新的MBER参数可允许对扇区进行解码。例如,如果解码失败是由于磁道挤压造成的,则如果使用了该扇区的更新MBER参数,则扇区可能会解码。但是,可能不会使用MBER自适应,因为自适应将基于可能包含错误的检测器判定。相反,自适应组件108可以使用检测器判定生成或调整当前MMSE参数
Figure BDA0001701802830000061
自适应组件然后可以使用当前MMSE参数zavg (f)近似更新的MBER参数:
zt (f)≈zt (m)+(zavg (f)-zavg (m))
由于对于制造参数集合和字段内错误恢复参数集合而言MBER偏差与MMSE偏差之间的差值可能相同,因此这可能是有效的。由于Zt(m)和zavg (m)存储在制造过程的制造数据112中,在从检测器判定和LMS算法计算zavg (f)之后自适应组件可执行近似。在一些实施例中,LMS自适应可以利用来自解码器的总信息(例如,LDPC分片的总信息),其可以从检测器判定和外部信息中导出。
尽管上述示例响应于解码失败来计算近似参数,但是实施例不限于此。例如,响应于触发条件(例如,解码器HO未能将扇区解码三十(30)次),自适应组件108可以以动态和连续的方式生成近似参数,并且基于检测器106或允许使用近似参数的自适应组件108中的模式选择使用该近似参数。
参见图2,示出了近似参数自适应的方法的流程图,该方法通常指定为200。更具体地讲,流程图200可以是制造或训练操作,以生成如上文相对于图1详细描述的制造数据112(例如,对于当前区)。
在202,系统可以接收当前区的连续时间输入信号的多个样本以及相应的已知数据。然后,系统可以在204处基于连续时间输入信号生成数字化样本序列。在206处,系统可以基于数字化样本生成均衡采样序列。
接下来,系统可以在208处基于均衡样本序列和可更新的MBER检测器参数产生基于MBER的输入信号的数据序列估计。以在210处,系统可基于均衡样本序列和可更新的MMSE检测器参数产生基于MMSE的输入信号的数据序列估计。在一些实施例中,解码器可以针对基于MBER的估计和基于MMSE的估计中的一个或多个执行解码操作。
在212处,系统可以基于已知值和MBER估计对MBER检测器参数执行基于MBER的自适应过程。然后,在214处,系统可以基于已知值和MMSE估计对MMSE检测器参数执行基于MMSE的自适应过程。
然后,在216处,系统可确定MBER检测器参数和MMSE检测器参数是否已稳定。如果参数已稳定,则在218处,系统可存储当前区的基于MBER的检测器参数和基于MMSE的检测器参数(例如,作为生成数据112)。在一些实施例中,系统还可以确定并存储MBER检测器参数与MMSE检测器参数之间的关系数据(例如,差值)。除此之外或另选地,当利用区参数时可生成一些或全部关系数据。如果参数尚不稳定,则系统可返回到208以进行另外的自适应操作。虽然未示出,但在一些实施例中,当参数尚未稳定时,也可以重复另外的操作诸如操作202至206中的一个或多个操作,或者可以对新样本执行稳定性确定,直到参数对于该区的数据样本总体上已稳定。
参见图3,示出了近似参数自适应的方法的流程图,该方法通常指定为300。更具体地讲,流程图300可以是在读取或接收操作期间的检测、解码和近似参数自适应,并且可以如上文相对于图1所详述的那样执行。
在操作中,在302处,系统可以例如针对当前数据扇区接收连续时间输入信号的多个样本。在304处,系统可以基于连续时间输入信号例如使用ADC生成数字化样本序列。接下来,在306处,系统可以基于数字化样本生成均衡采样序列。
在308处,系统可基于均衡样本序列和可更新的MBER检测器参数(例如,使用SOVA检测器)产生输入信号的数据序列估计。然后,可以在310处例如使用LDPC解码器对检测器估计来执行解码操作。
在312处,系统可以确定解码器是否成功。如果是,系统可以停止当前扇区的操作,输出解码的数据序列,并且在314处,使用MBER自适应基于成功解码的数据序列更新基于MBER的检测器参数。如果解码器不成功,则系统可以在316处确定当前扇区的解码尝试的阈值次数是否已经失败。如果不是,则系统可以返回到308以进行附加检测和解码尝试。如果对于当前扇区已经发生阈值次数的解码失败,则系统可以在318处开始近似参数自适应。更具体地讲,在318处,系统可以通过使用基于MMSE的检测器参数执行检测操作,对基于MMSE的检测器估计上执行解码并且使用MMSE自适应更新基于MMSE的检测器参数,以调整当前扇区的基于MMSE的检测器参数。
接下来,在320处,系统可以根据基于MMSE的检测器参数,并且根据当前区的MBER检测器参数和基于MMSE的检测器参数的先前值的关系数据来近似更新的MBER检测器参数。例如,可以通过将先前生成并存储的MBER检测器参数和基于MMSE的检测器参数之间的差值添加至当前扇区的当前生成的基于MMSE的检测器参数,以生成近似的更新MBER检测器参数,如以上关于图1所讨论的。
然后,在322处,系统可执行检测器操作以基于均衡样本序列和近似的更新MBER检测器参数产生输入信号的数据序列估计,并且基于使用近似的更新MBER检测器参数生成的估计来执行解码操作(例如,可以使用近似的更新MBER检测器参数执行一个或多个迭代检测和解码操作)。虽然未示出,但如果322处的解码操作成功,则可以针对当前扇区输出解码结果,并且可以基于近似的更新MBER检测器参数和MBER检测器参数中的一者或两者使用成功解码结果执行MBER自适应。如果322处的解码操作不成功,则可以触发其他恢复操作,或者过程300可以以错误状态终止。
针对方法200和300列出的所有步骤都可应用于具有自适应参数的系统。如上所述,其他自适应算法可代替MBER和MMSE,并且这些处理可用于其他电路例如解码器、均衡器、ADC等等的参数。根据本公开,许多其他变型形式将是显而易见的。用于执行该方法中的操作的组件和电路可以是分立的,或者集成到片上系统(SOC)或其他电路中。此外,这些步骤可以在处理器(例如,数字信号处理器)中执行、在软件中实现、经由固件实现或通过其他手段来执行。
参见图4,示出了包括近似参数自适应的系统的框图,并且该系统通常被指定为400。系统400可以是数据存储设备(DSD)的示例,并且可以是系统100的示例性具体实施。DSD 416可以任选地连接到主机设备414并且可从该主机设备移除,该主机设备可以是具有存储数据的设备或系统,诸如台式计算机、膝上型计算机、服务器、数字视频录像机、影印机、电话、音乐播放器、未列出的其他电子设备或系统,或者它们的任何组合。数据存储设备416可经由基于硬件/固件的主机接口电路412与主机设备414进行通信,该主机接口电路可包括允许DSD 416与主机414物理连接和断开连接的连接器(未示出)。
DSD 416可包括可以是可编程控制器的系统处理器402以及相关联的存储器404。系统处理器402可以是片上系统(SOC)的一部分。缓冲器406可以在读取和写入操作期间临时存储数据,并且可包括命令队列。读取/写入(R/W)信道410可以在对数据存储介质408进行写入操作期间对数据进行编码,并且在从数据存储介质进行读取操作期间对数据进行重构。数据存储介质408被示出和描述为硬盘驱动器,但也可以是其他类型的磁介质,诸如闪存介质、光学介质或其他介质,或者它们的任何组合。
RAV信道410可以一次接收来自多于一个数据存储介质的数据,并且在一些实施例中,还可以同时接收诸如来自读取头的多于一个输出的多个数据信号。例如,具有二维磁记录(TDMR)系统的存储系统可具有多个读取或记录元件,并且可以同时或几乎同时从两个轨道进行读取。多维录音(MDR)系统可以接收来自多个源的两个或更多个输入(例如,记录头、闪存、光学存储器等)。R/W信道410可组合多个输入并提供单个输出,如本文的示例所述。
框418可实现系统和方法100、200和300的系统和功能中的全部和部分。在一些实施例中,框418可以是集成到R/W信道410中的独立电路,被包括在片上系统、固件、软件或它们的任何组合中。
本文所述的说明、示例和实施例旨在提供对各种实施方案的结构的一般理解。这些说明并非旨在用作采用本文所述结构或方法的装置和系统的所有元件和特征的完整描述。在查看本公开后,许多其他实施例对于本领域技术人员而言可以是显而易见的。可通过本公开利用并得到其他实施例,使得可在不脱离本公开的范围的情况下进行结构和逻辑替换和变化。例如,附图和以上描述提供了可改变的架构和电压的示例,诸如系统的设计要求。此外,虽然在本文中已说明和描述了具体实施例,但应当理解,被设计为实现相同或相似目的的任何后续布置可以替代所示的具体实施例。
本公开旨在覆盖各种实施例的任何和全部后续改型或变型。在查看说明书后,上述示例的组合以及本文中未具体描述的其他实施例对于本领域技术人员而言将是显而易见的。此外,图示仅仅是代表性的,可能未按比例绘制。图示中的某些比例可能被放大,而其他比例可能被缩小。因此,本公开和附图被认为是例示性的,而非限制性的。

Claims (20)

1.一种用于近似参数自适应的装置,包括:
电路,所述电路被配置为使用一组信道参数处理输入信号,所述电路被进一步配置为:
使用第一自适应算法产生第一组信道参数,以供所述电路使用作为处理所述输入信号时的所述一组信道参数;
基于所述第一组信道参数,并且基于使用所述第一自适应算法生成的第三组信道参数和使用第二自适应算法生成的第四组信道参数之间的关系来近似所述第二自适应算法的第二组信道参数,以供所述电路使用作为处理所述输入信号时的所述一组信道参数;以及
使用所述第二组信道参数作为所述一组信道参数执行对所述输入信号的所述处理。
2.根据权利要求1所述的装置,还包括所述电路还包括检测器,所述检测器使用所述一组信道参数执行对所述输入信号的所述处理。
3.根据权利要求2所述的装置,还包括所述检测器是软输出维特比算法(SOVA)检测器,并且所述一组信道参数是所述SOVA检测器的分支偏差。
4.根据权利要求2所述的装置,还包括所述第一自适应算法是最小均方误差MMSE自适应算法,并且所述第二自适应算法是最小误码率MBER自适应算法。
5.根据权利要求1所述的装置,还包括存储器,所述存储器存储使用所述第一自适应算法生成的所述第三组信道参数、以及使用所述第二自适应算法生成的所述第四组信道参数。
6.根据权利要求1所述的装置,还包括所述电路还包括检测器,所述检测器使用所述一组信道参数执行对所述输入信号的所述处理,所述电路被进一步配置为:
使用由所述第二自适应算法生成的第五组信道参数作为处理所述输入信号时的所述一组信道参数执行所述输入信号的处理,以产生检测结果;
确定由所述检测器使用所述第五组信道参数产生的一个或多个检测结果的解码已失败阈值次数;以及
至少部分地响应于所述确定所述解码已经失败阈值次数,使用所述第二组信道参数作为所述一组信道参数执行对所述输入信号的所述处理。
7.根据权利要求6所述的装置,还包括所述电路被配置为:
确定由所述检测器使用所述第二组信道参数产生的一个或多个检测结果的解码已成功;以及至少部分地响应于所述确定所述解码已成功,使用所述第二自适应算法,使用所述成功解码结果调整所述第二组信道参数。
8.根据权利要求1所述的装置,还包括所述电路还包括检测器,所述检测器使用所述一组信道参数执行对所述输入信号的所述处理,所述电路被进一步配置为:
使用所述第二自适应算法生成的第五组信道参数作为处理所述输入信号时的所述一组信道参数执行对所述输入信号的处理,以产生检测结果;
确定由所述检测器使用所述第五组信道参数产生的一个或多个检测结果的解码在小于失败阈值次数后成功;以及
至少部分地响应于所述确定所述解码已成功,使用所述第二自适应算法,使用所述成功解码结果调整所述第五组信道参数。
9.根据权利要求1所述的装置,还包括:
存储器,所述存储器存储使用所述第一自适应算法生成的所述第三组信道参数、以及使用所述第二自适应算法生成的所述第四组信道参数;
所述输入信号是从磁存储介质的扇区读取的回读信号;并且
所述第三组信道参数和所述第四组信道参数对应于包括所述扇区并且在制造过程期间生成的所述磁存储介质的区域,所述制造过程包括回读写入包括所述扇区的所述磁存储介质的所述区域的已知数据。
10.一种用于近似参数自适应的系统,包括:
信道电路,所述信道电路被配置为使用一组参数处理输入信号;自适应电路,所述自适应电路被配置为:
使用第一自适应算法产生第一组信道参数,以供所述电路使用作为处理所述输入信号时的所述一组信道参数;
基于所述第一组信道参数,并且基于使用所述第一自适应算法生成的第三组信道参数和使用第二自适应算法生成的第四组信道参数之间的关系来近似所述第二自适应算法的第二组信道参数,以供所述信道电路使用作为处理所述输入信号时的所述一组信道参数;以及
将所述第二组信道参数输出到所述信道电路,以用作处理所述输入信号时的所述一组信道参数。
11.根据权利要求10所述的系统,还包括所述信道电路是软输出维特比算法(SOVA)检测器,并且所述一组信道参数是所述SOVA检测器的分支偏差。
12.根据权利要求11所述的系统,还包括所述第一自适应算法是最小均方误差MMSE自适应算法,并且所述第二自适应算法是最小误码率MBER自适应算法。
13.根据权利要求11所述的系统,还包括:
存储器,所述存储器存储使用所述第一自适应算法生成的所述第三组信道参数、以及使用所述第二自适应算法生成的所述第四组信道参数;
所述输入信号是对应于磁存储介质的扇区的数字化样本序列;并且
所述第三组信道参数和所述第四组信道参数对应于包括所述扇区并且在制造过程期间生成的所述磁存储介质的区域,所述制造过程包括回读写入包括所述扇区的所述磁存储介质的所述区域的已知数据。
14.根据权利要求13所述的系统,还包括:
ADC电路,所述ADC电路被配置为基于对应于所述扇区的回读信号生成一个或多个ADC样本;
均衡器电路,所述均衡器电路被配置为接收ADC样本并均衡所述ADC样本以生成所述数字化样本序列;和
解码器,所述解码器被配置为接收使用所述一组参数处理所述输入信号的所述SOVA检测器的输出,并且对所述SOVA检测器的所述输出执行解码。
15.根据权利要求10所述的系统,还包括所述信道电路是检测器,并且所述自适应电路被进一步配置为:
将第五组信道参数输出到所述信道电路,以用作处理所述输入信号时的所述一组信道参数以产生一个或多个检测结果,所述第五组信道参数使用所述第二自适应算法产生;
确定使用所述第五组信道参数对由所述检测器产生的所述一个或多个检测结果的解码已失败阈值次数;以及
至少部分地响应于所述确定所述解码已经失败阈值次数,使用所述第二组信道参数作为所述一组信道参数执行对所述输入信号的所述处理。
16.根据权利要求10所述的系统,还包括所述信道电路是检测器,并且所述自适应电路被进一步配置为:
将第五组信道参数输出到所述信道电路,以用作处理所述输入信号时的所述一组信道参数以产生一个或多个检测结果,所述第五组信道参数使用所述第二自适应算法产生;
确定使用所述第五组信道参数对由所述检测器产生的所述一个或多个检测结果的解码在小于失败阈值次数后已成功;以及
至少部分地响应于所述确定所述解码已成功,使用所述第二自适应算法,使用所述成功解码结果调整所述第五组信道参数。
17.一种用于近似参数自适应的方法,包括:
通过被配置为使用一组信道参数并且使用第一自适应算法处理输入信号的电路产生第一组信道参数,以供所述电路使用作为处理所述输入信号时的所述一组信道参数;
基于所述第一组信道参数,并且基于使用所述第一自适应算法生成的第三组信道参数和使用第二自适应算法生成的第四组信道参数之间的关系来近似所述第二自适应算法的第二组信道参数,以供所述电路使用作为处理所述输入信号时的所述一组信道参数;以及
使用所述第二组信道参数作为所述一组信道参数执行对所述输入信号的所述处理。
18.根据权利要求17所述的方法,还包括电路包括软输出维特比算法(SOVA)检测器,所述SOVA检测器使用所述一组信道参数作为所述SOVA检测器的分支偏差以执行所述输入信号的所述处理。
19.根据权利要求18所述的方法,还包括所述第一自适应算法是最小均方误差MMSE自适应算法,并且所述第二自适应算法是最小误码率MBER自适应算法。
20.根据权利要求17所述的方法,还包括:
所述输入信号是对应于磁存储介质的扇区的数字化样本序列;
所述第三组信道参数和所述第四组信道参数对应于包括所述扇区并且在制造过程期间生成的所述磁存储介质的区域,所述制造过程包括回读写入包括所述扇区的所述磁存储介质的所述区域的已知数据;并且
所述第三组信道参数与所述第四组信道参数之间的所述关系是差值。
CN201810636877.8A 2017-06-20 2018-06-20 近似参数自适应 Active CN109104200B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762522248P 2017-06-20 2017-06-20
US62/522,248 2017-06-20
US15/793,870 2017-10-25
US15/793,870 US10714134B2 (en) 2017-06-20 2017-10-25 Approximated parameter adaptation

Publications (2)

Publication Number Publication Date
CN109104200A CN109104200A (zh) 2018-12-28
CN109104200B true CN109104200B (zh) 2022-07-01

Family

ID=62683652

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201810616850.2A Active CN109104388B (zh) 2017-06-20 2018-06-15 用于正则化参数自适应的装置、系统和方法
CN201810636877.8A Active CN109104200B (zh) 2017-06-20 2018-06-20 近似参数自适应
CN201810635583.3A Active CN109104204B (zh) 2017-06-20 2018-06-20 用于混合定时恢复的装置、系统和方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201810616850.2A Active CN109104388B (zh) 2017-06-20 2018-06-15 用于正则化参数自适应的装置、系统和方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201810635583.3A Active CN109104204B (zh) 2017-06-20 2018-06-20 用于混合定时恢复的装置、系统和方法

Country Status (4)

Country Link
US (14) US10014026B1 (zh)
CN (3) CN109104388B (zh)
SG (3) SG10201804852XA (zh)
TW (3) TWI701591B (zh)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8595191B2 (en) 2009-12-31 2013-11-26 Commvault Systems, Inc. Systems and methods for performing data management operations using snapshots
US10152457B1 (en) 2016-10-25 2018-12-11 Seagate Technology Llc Target parameter adaptation
US10382166B1 (en) * 2017-02-22 2019-08-13 Seagate Technology Llc Constrained receiver parameter optimization
US10014026B1 (en) 2017-06-20 2018-07-03 Seagate Technology Llc Head delay calibration and tracking in MSMR systems
GB2566760B (en) * 2017-10-20 2019-10-23 Please Hold Uk Ltd Audio Signal
GB2566759B8 (en) 2017-10-20 2021-12-08 Please Hold Uk Ltd Encoding identifiers to produce audio identifiers from a plurality of audio bitstreams
JP6813474B2 (ja) * 2017-12-26 2021-01-13 株式会社東芝 磁気ディスク装置及びリード/ライトオフセット補正方法
US11022511B2 (en) 2018-04-18 2021-06-01 Aron Kain Sensor commonality platform using multi-discipline adaptable sensors for customizable applications
US11018842B1 (en) 2018-07-31 2021-05-25 Seagate Technology Llc Dynamic timing recovery bandwidth modulation for phase offset mitigation
US11016681B1 (en) 2018-07-31 2021-05-25 Seagate Technology Llc Multi-threshold parameter adaptation
US10522177B1 (en) 2018-07-31 2019-12-31 Seagate Technology Llc Disc locked clock-based servo timing
US10803902B1 (en) 2018-08-19 2020-10-13 Seagate Technology Llc Hardware-based read sample averaging
US10460762B1 (en) * 2018-09-04 2019-10-29 Seagate Technology Llc Cancelling adjacent track interference signal with different data rate
US10468060B1 (en) 2018-09-27 2019-11-05 Seagate Technology Llc Cancelling adjacent track interference
CN110554838B (zh) * 2019-06-27 2020-08-14 中南大学 一种基于联合优化回声状态网络的热数据预测方法
JP7439474B2 (ja) * 2019-11-25 2024-02-28 富士電機株式会社 プログラマブルコントローラシステムおよびモジュール
US11366602B2 (en) 2020-06-23 2022-06-21 Western Digital Technologies, Inc. Data storage device with burn-after-read mode
JP2022003598A (ja) * 2020-06-23 2022-01-11 株式会社東芝 磁気ディスク装置及びリード処理方法
US11495248B2 (en) * 2020-06-23 2022-11-08 Fujifilm Corporation Signal processing device, magnetic tape cartridge, magnetic tape reading apparatus, processing method of signal processing device, operation method of magnetic tape reading apparatus, and non-transitory computer-readable storage medium
US11595050B2 (en) * 2021-07-16 2023-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Circuits and methods for a cascade phase locked loop
US11456792B1 (en) * 2021-07-30 2022-09-27 Raytheon Company Intermodulation suppression in phased arrays using volterra filters
US11562767B1 (en) 2021-09-08 2023-01-24 Seagate Technology Llc Multi-sector read offset recovery
US11735220B2 (en) 2021-12-27 2023-08-22 Seagate Technology Llc Phase locking multiple clocks of different frequencies
US11694722B1 (en) 2022-02-15 2023-07-04 Western Digital Technologies, Inc. Data timestamp and read counter for magnetic recording devices
US20240022390A1 (en) * 2022-07-15 2024-01-18 Hughes Network Systems Method and Apparatus for Synchronizing Frequency in remote terminals
CN116055928B (zh) * 2023-04-03 2023-06-02 深圳市紫光同创电子有限公司 一种数据采样方法、装置、电子设备以及存储介质

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1323462A (zh) * 1998-08-14 2001-11-21 夸尔柯姆股份有限公司 用于最大后验概率解码器的存储器体系结构
CN1367622A (zh) * 2000-12-19 2002-09-04 株式会社Ntt都科摩 自适应均衡方法及自适应均衡器
CN101277103A (zh) * 2007-03-31 2008-10-01 索尼德国有限责任公司 自适应滤波器装置和用于确定滤波器系数的方法
CN101577536A (zh) * 2009-06-17 2009-11-11 北京九方中实电子科技有限责任公司 一种改进的lms算法的实现方法
CN102916916A (zh) * 2012-10-23 2013-02-06 华南理工大学 基于最小误码率准则的自适应信道均衡器及其实现方法
CN103825852A (zh) * 2014-01-28 2014-05-28 华南理工大学 一种双模自适应判决反馈均衡模块及其实现方法
US9362955B2 (en) * 2010-09-10 2016-06-07 Trellis Phase Communications, Lp Encoding and decoding using constrained interleaving
CN105745712A (zh) * 2014-01-20 2016-07-06 株式会社日立制作所 信息再生装置、信息再生方法、信息记录装置以及信息记录方法

Family Cites Families (190)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2508491B2 (ja) 1987-09-28 1996-06-19 ソニー株式会社 デ―タ再生装置
JP2653933B2 (ja) 1991-04-30 1997-09-17 富士通株式会社 磁気ディスク装置のオフセット検出方式
US5862192A (en) 1991-12-31 1999-01-19 Lucent Technologies Inc. Methods and apparatus for equalization and decoding of digital communications channels using antenna diversity
US5621769A (en) 1992-06-08 1997-04-15 Novatel Communications Ltd. Adaptive-sequence-estimation apparatus employing diversity combining/selection
MY108838A (en) 1992-07-03 1996-11-30 Koninklijke Philips Electronics Nv Adaptive viterbi detector
KR960012019B1 (ko) 1993-11-18 1996-09-09 엘지전자 주식회사 에이치디티브이(hdtv)의 채널등화기
KR100300954B1 (ko) 1994-09-27 2001-10-22 윤종용 고정각속도방식의디스크재생장치의적응형등화기
US6665308B1 (en) 1995-08-25 2003-12-16 Terayon Communication Systems, Inc. Apparatus and method for equalization in distributed digital data transmission systems
US5970093A (en) 1996-01-23 1999-10-19 Tiernan Communications, Inc. Fractionally-spaced adaptively-equalized self-recovering digital receiver for amplitude-Phase modulated signals
US5742532A (en) 1996-05-09 1998-04-21 The Board Of Trustees Of The Leland Stanford Junior University System and method for generating fractional length delay lines in a digital signal processing system
US6633894B1 (en) 1997-05-08 2003-10-14 Legerity Inc. Signal processing arrangement including variable length adaptive filter and method therefor
US6377552B1 (en) 1997-08-29 2002-04-23 Motorola, Inc. System, device, and method for evaluating dynamic range in a communication system
WO1999019785A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Apparatus and method for generating a distributed clock signal using gear ratio techniques
US6222592B1 (en) 1998-01-13 2001-04-24 Samsung Electronics Co., Ltd. TV receiver equalizer storing channel characterizations for each TV channel between times of reception therefrom
US6111712A (en) 1998-03-06 2000-08-29 Cirrus Logic, Inc. Method to improve the jitter of high frequency phase locked loops used in read channels
US6157510A (en) 1998-03-10 2000-12-05 Maxtor Corporation Magnetic storage device with multiple read elements which are offset laterally and longitudinally
FI104772B (fi) 1998-03-23 2000-03-31 Nokia Networks Oy Itseoptimoiva kanavakorjaus- ja ilmaisumenetelmä ja itseoptimoiva kanavakorjain/ilmaisin
JP2000048488A (ja) 1998-07-27 2000-02-18 Pioneer Electron Corp クロストーク除去回路を有する記録情報再生装置
JP3226499B2 (ja) 1998-09-25 2001-11-05 富士通株式会社 記憶ディスク装置のヘッド位置決め制御方法及びその装置
US6320920B1 (en) 1998-10-08 2001-11-20 Gregory Lee Beyke Phase coherence filter
US6597745B1 (en) * 1999-04-06 2003-07-22 Eric M. Dowling Reduced complexity multicarrier precoder
US6549587B1 (en) 1999-09-20 2003-04-15 Broadcom Corporation Voice and data exchange over a packet based network with timing recovery
US6181213B1 (en) 1999-06-14 2001-01-30 Realtek Semiconductor Corp. Phase-locked loop having a multi-phase voltage controlled oscillator
FR2796487B1 (fr) * 1999-06-28 2001-10-12 St Microelectronics Sa Procede et dispositif pour l'asservissement d'un faisceau optique incident sur une piste d'un support mobile d'informations, en particulier un disque numerique a vitesse de rotation elevee
US6519107B1 (en) 1999-09-24 2003-02-11 Maxtor Corporation Hard disk drive having self-written servo burst patterns
US6505222B1 (en) 1999-10-29 2003-01-07 International Business Machines Corporation Systems methods and computer program products for controlling undesirable bias in an equalizer
US7324437B1 (en) 1999-11-27 2008-01-29 Deutsche Telekom Ag Method for co-channel interference cancellation in a multicarrier communication system
US6760371B1 (en) 2000-03-22 2004-07-06 The Boeing Company Method and apparatus implementation of a zero forcing equalizer
US7133239B1 (en) 2000-05-09 2006-11-07 Maxtor Corporation Methods and apparatuses for writing spiral servo patterns onto a disk surface
US6581182B1 (en) 2000-05-15 2003-06-17 Agere Systems Inc. Iterative decoding with post-processing of detected encoded data
US7245638B2 (en) * 2000-07-21 2007-07-17 Broadcom Corporation Methods and systems for DSP-based receivers
CN1276595C (zh) 2000-08-30 2006-09-20 松下电器产业株式会社 数据传送装置、无线电通信系统及无线电通信方法
US7133233B1 (en) 2000-10-24 2006-11-07 Maxtor Corporation Disk drive with read while write capability
US7046701B2 (en) 2000-11-03 2006-05-16 Qualcomm Inc. System, method, and apparatus for fractional delay
US6697891B2 (en) 2001-01-16 2004-02-24 Hitachi Global Storage Technologies Netherlands B.V. Parallel read/write circuit and method for efficient storing/retrieval of data to/from a recording medium
JP4487433B2 (ja) 2001-03-02 2010-06-23 ヤマハ株式会社 記録媒体記録装置
SG96277A1 (en) 2001-03-23 2003-05-23 Toshiba Kk Magnetic disk drive apparatus having a self-servo writing system and method for writing servo pattern therein
US6738205B1 (en) 2001-07-08 2004-05-18 Maxtor Corporation Self-writing of servo patterns in disk drives
US6670901B2 (en) 2001-07-31 2003-12-30 Motorola, Inc. Dynamic range on demand receiver and method of varying same
US6687073B1 (en) 2001-08-31 2004-02-03 Western Digital Technologies, Inc. Method of simultaneously writing servo tracks on a hard disk drive
US7440208B1 (en) 2001-09-21 2008-10-21 Maxtor Corporation Flexible partial response targets for data detectors
US6993291B2 (en) 2001-10-11 2006-01-31 Nokia Corporation Method and apparatus for continuously controlling the dynamic range from an analog-to-digital converter
US7085330B1 (en) 2002-02-15 2006-08-01 Marvell International Ltd. Method and apparatus for amplifier linearization using adaptive predistortion
TW591613B (en) 2002-03-26 2004-06-11 Via Tech Inc Method and related device for achieving stable writing state of compact disk driver by adjusting writing clock
JP3816050B2 (ja) 2002-04-23 2006-08-30 松下電器産業株式会社 信号処理装置
TW587882U (en) * 2002-05-01 2004-05-11 Interdigital Tech Corp Node-B capable of supporting point to multi-point services using high speed channels
TW200413907A (en) * 2002-08-29 2004-08-01 Motorola Inc Storage system with memory for storing data
BR0215941A (pt) * 2002-11-15 2005-09-06 Telecom Italia Spa Método para sincronização fina de um receptor de telecomunicação digital, e, receptor de comunicação digital
US7180963B2 (en) 2002-11-25 2007-02-20 Ali Corporation Digital receiver capable of processing modulated signals at various data rates
US7830956B2 (en) * 2003-02-05 2010-11-09 Fujitsu Limited Method and system for processing a sampled signal
US7324589B2 (en) * 2003-02-05 2008-01-29 Fujitsu Limited Method and system for providing error compensation to a signal using feedback control
US7245448B2 (en) 2003-02-20 2007-07-17 Fujitsu Limited Information recording apparatus and data writing control device therefor
US7324561B1 (en) * 2003-06-13 2008-01-29 Silicon Clocks Inc. Systems and methods for generating an output oscillation signal with low jitter
JP2005135563A (ja) 2003-10-31 2005-05-26 Sanyo Electric Co Ltd 適応等化器
KR20060127132A (ko) 2004-01-14 2006-12-11 루미넥스 코포레이션 동작범위 확장 방법 및 시스템
CN1281003C (zh) * 2004-02-26 2006-10-18 上海交通大学 基于导频矩阵的时域自适应信道估计方法
US7184233B2 (en) 2004-06-04 2007-02-27 Quantum Corporation Dual source tracking servo systems and associated methods
US7333280B1 (en) * 2004-08-03 2008-02-19 Western Digital Technologies, Inc. Servo writing a disk drive by synchronizing a servo write clock to a reference pattern on the disk and compensating for repeatable phase error
US7271971B2 (en) * 2004-12-03 2007-09-18 International Business Machines Corporation Dynamically adapting a magnetic tape read channel equalizer
JP2006172586A (ja) 2004-12-15 2006-06-29 Hitachi Global Storage Technologies Netherlands Bv 磁気ディスク装置
EP1849236A1 (en) * 2004-12-29 2007-10-31 Intel Corporation Channel estimation and fixed thresholds for multi-threshold decoding of low-density parity check codes
US7333279B2 (en) 2005-03-22 2008-02-19 Seagate Technology Llc System and method for drive-side guarantee of quality of service and for extending the lifetime of storage devices
US7375562B2 (en) * 2005-03-25 2008-05-20 Faraday Technology Corp. Phase locked system for generating distributed clocks
US7256876B1 (en) * 2005-07-14 2007-08-14 At&T Corp. Estimating optical transmission system penalties induced by polarization mode dispersion (PMD)
US8160181B1 (en) 2005-10-24 2012-04-17 Marvell International Ltd. Nonlinear detectors for channels with signal-dependent noise
US7529052B2 (en) 2005-12-19 2009-05-05 Broadcom Corporation Disk controller and methods for use therewith
US7474487B2 (en) 2005-12-19 2009-01-06 Broadcom Corporation Read/write timing generator and methods for use therewith
US7813421B2 (en) * 2006-01-17 2010-10-12 Marvell World Trade Ltd. Order recursive computation for a MIMO equalizer
US7433142B2 (en) 2006-02-01 2008-10-07 International Business Machines Corporation Using at least one servo channel to provide timing recovery and timing information to data channels
EP2035999A4 (en) * 2006-04-11 2009-07-01 Mathconsult Gmbh MATHEMATICAL DESIGN OF ION CHANNEL SELECTIVITY BY TECHNOLOGY OF INVERSE PROBLEMS
CN1866945A (zh) * 2006-05-11 2006-11-22 上海交通大学 Ofdm系统中基于可变遗忘因子的rls信道估计方法
US20080007855A1 (en) 2006-07-10 2008-01-10 Broadcom Corporation, A California Corporation Phase offset correction for timing recovery with use of ECC in a read channel for a disk drive
US8441751B1 (en) 2006-08-18 2013-05-14 Marvell International Ltd. Dibit pulse extraction methods and systems
US7940667B1 (en) 2006-09-13 2011-05-10 Pmc-Sierra Us, Inc. Delay measurements and calibration methods and apparatus for distributed wireless systems
KR100901787B1 (ko) 2006-12-15 2009-06-11 서강대학교기술지주 주식회사 후치필터링을 이용한 분수지연 필터 기반의 빔집속 장치 및 방법
US7715143B2 (en) 2006-12-31 2010-05-11 Broadcom Corporation Delta-sigma PLL using fractional divider from a multiphase ring oscillator
US7616685B2 (en) 2007-01-19 2009-11-10 Techwell, Inc. Method for channel tracking in an LMS adaptive equalizer for 8VSB
US7787550B2 (en) 2007-07-24 2010-08-31 Texas Instruments Incorporated Combined frame alignment and timing recovery in digital subscriber line (DSL) communications systems
US7733592B2 (en) * 2007-10-11 2010-06-08 International Business Machines Corporation Methods for multi-channel data detection phase locked loop frequency error combination
JP2009134806A (ja) * 2007-11-30 2009-06-18 Fujitsu Ltd ヘッドic、リード回路及び媒体記憶装置
US7948703B1 (en) 2008-01-30 2011-05-24 Marvell International Ltd. Adaptive target optimization methods and systems for noise whitening based viterbi detectors
US8102938B2 (en) 2008-04-22 2012-01-24 Finisar Corporation Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator
US7929237B2 (en) 2008-06-27 2011-04-19 Agere Systems Inc. Modulated disk lock clock and methods for using such
US8027117B1 (en) 2008-08-25 2011-09-27 Marvell International Ltd. Zone servo writing using self servo writing
US8296637B1 (en) 2008-09-22 2012-10-23 Marvell International Ltd. Channel quality monitoring and method for qualifying a storage channel using an iterative decoder
US7929238B1 (en) 2008-10-14 2011-04-19 Western Digital Technologies, Inc. Disk drive seeking with a fixed rate clock when crossing servo zones to facilitate zoned servo sectors
CN101478510B (zh) * 2009-02-17 2013-06-19 上海高清数字科技产业有限公司 一种自适应均衡器及使用该均衡器的接收机系统
US8040631B2 (en) 2009-05-18 2011-10-18 Seagate Technology Llc Servo processors that alternately control head positioning relative to sequential servo patterns
CN101932001B (zh) * 2009-06-24 2013-08-21 中兴通讯股份有限公司 一种自适应调制编码方法
JP2011014196A (ja) 2009-07-02 2011-01-20 Renesas Electronics Corp 適応等化器、情報再生装置、及び適応等化方法
US8139301B1 (en) * 2009-07-22 2012-03-20 Western Digital (Fremont), Llc Disk drive comprising a dual read element and delay circuitry to improve read signal
EP2302811B1 (en) * 2009-08-18 2013-03-27 Telefonaktiebolaget L M Ericsson (Publ) Soft output viterbi algorithm method and decoder
US8312359B2 (en) 2009-09-18 2012-11-13 Lsi Corporation Branch-metric calibration using varying bandwidth values
US8331050B1 (en) 2009-09-25 2012-12-11 Marvell International Ltd. Patterned magnetic media synchronization systems
TWI396089B (zh) * 2009-10-16 2013-05-11 Moxa Inc 以參數提供多通道傳輸串列資料之裝置及其方法
US20110090773A1 (en) 2009-10-16 2011-04-21 Chih-Ching Yu Apparatus for generating viterbi-processed data using an input signal obtained from reading an optical disc
US20110176400A1 (en) 2010-01-19 2011-07-21 Gerasimov Anton L Method of servo spiral switching during self servo-write for a disk drive
US8508879B1 (en) * 2010-01-21 2013-08-13 Marvell International Ltd. Write clock rephase for magnetic recording device
US8400726B1 (en) 2010-01-28 2013-03-19 Link—A—Media Devices Corporation Controlling preamble target amplitude
US8713413B1 (en) 2010-02-09 2014-04-29 Sk Hynix Memory Solutions Inc. Generation of interpolated samples for decision based decoding
WO2011121948A1 (ja) 2010-03-29 2011-10-06 パナソニック株式会社 光ディスク記録装置及び記録信号生成装置
US8542766B2 (en) 2010-05-04 2013-09-24 Samsung Electronics Co., Ltd. Time alignment algorithm for transmitters with EER/ET amplifiers and others
JP4852166B1 (ja) * 2010-08-04 2012-01-11 シャープ株式会社 移動局装置、通信システム、通信方法および集積回路
JP5582954B2 (ja) 2010-10-12 2014-09-03 ルネサスエレクトロニクス株式会社 デジタルpll回路、情報再生装置、ディスク再生装置および信号処理方法
US8665543B2 (en) 2010-10-29 2014-03-04 Sk Hynix Memory Solutions Inc. Inter-track interference cancelation for shingled magnetic recording
US8842750B2 (en) 2010-12-21 2014-09-23 Intel Corporation Channel estimation for DVB-T2 demodulation using an adaptive prediction technique
US20120166953A1 (en) * 2010-12-23 2012-06-28 Microsoft Corporation Techniques for electronic aggregation of information
WO2012127637A1 (ja) 2011-03-22 2012-09-27 富士通株式会社 クロック生成回路及びクロック生成回路制御方法
US9124277B2 (en) 2011-04-20 2015-09-01 Freescale Semiconductor, Inc. System and method for clock signal generation
US8539328B2 (en) 2011-08-19 2013-09-17 Lsi Corporation Systems and methods for noise injection driven parameter selection
US8456230B2 (en) 2011-09-22 2013-06-04 Lsi Corporation Adaptive filter with coefficient determination based on output of real time clock
US8479086B2 (en) 2011-10-03 2013-07-02 Lsi Corporation Systems and methods for efficient parameter modification
JP2013149306A (ja) * 2012-01-18 2013-08-01 Toshiba Corp 信号処理回路、信号処理方法、及び磁気ディスク装置
US8923137B2 (en) 2012-02-06 2014-12-30 Qualcomm Incorporated System and method for information verification based on channel awareness
US9077349B2 (en) * 2012-02-21 2015-07-07 Qualcomm Incorporated Automatic detection and compensation of frequency offset in point-to-point communication
US9357517B2 (en) * 2012-06-12 2016-05-31 Marvell World Trade Ltd. Apparatus and method for wireless baseband processing
US8780477B1 (en) 2012-06-21 2014-07-15 Western Digital Technologies, Inc. Disk drive adjusting servo timing to compensate for transient when crossing a servo zone boundary
US8724245B1 (en) 2012-06-21 2014-05-13 Western Digital Technologies, Inc. Disk drive employing overlapping servo zones to facilitate servo zone crossing
SG196730A1 (en) * 2012-07-16 2014-02-13 Agency Science Tech & Res Methods for reading data from a storage medium using a reader and storage devices
US9239754B2 (en) * 2012-08-04 2016-01-19 Seagate Technology Llc Single read based soft-decision decoding of non-volatile memory
EP2712136B1 (en) * 2012-09-20 2015-02-25 Nxp B.V. Channel frequency response estimation and tracking for time- and frequency varying communication channels
US9385757B1 (en) 2012-09-27 2016-07-05 Marvell International Ltd. Systems and methods for using a non-binary soft output viterbi algorithm
US9189379B2 (en) 2013-02-06 2015-11-17 Avago Technologies General Ip (Singapore) Pte. Ltd. Buffer for managing data samples in a read channel
US9246668B1 (en) * 2013-03-12 2016-01-26 Marvell International Ltd. Unified control for digital timing recovery and packet processing
US9093115B1 (en) 2013-03-15 2015-07-28 Seagate Technology Llc Track interference cancellation
EP2992654B1 (en) * 2013-05-15 2017-12-27 Huawei Technologies Co., Ltd. Low complexity, adaptive, fractionally spaced equalizer with non-integer sampling
US8760794B1 (en) 2013-05-16 2014-06-24 HGST Netherlands B.V. Servo systems with augmented servo bursts
US8767341B1 (en) 2013-05-16 2014-07-01 HGST Netherlands B.V. Servo systems with augmented servo bursts
US9544168B2 (en) 2013-06-06 2017-01-10 Pioneer Corporation Channel estimation device, receiving device, channel estimation method, channel estimation program, and recording medium
US9165597B2 (en) 2013-06-28 2015-10-20 Seagate Technology Llc Time-multiplexed single input single output (SISO) data recovery channel
WO2015009718A1 (en) * 2013-07-16 2015-01-22 Marvell World Trade Ltd. Systems and methods for calibrating read and write operations in two dimensional magnetic recording
US9129650B2 (en) * 2013-07-25 2015-09-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Array-reader based magnetic recording systems with frequency division multiplexing
CN103476026B (zh) * 2013-09-06 2017-01-18 中国科学院软件研究所 基于卫星信道编码的自适应隐蔽通信方法
US9064537B1 (en) 2013-09-13 2015-06-23 Western Digital Technologies, Inc. Disk drive measuring radial offset between heads by detecting a difference between ramp contact
CN103560984B (zh) * 2013-10-31 2017-12-15 北京工业大学 基于多模型加权软切换的信道自适应估计方法
US9245578B1 (en) 2013-11-26 2016-01-26 Western Digital Technologies, Inc. Disk drive compensating for inter-track interference in analog read signal
US9257145B1 (en) * 2013-11-27 2016-02-09 Western Digital Technologies, Inc. Disk drive measuring down-track spacing of read sensors
JP2015122632A (ja) * 2013-12-24 2015-07-02 富士通株式会社 光通信受信装置
US9245579B2 (en) * 2013-12-27 2016-01-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Two-dimensional magnetic recording reader offset estimation
US9025269B1 (en) 2014-01-02 2015-05-05 Western Digital Technologies, Inc. Disk drive compensating for cycle slip of disk locked clock when reading mini-wedge
US9645763B2 (en) 2014-01-13 2017-05-09 Seagate Technology Llc Framework for balancing robustness and latency during collection of statistics from soft reads
US9099132B1 (en) * 2014-02-25 2015-08-04 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for multi-head separation determination
US9280995B2 (en) 2014-03-28 2016-03-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Locking a disk-locked clock using timestamps of successive servo address marks in a spiral servo track
US8861111B1 (en) * 2014-04-01 2014-10-14 Lsi Corporation Two dimensional magnetic recording servo system phase alignment
US9019642B1 (en) 2014-04-02 2015-04-28 Lsi Corporation Synchronization mark detection for multi-dimensional magnetic recording
US8837068B1 (en) * 2014-04-14 2014-09-16 Lsi Corporation Two dimensional magnetic recording servo system adaptive combination
US8861112B1 (en) * 2014-04-23 2014-10-14 Lsi Corporation Two dimensional magnetic recording system head separation estimator
US20150341158A1 (en) * 2014-05-23 2015-11-26 Mediatek Inc. Loop gain calibration apparatus for controlling loop gain of timing recovery loop and related loop gain calibration method
US8953276B1 (en) 2014-06-05 2015-02-10 Seagate Technology Llc Correcting position error based on reading first and second user data signals
US9417797B2 (en) 2014-06-09 2016-08-16 Seagate Technology Llc Estimating read reference voltage based on disparity and derivative metrics
US9431052B2 (en) * 2014-06-26 2016-08-30 Marvell World Trade Ltd. Two dimensional magnetic recording systems, devices and methods
US9196298B1 (en) * 2014-06-30 2015-11-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Zero phase start for array reader magnetic recording system
CN104052691B (zh) * 2014-07-02 2017-02-15 东南大学 基于压缩感知的mimo‑ofdm系统信道估计方法
US9117470B1 (en) 2014-07-17 2015-08-25 International Business Machines Corporation Write delay to de-skew data in read while write function for tape storage devices
US9007707B1 (en) * 2014-10-31 2015-04-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for accessing codewords in parallel using a three sensor reader
US9245580B1 (en) * 2014-10-31 2016-01-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for three reader storage access
US9680484B2 (en) * 2014-12-05 2017-06-13 Texas Instruments Incorporated Clock conditioner circuitry with improved holdover exit transient performance
US9690361B2 (en) * 2014-12-24 2017-06-27 Intel Corporation Low-power context-aware control for analog frontend
US9424878B1 (en) * 2015-02-04 2016-08-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Two dimensional magnetic recording head separation calculator
US9401161B1 (en) 2015-03-11 2016-07-26 Seagate Technology Llc Magnetic read head with multiple read transducers each having different design characteristics
US9286915B1 (en) 2015-03-12 2016-03-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for format efficient sector fragment processing
US9508369B2 (en) 2015-03-13 2016-11-29 Seagate Technology Llc Defining a maximum sequential write duration for a data storage device utilizing heat-assisted recording
US9311959B1 (en) 2015-03-30 2016-04-12 Seagate Technology Llc Read channel optimization using multi-dimensional smoothing
US9489976B2 (en) 2015-04-06 2016-11-08 Seagate Technology Llc Noise prediction detector adaptation in transformed space
US9590803B2 (en) * 2015-05-22 2017-03-07 Seagate Technology Llc Timing error processor that uses the derivative of an interpolator function
CN106201333B (zh) 2015-06-01 2019-04-12 株式会社东芝 存储装置、控制器以及数据再读出方法
CN105050137B (zh) * 2015-06-18 2019-06-28 西安电子科技大学 一种基于信息物理系统模型的车联网拥塞控制方法
US9564157B1 (en) 2015-08-21 2017-02-07 Seagate Technology Llc System and method for detecting reader-writer offset in a heat-assisted magnetic recording head
US10347343B2 (en) 2015-10-30 2019-07-09 Seagate Technology Llc Adaptive read threshold voltage tracking with separate characterization on each side of voltage distribution about distribution mean
US10192614B2 (en) 2015-10-30 2019-01-29 Seagate Technology Llc Adaptive read threshold voltage tracking with gap estimation between default read threshold voltages
US9542972B1 (en) 2015-11-12 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for multi-head coefficient based scaling
US9837990B1 (en) 2015-12-11 2017-12-05 Syntropy Systems, Llc Digital signal processor
US10043582B2 (en) 2016-02-11 2018-08-07 Seagate Technology Llc Establishing parameters of subsequent read retry operations based on syndrome weights of prior failed decodings
US9536563B1 (en) 2016-02-16 2017-01-03 Seagate Technology Llc Detecting shingled overwrite errors
US10445171B2 (en) 2016-02-29 2019-10-15 Seagate Technology Llc On-the-fly error detection algorithm during retry procedure
CN105656819B (zh) * 2016-03-21 2018-12-18 电子科技大学 一种基于压缩感知和大规模mimo的自适应信道估计方法
CN105812299B (zh) * 2016-04-22 2020-05-15 中国地质大学(武汉) 基于联合块稀疏重构的无线传感网信道估计方法
US9947362B1 (en) 2016-06-25 2018-04-17 Seagate Technology Llc Asynchronous interference cancellation
US10290358B2 (en) 2016-07-08 2019-05-14 Seagate Technology Llc Independent read threshold voltage tracking for multiple dependent read threshold voltages using syndrome weights
US10180868B2 (en) 2016-07-08 2019-01-15 Seagate Technology Llc Adaptive read threshold voltage tracking with bit error rate estimation based on non-linear syndrome weight mapping
US9819456B1 (en) 2016-10-17 2017-11-14 Seagate Technology Llc Preamble detection and frequency offset determination
US10164760B1 (en) * 2016-10-18 2018-12-25 Seagate Technology Llc Timing excursion recovery
US10152457B1 (en) 2016-10-25 2018-12-11 Seagate Technology Llc Target parameter adaptation
US9998136B1 (en) * 2017-02-17 2018-06-12 Seagate Technology Llc Loop consistency using multiple channel estimates
JP2018160302A (ja) 2017-03-23 2018-10-11 株式会社東芝 ストレージ装置及びコントローラ
US10014026B1 (en) 2017-06-20 2018-07-03 Seagate Technology Llc Head delay calibration and tracking in MSMR systems
US10388368B2 (en) 2017-10-31 2019-08-20 Seagate Technology Llc Adaptive read threshold voltage tracking with charge leakage mitigation using charge leakage settling time
US10276233B1 (en) 2017-10-31 2019-04-30 Seagate Technology Llc Adaptive read threshold voltage tracking with charge leakage mitigation using threshold voltage offsets
US10297281B1 (en) 2017-11-06 2019-05-21 Seagate Technology Llc Servo sector detection
US10498565B1 (en) 2018-09-05 2019-12-03 Macom Technology Solutions Holding, Inc Sampling phase optimization for digital modulated signals

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1323462A (zh) * 1998-08-14 2001-11-21 夸尔柯姆股份有限公司 用于最大后验概率解码器的存储器体系结构
CN1367622A (zh) * 2000-12-19 2002-09-04 株式会社Ntt都科摩 自适应均衡方法及自适应均衡器
CN101277103A (zh) * 2007-03-31 2008-10-01 索尼德国有限责任公司 自适应滤波器装置和用于确定滤波器系数的方法
CN101577536A (zh) * 2009-06-17 2009-11-11 北京九方中实电子科技有限责任公司 一种改进的lms算法的实现方法
US9362955B2 (en) * 2010-09-10 2016-06-07 Trellis Phase Communications, Lp Encoding and decoding using constrained interleaving
CN102916916A (zh) * 2012-10-23 2013-02-06 华南理工大学 基于最小误码率准则的自适应信道均衡器及其实现方法
CN105745712A (zh) * 2014-01-20 2016-07-06 株式会社日立制作所 信息再生装置、信息再生方法、信息记录装置以及信息记录方法
CN103825852A (zh) * 2014-01-28 2014-05-28 华南理工大学 一种双模自适应判决反馈均衡模块及其实现方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Signal processing for high speed underwater acoustic transmission of image;《Chinese Journal of Acoustics》;20090115(第01期);255-258 *
Turbo码SOVA译码的一种新的改进算法;谢仁宏等;《信号处理》;20040630(第03期);131-135 *
高码率自适应Turbo编译码器的设计与FPGA实现;黄懿等;《电讯技术》;20080328(第03期);117-130 *

Also Published As

Publication number Publication date
US10665256B2 (en) 2020-05-26
CN109104204B (zh) 2020-09-22
US10177771B1 (en) 2019-01-08
US20180367164A1 (en) 2018-12-20
US20200005819A1 (en) 2020-01-02
US20180366155A1 (en) 2018-12-20
US20200065262A1 (en) 2020-02-27
US10410672B1 (en) 2019-09-10
CN109104204A (zh) 2018-12-28
US11361788B2 (en) 2022-06-14
US10496559B1 (en) 2019-12-03
US10469290B1 (en) 2019-11-05
TW201907293A (zh) 2019-02-16
US10276197B2 (en) 2019-04-30
TW201905682A (zh) 2019-02-01
US10936003B1 (en) 2021-03-02
SG10201805246XA (en) 2019-01-30
US10755734B2 (en) 2020-08-25
TW201907260A (zh) 2019-02-16
US20180366149A1 (en) 2018-12-20
US10607648B1 (en) 2020-03-31
TWI701591B (zh) 2020-08-11
US10714134B2 (en) 2020-07-14
US20180366156A1 (en) 2018-12-20
CN109104388A (zh) 2018-12-28
US10014026B1 (en) 2018-07-03
US10157637B1 (en) 2018-12-18
SG10201805247VA (en) 2019-01-30
CN109104200A (zh) 2018-12-28
SG10201804852XA (en) 2019-01-30
CN109104388B (zh) 2021-06-11
TWI691899B (zh) 2020-04-21
US10068608B1 (en) 2018-09-04

Similar Documents

Publication Publication Date Title
CN109104200B (zh) 近似参数自适应
US8719682B2 (en) Adaptive calibration of noise predictive finite impulse response filter
US20120207201A1 (en) Systems and Methods for Data Detection Using Distance Based Tuning
US8797666B2 (en) Adaptive maximum a posteriori (MAP) detector in read channel
US10608808B1 (en) Iterative recovery from baseline or timing disturbances
US9118348B2 (en) Decoding apparatus, storage apparatus, and decoding method
US9252989B2 (en) Data-dependent equalizer circuit
EP2665191B1 (en) Systems and methods for dual binary and non-binary decoding
US20130332790A1 (en) LDPC Decision Driven Equalizer Adaptation
US10790933B1 (en) Constrained receiver parameter optimization
US8751915B2 (en) Systems and methods for selectable positive feedback data processing
US8824076B2 (en) Systems and methods for NPML calibration
US8880986B2 (en) Systems and methods for improved data detection processing
US8654474B2 (en) Initialization for decoder-based filter calibration
US9430270B2 (en) Systems and methods for multiple sensor noise predictive filtering
US8625217B1 (en) Branch metric computation and noise predictive calibration/adaptation for over-sampled Y samples
US8848308B2 (en) Systems and methods for ADC sample based inter-track interference compensation
US11016681B1 (en) Multi-threshold parameter adaptation
US8782488B2 (en) Systems and methods for back step data decoding
US11223447B1 (en) Multiple detector data channel and data detection utilizing different cost functions
US8902525B1 (en) Systems and methods for indirect parameter calibration in a data processing system
US8694847B2 (en) Systems and methods for sector quality determination in a data processing system
US8917467B1 (en) Systems and methods for ATI mitigation
US8867154B1 (en) Systems and methods for processing data with linear phase noise predictive filter
US20130219233A1 (en) Systems and Methods for Quality Based Priority Data Processing

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant