CN109075155B - 封装电路系统结构 - Google Patents
封装电路系统结构 Download PDFInfo
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Abstract
一种封装电路系统结构,具有嵌入到体材料(322)中的电路元件(301,304)。嵌入的电路元件(301,304)中的至少一个形成包括与结构的一侧(324)的信号地电位(350)的电连接和与结构的另一侧的导电层(316)的电连接的双耦接。导电层在未形成双耦接的至少一个嵌入的电路元件(304)上方延伸,从而为其提供有效的EMI屏蔽。
Description
技术领域
本公开内容涉及电路系统,尤其涉及包括两个或更多个电路元件的封装电路系统。本公开内容还涉及用于制造包括两个或更多个电路元件的封装电路系统的方法。
背景技术
电磁(EM)场被定义为由电荷运动引起的空间特性(大英百科全书)。静止的电荷在周围空间中产生电场,并且当电荷正在移动时,还产生磁场。也可以通过变化的磁场产生电场。电场和磁场的相互作用产生电磁场。
在空间中的人造和自然的电磁场源都会干扰电气设备的运行。例如,在汽车系统中使用的传感器暴露于各种变化的场,并且需要被有效屏蔽以避免电磁干扰(EMI)。通常,通过用由导电或磁性材料制成的屏障阻挡EM场来隔离设备。例如,传统的微机电系统(MEMS)设备通常包括MEMS管芯和集成电路(IC)管芯,并且通过在组装的MEMS和IC管芯的每一侧具有金属层来实现所需的屏蔽。在预模制的塑料封装中,通常通过在组件的一侧具有引线框架(管芯焊盘(die pad))和在组件的另一侧具有接地的盖子来实现屏蔽。超模压的塑料封装主要使用所谓的倒装管芯焊盘,其中屏蔽由一侧的管芯焊盘提供以及由另一侧的印刷布线板(PWB)上的金属化提供。
近年来,还发展了许多无引线封装技术,以使制造过程流水线化并减小封装尺寸。然而,已建立的无引线封装技术尚未在具有挑战性的条件下——在汽车应用中是典型的——为EMI屏蔽提供适当的解决方案。
发明内容
本公开内容的目的是引入以简单的方式为嵌入的电路元件提供有效的EMI屏蔽的封装电路系统结构。
本公开内容的目的通过特征在于独立权利要求中所陈述的内容的封装电路系统结构和制造方法来实现。在从属权利要求中公开了本公开内容的优选实施方式。
在解决方案中,通常暴露于外部EM场的一侧至少部分地用导电层覆盖,并且嵌入的电路元件中的一个被布置成形成通过嵌入用体材料的双耦接(double coupling),从而将导电层和信号地电位耦接。因此,处于信号地电位的导电层向被其覆盖的电路元件提供有效的EMI屏蔽。改进的EMI屏蔽可以用简单的结构元件以易于制造的方式来实施。
附图说明
在下文中,将参照附图借助优选的实施方式更详细地描述本公开内容,在附图中:
图1示出典型的现有技术的封装电路系统结构;
图2示出在焊接到印刷布线板的焊接组件中的图1的结构;
图3示出改进的封装电路系统结构的实施方式;
图4示出封装电路系统结构的另一实施方式;
图5示出封装电路系统结构的又一实施方式;
图6示出用于制造改进的封装电路系统结构的方法的各个阶段;
图7示出由封装电路系统结构内的连接路径形成的电路的方案;以及
图8示出说明在连接路径中电阻的影响的曲线。
具体实施方式
以下实施方式是示例性的。虽然说明书可能会提及“一”、“一个”或“一些”实施方式,但这并不一定意味着每个这样的提及是针对相同的实施方式,或者特征仅适用于单个实施方式。可以组合不同实施方式的单个特征以提供更多实施方式。
在下文中,将利用可以实施本发明的各种实施方式的设备架构的简单示例来描述本发明的特征。仅详细描述了与说明实施方式相关的元件。本领域的技术人员通常已知的集成设备的各种部件可能在本文中不具体描述。
图1的示意图示出典型的现有技术的封装电路系统结构。结构包括可能不同来源(不同的晶圆、设计、技术)的一个或更多个电路元件(管芯)。图1示出示例性扇出晶圆级封装(FO-WLP)器件,即可以通过将电路元件嵌入体材料(bulk material)中形成的集成器件100。电路元件可以包括嵌入低成本塑料材料106中的一个或更多个IC管芯101、一个或更多个其他元件104以及一个或更多个导电通孔形成部分105。其他元件104可以包括例如MEMS管芯或无源部件,如光学元件、任何其他电气部件或子组件。
IC管芯101通常包括衬底部分103和具有IC管芯的电路特征和接触焊盘的表面部分102。IC管芯101的表面部分102和其他嵌入的元件104的接触表面被类似地定向在集成器件100的一个表面上或对准集成器件100的一个表面。该一个表面可以由绝缘体和形成再分布层(RDL)107的导体层的组合覆盖。RDL被配置成选择性地提供到与RDL的导电部分相接触的元件的连接。外部连接元件例如焊料凸起108通常被制造在RDL的顶部,在也能够与RDL的导电部分相接触的位置。因此,RDL选择性地提供在元件层的电路元件与集成器件100的外部连接元件108之间的连接。管芯的背面可以嵌入塑料中(如其他元件104和IC管芯101)或可以延伸至与集成器件的后表面对准(如导电通孔形成部分105)。由于扇出晶圆级封装(FO-WLP)器件从较大的实体切块而成,FO-WLP器件的竖向侧面是低成本塑料材料106,并因而不包括任何功能结构,如导电引线。
图2示出在焊接到印刷布线板(PWB)206的焊接组件中的图1的集成FO-WLP器件100。变化的外部电场对集成器件的影响由AC电压源215说明。虚拟电压源215到嵌入的管芯104、101中的每一个的电容耦合分别由电容213和214说明。IC管芯101的衬底部分103通常连接至表示集成器件的信号的地电位的电位。在图2中,IC管芯101的表面部分102被示出为包括与衬底部分103电接触的接触焊盘212。该接触焊盘212与作为RDL 107的一部分的接触区域和布线211对准。接触区域和布线211连接至PWB 206上的信号地250或等效电位。再分布层RDL 107因此提供与信号地电位250的电连接。
在这种配置中,IC管芯101的衬底103为IC管芯的电路部分102形成天然EMI屏蔽。然而,其他电路元件104,如MEMS管芯、无源器件和/或电气子组件,不具有这种天然屏蔽。嵌入的管芯的总体积可以连接至相对高的阻抗216(例如,经由集成器件100的RDL 107、IC管芯101的电路部分103、焊料凸起209和PWB 206,或者经由集成器件100的RDL 107、焊料凸起208、PWB 206和连接至PWB的外部阻抗)。在这种情况下,电压源215的一部分电压出现在电路元件和信号地之间。所述电压部分的大小取决于电容213和阻抗216的分压。该电压部分有时可能足够高,从而由于EMI而不利地影响集成器件的操作。
图3示出改进的封装电路系统结构的实施方式,其提供对嵌入的电路元件的改进的EMI屏蔽,并有助于避免所描述的EMI影响。封装电路系统结构在下文中称为集成器件300。变化的外部电场对集成器件的影响再次由电压源315说明。到嵌入的管芯304、301中的每一个的虚拟电压源315的电容耦合分别由电容313和317进一步说明。集成器件300包括其中电路元件301、304嵌入体材料322中的电路层320。集成器件300还包括外部连接元件308、309和如上所描述的被配置成选择性地提供在元件层的电路元件301、304与外部连接元件308、309之间的连接的再分布层310。让我们表示封装电路系统结构具有包括外部连接元件308、309的第一侧324。集成器件300还包括位于集成器件的第二侧的导电层316。第二侧是集成器件的与第一侧相对的一侧。导电层316至少部分地覆盖第二侧的表面。在图3的示例中,导电层覆盖第二侧的整个表面。在FO-WLP器件的情况下,集成器件300的在第一侧324和第二侧之间的侧面为体材料322。换句话说,集成器件300的在第一表面和第二表面之间的外表面不包括在导电层和再分布层之间创建导电路径的导电部分。
现在,嵌入的电路元件中的至少一个被布置成形成通过体材料的双耦接。双耦接由与信号地电位350的电连接和与集成器件300的导电层316的电连接形成。在图3的示例性实施方式中,IC管芯301被布置成从集成器件300的再分布层310延伸到集成器件300的第二侧的导电层316。IC管芯301包括衬底部分303和表面部分302。IC管芯的衬底部分303与电路层320的定向为朝向第二侧的表面对准并且因此暴露于导电层316并与导电层316接触。IC管芯的表面部分302被对准为形成电路层320的定向为朝向第一侧324的表面的一部分。因此,IC管芯暴露于再分布层310的一个或更多个导电部分并与之接触。再分布层310的导电部分包括到信号地电位350的接触区域和布线311。IC管芯301的表面部分302再次示出为包括与IC管芯的衬底部分303电接触的接触焊盘312。如参照图2所述,该接触焊盘312与再分布层307的接触区域和布线311对准,并从而连接至印刷布线板306上的信号地350或等效电位。由于在导电层316和衬底部分303之间的低阻抗接触,导电层316的电压因此可以忽略不计,并且导电层316实际上保持在信号地电位。
导电层316在其与之接触以用于双耦接的嵌入的电路元件上方延伸,这里在IC管芯301上方延伸。此外,导电层316还在至少一个未形成双耦接的嵌入的电路元件上方延伸,这里是在MEMS管芯304上方延伸。在此上下文中表达“在……上方延伸”意味着导电层316在嵌入的电路元件与外部EM场之间形成导电层。在图3中,集成器件300的层316、320、310在水平方向上延伸并且导电层316在MEMS管芯304上方水平延伸,从而有效地保护它免受电压源315——即来自外部EM场——的影响,并因此取决于管芯304上方的层316的覆盖范围的延伸度,使得从有效电压源315到MEMS管芯304的电容313接近于零。
导电层316层可以是任何导电材料。有利地,导电层是由一种金属材料或多种金属材料子层形成的金属层。有利的子层化配置的示例包括含有钛(Ti)或钛-钨(Ti/W)层与铜(Cu)或铝(Al)层的组合的双层结构。该导电层316与衬底部分303直接接触。双耦接中的电连接可以是在导电层316的金属材料与衬底部分303的硅材料之间的欧姆接触。还可以应用在导电层316的金属材料与衬底部分303的硅材料之间的肖特基势垒型接触。肖特基势垒型接触对于目的是足够的,因为肖特基势垒的界面电容将比从电压源315到导电层316的电容317高许多个数量级,并且将在高频处呈现低阻抗接触。
让我们表示形成双耦接的嵌入的电路元件的竖向维度是垂直于第一表面和第二表面的维度。形成双耦接的嵌入的电路元件301的竖向维度的至少一部分不是导电材料。术语导电材料在本文中是指电阻率约为10-8至10-7欧姆的材料。在包括衬底部分和表面部分的电路元件的情况下,嵌入的电路元件的竖向维度的一部分包括衬底部分。在具有均匀结构的电路元件的情况下,如半导体通孔,嵌入的电路元件的竖向维度的一部分包括通孔的整个深度。要求涉及从导电层316到信号地350的连接路径的特性,这将参照图7和图8更详细地讨论。图4示出封装电路系统结构的又一实施方式,在下文中称为集成器件400。到目前为止,图4的元件对应于图3的元件,所以可以从图3的描述中参考对它们的更详细的描述。集成器件400包括其中电路元件401、404嵌入体材料中的电路层420。集成器件400还包括外部连接元件408、409以及如上所描述的被配置成选择性地提供在元件层的电路元件401、404与外部连接元件408、409之间的连接的再分布层410。如果集成器件的第一侧424包括外部连接元件408、409,则导电层416位于集成器件的与第一侧相对的第二侧。
集成器件400包括IC管芯401和MEMS管芯404。IC管芯包括衬底部分403和表面部分402,并形成双耦接,如参照图3的IC管芯所描述的。MEMS管芯包括器件层419和衬底部分418。在本实施方式中,MEMS管芯的衬底部分418也对准为形成电路层420的表面并且因此暴露于导电层416并与导电层416接触。这将迫使MEMS管芯的衬底部分418具有与导电层416相同的近地电位。每当MEMS器件具有分层结构时,这是允许的甚至是有利的,在该分层结构中,器件层419位于MEMS管芯的前表面上,即在集成器件的第一侧中,并且器件层419与衬底部分418电隔离。在绝缘体上硅(SOI)晶圆上制造的MEMS器件默认具有这种结构。导电层416和衬底部分403向器件层提供的有效EMI屏蔽。
图5示出封装电路系统结构的又一实施方式,在下文中称为集成器件500。到目前为止,图5的元件对应于图3的元件,所以可以从图3的描述中参考对它们的更详细的描述。集成器件500包括其中电路元件501、504嵌入体材料中的电路层520。集成器件500还包括外部连接元件508、509以及如上所描述的被配置成选择性地提供在元件层的电路元件501、504与外部连接元件508、509之间的连接的再分布层510。如果集成器件的第一侧524包括外部连接元件508、509,则导电层516位于与集成器件的第一侧524相对的第二侧。
集成器件500包括IC管芯501和MEMS管芯504。集成器件500还包括半导体材料成型部分505的通孔,在下文中称为导电通孔505。在本实施方式中,通孔505借助于与信号地电位的电连接和与集成器件500的导电层的电连接形成双耦接。在图5的实施方式中,通孔505被布置成从再分布层510延伸到集成器件500的导电层516。通孔505的一端被对准为形成电路层520的表面并且因此暴露于导电层516并与导电层516接触。通孔505的另一端被对准为形成电路层520的相对表面并且因此暴露于包括到信号地电位的接触区域和布线511的再分布层510并与之接触。导电层516在IC管芯501和MEMS管芯504上方水平延伸并为它们提供有效的EMI屏蔽。
图6的流程图示出用于制造图3至图5中所示的封装电路系统结构的方法的各个阶段。过程可以通过制造(阶段600)电路层晶圆开始,电路层晶圆包括嵌入体材料中的可能不同来源(不同的晶圆、设计、技术)的一个或更多个电路元件。例如,可以应用本领域技术人员熟知的扇出晶圆级封装(FO-WLP)工艺。可以从电路层晶圆的一个表面减薄(阶段602)体材料,使得嵌入的电路元件中的至少一个露出。在未被减薄的电路层的表面上制造(阶段604)包括与信号地电位的电连接的再分布层,并且在再分布层上制造(阶段606)外部连接元件。再分布层因此选择性提供在元件层的电路元件与外部连接元件之间的连接。在减薄的表面上制造(阶段608)导电层。露出的嵌入的电路元件因此形成包括与信号地电位的电连接和与导电层的电连接的双耦接。使导电层在至少一个未形成双耦接的嵌入的电路元件上方延伸。
图3、图4和图5示出实施方式,其中,在FO-WLP封装器件顶部添加导电层并且该屏蔽用导电层通过器件内的嵌入结构之一、通过器件的第一表面上的再分布层以及通过外部连接元件如焊球连接至印刷布线板的信号地电位。
共同理解是,应该使导电层和在印刷布线板上的接地面之间的连接的电阻尽可能小。这对于某个频率是正确的,但现在已经检测到存在反面效果的频率范围:电阻越低,屏蔽效果越差。
从图3、图4和图5中可以看出,导电层和印刷布线板上的任何地电位平面形成电容器,其中FOWLP器件的一部分位于电容器内。相应地,在从导电层到地电位平面的连接路径中,除了电阻之外,还存在感应部件,尤其是由任何窄而长的布线部分产生的感应部件。图7示出由此形成的电路的方案以及EMI的相关电容耦合。
可以分析图7的电路,并且求解干扰电压UEMI:
其中Cp是来自外部干扰源的耦合电容,UEXT是外部源的电压,R是连接路径的电阻,L是连接路径的电感,CP是封装电容和ω是干扰电压的角频率。在微机电设备中,封装电容和连接路径的电感的典型示例值将大约是Cp=0.4pF和L=10nH。图8示出绘制为针对不同R值的作为频率的函数的比率(UEMICp)/(UEXTCc)的绝对值。该比率不是总衰减,而只是关于很高频率的相对值,其中电容分压占主导地位。
图8的曲线示出,在R的较小值处,如R=5,在约2.5GHz处存在显著的共振。实际上,这种谐振是非常有害的,因为该频带通常被许多通信系统如WiFi所使用。在电阻R的较高值处,例如,在50至150欧姆的范围内,这种谐振变得可以忽略不计,但是以较低频率处的较高信号水平为代价。但总体而言,较高的电阻会产生更可接受的结果。精确的最佳值基于封装的尺寸变化,并且无法定义通常有效的电阻值。连接路径的电阻的最佳值可以在20欧姆和1k欧姆之间变化。
图3、图4和图5中所示的屏蔽布置提供了在导电路径中包括电阻R的新颖方式。因为图3/图4中的IC管芯的衬底部分303/403很多时候具有高电阻率并且衬底接触具有有限的尺寸,所以可以容易地将所得的电阻带到期望的范围。如果电阻由有限尺寸的一个触点的扩展电阻主导,那么它将是:
其中,ρ是硅的电阻率,并且d是接触点的直径。如果ρ=5欧姆cm(ohmcm)和d=100μm,则RSPRD=250欧姆,这是用于防止图8的谐振的非常有用的值。该相同的原理可以应用于图5的导电通孔505。导电通孔可以由半导体材料制成,例如具有根据等式2进行选择以产生期望的电阻值的电阻率和接触尺寸的硅。
对于本领域技术人员明显的是,取决于所应用的技术,可以改变过程的某些阶段的顺序。减薄电路层晶圆表面的中间步骤提供了简单的方式,以使嵌入的电路元件中的一个或更多个露出,以从其衬底部分侧连接到地电位。
随着技术进步,本发明的基本构思可以以各种方式实施。因而,本发明及其实施方式不限于以上示例,而是它们可以在权利要求的范围内变化。
Claims (7)
1.一种封装电路系统结构,包括:
电路层,其包括嵌入体材料中的嵌入的电路元件;
外部连接元件;
再分布层,其被配置成选择性地提供在所述电路层的电路元件与所述外部连接元件之间的连接;其中,
所述封装电路系统结构具有包括所述外部连接元件的第一侧;
所述再分布层提供与信号地电位的电连接,
所述封装电路系统结构包括在所述封装电路系统结构的第二侧的导电层,其中,所述第二侧与所述第一侧相对,
所述封装电路系统结构的在所述第一侧与所述第二侧之间的侧面为所述体材料;
所述嵌入的电路元件至少包括嵌入的集成电路管芯和嵌入的微机电系统管芯;
所述嵌入的集成电路管芯包括衬底部分和表面部分;
所述嵌入的集成电路管芯的所述衬底部分与所述电路层的定向为朝向所述第二侧的表面对准,并且因此暴露于所述导电层并与所述导电层电接触;
所述嵌入的集成电路管芯的所述表面部分暴露于所述再分布层并与所述再分布层接触;
所述嵌入的集成电路管芯的所述表面部分包括与所述集成电路管芯的所述衬底部分和所述信号地电位电接触的接触焊盘,
所述嵌入的集成电路管芯的所述衬底部分形成将所述导电层与所述信号地电位电连接的连接路径;
所述连接路径的电阻在20欧姆与1k欧姆之间;
所述导电层在所述第二侧在所述嵌入的微机电系统管芯上方延伸;
所述嵌入的微机电系统管芯不与所述导电层电接触。
2.根据权利要求1所述的封装电路系统结构,其特征在于,所述导电层是金属层。
3.根据权利要求2所述的封装电路系统结构,其特征在于,所述金属层包括不同金属的子层。
4.根据权利要求1、2或3所述的封装电路系统结构,其特征在于,所述嵌入的微机电系统管芯的所述衬底部分与所述导电层的电连接是欧姆接触或肖特基势垒接触。
5.根据权利要求1、2或3所述的封装电路系统结构,其特征在于,所述信号地电位是所述封装电路系统结构的所有信号的地电位。
6.根据权利要求1、2或3所述的封装电路系统结构,其特征在于,所述封装电路系统结构的在所述第一侧和所述第二侧之间的外表面不包括在所述导电层和所述再分布层之间创建导电路径的导电部分。
7.一种制造封装电路系统结构的方法,所述方法包括:
制造包括嵌入体材料中的电路元件的电路层,所述电路元件包括嵌入的集成电路管芯和嵌入的微机电系统管芯,其中所述嵌入的集成电路管芯包括衬底部分和表面部分;
在所述电路层上制造再分布层,所述再分布层包括用于与信号地电位的电连接的接触区域和布线;
在所述再分布层上制造外部连接元件,所述再分布层选择性地提供在所述电路层的电路元件和所述外部连接元件之间的连接,包括所述外部连接元件的一侧是所述封装电路系统结构的第一侧;
从与所述第一侧相对的第二侧减薄所述体材料,使得所述嵌入的集成电路管芯露出;
在所述封装电路系统结构的减薄的第二侧制造导电层;其中所述方法包括:
在所述嵌入的集成电路管芯的所述表面部分中包括与所述集成电路管芯的所述衬底部分电接触并且与所述信号地电位电接触的接触焊盘,由此,所述嵌入的集成电路管芯的所述衬底部分形成将所述信号地电位与所述导电层电连接的连接路径,使得所述连接路径的电阻在20欧姆与1k欧姆之间;
在不与所述导电层电接触的所述嵌入的微机电系统管芯上方延伸所述导电层。
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