CN108963048A - A kind of semiconductor diode chip structure and its lamp luminescence component - Google Patents
A kind of semiconductor diode chip structure and its lamp luminescence component Download PDFInfo
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- CN108963048A CN108963048A CN201810531313.8A CN201810531313A CN108963048A CN 108963048 A CN108963048 A CN 108963048A CN 201810531313 A CN201810531313 A CN 201810531313A CN 108963048 A CN108963048 A CN 108963048A
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- layer
- diode chip
- semiconductor diode
- semiconductor
- metal
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F21—LIGHTING
- F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
- F21V29/00—Protecting lighting devices from thermal damage; Cooling or heating arrangements specially adapted for lighting devices or systems
- F21V29/50—Cooling arrangements
- F21V29/60—Cooling arrangements characterised by the use of a forced flow of gas, e.g. air
- F21V29/67—Cooling arrangements characterised by the use of a forced flow of gas, e.g. air characterised by the arrangement of fans
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F21—LIGHTING
- F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
- F21V29/00—Protecting lighting devices from thermal damage; Cooling or heating arrangements specially adapted for lighting devices or systems
- F21V29/50—Cooling arrangements
- F21V29/70—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks
- F21V29/74—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks with fins or blades
- F21V29/77—Cooling arrangements characterised by passive heat-dissipating elements, e.g. heat-sinks with fins or blades with essentially identical diverging planar fins or blades, e.g. with fan-like or star-like cross-section
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Abstract
The invention discloses a kind of semiconductor diode chip structures, including semiconductor diode chip, the encapsulating structure of semiconductor diode chip and the substrate for welding encapsulating structure, semiconductor diode chip includes Sapphire Substrate, rectangular packaging insulating layer is provided in Sapphire Substrate, several main core blade units are filled in Sapphire Substrate inside packaging insulating layer, and fine crack slot is provided between adjacent main core blade unit, main core blade unit includes the first metal dish, first metal dish side is provided with the second metal dish, annular insulating layer is provided between second metal dish and the first metal dish, the second metal dish installation site on two adjacent main core blade units is opposite, the both ends of annular insulating layer are connected on packaging insulating layer, connecting bridge is provided in fine crack slot, microchip is provided in connecting bridge, realize chip structure Separate type work and Exciting-simulator system joint, increase the whole amount of light of master unit chip.
Description
Technical field
The present invention relates to semiconductor diode field, specially a kind of semiconductor diode chip structure and its lamp luminescence
Component.
Background technique
In semiconductor diode field, LED just gradually replaces tradition to shine as important optoelectronic diode, LED technology
Bright technology and fluorescent technique enter lighting area, while LED chip is also because of the characteristic that it is provided simultaneously with electronic device, in addition to shining
Bright application more opens many completely new application fields, pursues and being worth higher to lumen to the continuous of industry manufacturing cost
During compression, the upside-down mounting application of light emitting diode has been generally considered industrial trend, and upside-down mounting LED chip is
Conducive to high current to obtain higher lumen value, and improve chip with the welding manner of heat sink closer semiconductor active region
Heat transfer.
Traditional positive assembling structure LED technology is slowly eliminated instead better reliability, lumen density are bigger
The LED technology of inverted structure, while the envelope of epoxy resin is mostly used in the encapsulation process of existing semiconductor diode chip greatly
Dress mode, semiconductor diode chip is interior to carry out die bond in such a way that silica gel drips glue, and generates during the drop glue of silica gel
Fluorescent powder sedimentation so that packaging effect is irregular, the light-out effect of LED is difficult to be well controlled, inverted structure
For LED light when carrying out the connection of chip positive and negative anodes, connection line is too long, is easy to influence the accuracy of encapsulation, in upside-down mounting diode core
In piece welding process because electrode it is face-down, the alignment of chip and pad be need more accurately sealed in unit investment, and
Coplanar, closely-spaced positive and negative electrode arrangement is also easy to appear chip short circuit caused by solder mutually overflows in welding.
Summary of the invention
In order to overcome the shortcomings of prior art, the present invention provides a kind of semiconductor diode chip structure and its lamps and lanterns
Luminescence component realizes the separate type work and Exciting-simulator system joint of chip structure, increases the whole amount of light of master unit chip,
It can effectively solve the problem of background technique proposes.
The technical solution adopted by the present invention to solve the technical problems is:
A kind of semiconductor diode chip structure and its lamp luminescence component, including semiconductor diode chip, semiconductor
The encapsulating structure of diode chip for backlight unit and the substrate for welding encapsulating structure, the semiconductor diode chip include sapphire lining
Bottom is provided with rectangular packaging insulating layer in the Sapphire Substrate, fills out in the Sapphire Substrate inside the packaging insulating layer
Filled with several main core blade units, and fine crack slot, the main core blade unit packet are provided between the adjacent main core blade unit
Include the first metal dish, first metal dish side is provided with the second metal dish, second metal dish and the first metal dish it
Between be provided with annular insulating layer, the second metal dish installation site on two adjacent main core blade units on the contrary, it is described annular absolutely
The both ends of edge layer are connected on packaging insulating layer, and connecting bridge is provided in the fine crack slot, micro- core is provided in the connecting bridge
Piece.
Further, the main core blade unit further includes the conductive membrane layer with the contact of the surface of Sapphire Substrate, described
It is provided with the first electroluminescent layer on conductive membrane layer, is provided with semiconductor layer on the first electroluminescent layer, is set on the semiconductor layer
It is equipped with the second electroluminescent layer, buffer layer is provided between the second electroluminescent layer and the first metal dish, the packaging insulating layer is inside
It is laid between the first electroluminescent layer and the first metal dish, and passes through conductive microplate between the conductive membrane layer and the second electroluminescent layer
Ohm connection, and the conductive microplate is connected on the second metal dish, in the annular insulating layer to be laid in conductive microplate and
The contact surface of semiconductor layer.
Further, the first electroluminescent layer, semiconductor layer and the second electroluminescent layer are divided into several by the conductive microplate
Shape array, and parabola microprism is provided in the corresponding Sapphire Substrate of the stripe array, semiconductor layer includes that electronics mentions
Take layer, PN ganglionic layer and hole transmission layer.
Further, the PN ganglionic layer in the stripe array includes p-type contact layer and N shape contact layer, wherein adjacent
The PN section of p-type contact layer and second main core blade unit in the PN ganglionic layer of first main core blade unit of two main core blade units
N-type contact layer in layer is linked together by connecting bridge.
Further, the conductive microplate and first electroluminescent layer of contact position are provided with micropore, and the micropore sequentially passes through
Semiconductor layer, the second electroluminescent layer, conductive membrane layer and buffer layer.
Further, the substrate includes aluminum base layer, and the aluminum base layer upper and lower surfaces are provided with groove, described
Covering in aluminum base layer has heat-conducting layer, and has ceramic film by Groove binding between the aluminum base layer and heat-conducting layer, described thermally conductive
Layer surface, which is covered, dielectric substance layer, and the dielectric substance layer surface is covered copper foil layer, and the bottom of the aluminum base layer, which is covered, PI
Film layer is provided with gold thread between the dielectric substance layer and copper foil layer, and the both ends of the gold thread are provided with patch disk.
Further, viscous by thermally conductive gluing between the ceramic film and heat-conducting layer, and the heat-conducting glue is filled into ditch
In slot, and the heat-conducting glue is filled into groove, and the semiconductor diode chip encapsulated by encapsulating structure after pass through welding
It is connected on the positive and negative anodes of the copper foil layer of substrate.
Further, the encapsulating structure includes the reflector of package support and installation on the package support, reflector
Interior bottom package support surface centre on be welded with metal heat sink, the semiconductor diode chip is mounted on metal heat sink
On, package support surface both ends are provided with metal pin, and one end of the metal pin is connected to envelope by point layer
It filling on bracket, the other end of the metal pin extends into metal heat sink, and the metal heat sink is internally provided with electrical hole, and
The semiconductor diode chip is connected on metal pin by passing through the interior bonding line in electrical hole, the semiconductor diode
Chip surface is provided with hemisphere silica gel, negative lens is provided between the hemisphere silica gel and reflector, positioned at the top of hemisphere silica gel
It is provided with hemisphere vacuum chamber in the negative lens in portion, plane fluorescent bisque is provided at the top of the hemisphere vacuum chamber, and described flat
Face fluorescence layering top is provided with the closedtop cambered surface with negative lens integrally connected.
Further, the present invention also provides a kind of lamp luminescence component of semiconductor diode chip, including mounting base,
And set ring plate of the screw occlusion in mounting base, the substrate are arranged in mounting base, the mounting base bottom is provided with cylinder
Type radiating fin is provided with ring layer slot among the cartridge type radiating fin, is equipped with mini fan inside the ring layer slot, described
The surface of set ring plate and the contact of cartridge type radiating fin is provided with through slot.
Further, the cartridge type radiating fin between ring layer slot and set ring plate is in sealing state.
Compared with prior art, the beneficial effects of the present invention are:
(1) structure type of the invention use inverted structure semiconductor diode chip structure, packaging insulating layer and
The structure type that the main core blade unit in packaging insulating layer is arranged is whole overlooking structure figure, by one by way of segmentation
Whole semiconductor diode chip separation is at several smaller chip forms, to effectively control single main core blade unit
Luminous efficiency；
(2) present invention makes the first metal dish and the second metal dish completely isolated by annular insulating layer, and adjacent two
The second metal dish installation site on main core blade unit is on the contrary, i.e. the second metal dish is separately positioned on two neighboring main core blade unit
The left and right sides, thus two adjacent main core blade units inside formed inverse current guiding, the main core blade unit of segmentation
It is bridged by being provided with connecting bridge in fine crack slot, and the microchip by being arranged in connecting bridge controls two neighboring main core
The electronics of blade unit flows, thus the phase mutual excitation of two main core blade units, the further luminous effect for improving main core blade unit
Rate.
(3) present invention is by being arranged silver-colored reflecting surface in the contact surface of buffer layer and the second electroluminescent layer, for reducing buffer layer
With the extinction effect of the second electroluminescent layer, the light that semiconductor layer is generated is projected by Sapphire Substrate as far as possible,
The packaging insulating layer is inwardly laid between the first electroluminescent layer and the first metal dish, the conductive membrane layer and the second electroluminescent layer
Between by conductive microplate Ohm connection, and the conductive microplate is connected on the second metal dish, in the annular insulating layer to
It is laid in the contact surface of conductive microplate and semiconductor layer.
(4) cooperate lamp assembly in the present invention, carry out the high efficiency and heat radiation of semiconductor diode, mini fan is by air from passing through
It is pumped into, is flowed into the morphogenetic flow-guiding channel of seal shape in wears groove, and be discharged from the intermediate of cartridge type radiating fin, while micro electric
The air of the cartridge type radiating fin of flow-guiding channel bottom is fanned while extracting, so that surface flow of the air along cartridge type radiating fin,
To carry out effective thermally conductive cooling by cartridge type radiating fin.
Detailed description of the invention
Fig. 1 is semiconductor diode chip structural schematic diagram of the invention；
Fig. 2 is semiconductor diode chip the schematic diagram of the section structure of the invention；
Fig. 3 is semiconductor diode chip semiconductor layer the schematic diagram of the section structure of the invention；
Fig. 4 is semiconductor diode chip connecting bridge attachment structure schematic diagram of the invention；
Fig. 5 is semiconductor diode chip of the invention and package support attachment structure schematic diagram；
Fig. 6 is that of the invention waiting has component schematic perspective view；
Fig. 7 is semiconductor diode chip package structure diagram of the invention；
Fig. 8 is semiconductor diode chip mounting board structure schematic diagram of the invention；
Fig. 9 is that the aluminum substrate in semiconductor diode installation base plate of the invention is three-dimensional；
Figure 10 is encapsulating structure process flow diagram of the invention；
Figure 11 is encapsulating structure gluing process flow diagram of the invention；
Figure 12 is aluminum substrate production process block diagram of the invention.
Figure label:
1- Sapphire Substrate；2- packaging insulating layer；3- main core blade unit；4- fine crack slot；5- connecting bridge；6- microchip；7-
Stripe array；8- substrate；9- mounting base；10- encapsulating structure；12- semiconductor diode chip；
The first metal dish of 301-；The second metal dish of 302-；303- annular insulating layer；304- conductive membrane layer；305- first
Electroluminescent layer；306- semiconductor layer；307- buffer layer；308- conduction microplate；The micro- rib border of 309- parabola；The electroluminescent layer of 310- second；
311- micropore；
3061- electron extraction layer；3062-PN ganglionic layer；3063- hole transmission layer；30621-P type contact layer；30622-N type
Contact layer；
801- aluminum base layer；802- groove；803- heat-conducting layer；804- ceramic film；805- dielectric substance layer；806- copper foil layer；
807-PI film layer；808- gold thread；809- pastes disk；
901- mounting base；902- cartridge type radiating fin；903- ring layer slot；904- mini fan；905- runs through slot；
1002- package substrate；1003- reflector；1004- metal heat sink；1005- metal pin；1006- electrical property hole；
Bonding line in 1007-；1008- hemisphere silica gel；1009- negative lens；1010- hemisphere vacuum chamber；1011- plane fluorescent bisque；
1012- closedtop cambered surface；1013- argentum reflecting layer；1014- annular groove；The transparent adhesive layer of 1015-.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figures 1 to 9, the present invention provides a kind of semiconductor diode chip structure, the semiconductor diodes
Chip 12 includes Sapphire Substrate 1, is provided with rectangular packaging insulating layer 2, the packaging insulating layer in the Sapphire Substrate 1
It is filled with several main core blade units 3 in Sapphire Substrate 2 inside 2, and is provided between the adjacent main core blade unit 3
Fine crack slot 4, wherein the structure type uses the semiconductor diode chip structure of inverted structure, packaging insulating layer 2 and setting
The structure type of main core blade unit 3 in packaging insulating layer 2 is whole overlooking structure figure, whole by one by way of segmentation
The semiconductor diode chip separation of body is at several smaller chip forms, to effectively control single main core blade unit 3
Luminous efficiency.
The main core blade unit 3 in the present invention includes the first metal dish 301,301 side of the first metal dish setting
There is the second metal dish 302, and there are adaptability difference in height, the second metal dish for first metal dish 301 and the second metal dish 302
302 and first are provided with annular insulating layer 303 between metal dish 301, and it is exhausted that the both ends of the annular insulating layer 303 are connected to encapsulation
In edge layer 2, make the first metal dish 301 and the second metal dish 302 completely isolated by annular insulating layer 303, adjacent two
302 installation site of the second metal dish on main core blade unit 3 is on the contrary, i.e. the second metal dish 302 is separately positioned on two neighboring master
The left and right sides of chip unit 3, so that inverse current guiding is formed in the inside of two adjacent main core blade units 3, segmentation
Main core blade unit 3 is bridged by being provided with connecting bridge 5 in fine crack slot 4, and the microchip 6 by being arranged in connecting bridge 5
The electronics flowing of two neighboring main core blade unit 3 is controlled, so that the phase mutual excitation of two main core blade units 3, further to improve
The luminous efficiency of main core blade unit 3.
Wherein main core blade unit 3 further includes the conductive membrane layer 304 with the contact of the surface of Sapphire Substrate 1, conductive film
Layer 304 uses the better graphene-structured of electric conductivity, and wherein the conductive membrane layer 304 of graphene-structured provides semiconductor two
Pole pipe high performance electric conductivity between the two, graphene has high light transmittance, while the flexibility of graphene is also convenient in semiconductor
The production of the flexible substrate of diode, while saving the production cost in semiconductor diode.
It is provided with the first electroluminescent layer 305 on conductive membrane layer 304, is provided with semiconductor on the first electroluminescent layer 305
Layer 306, is provided with the second electroluminescent layer 310 on the semiconductor layer 306, the second electroluminescent layer 310 and the first metal dish 301 it
Between be provided with buffer layer 307, wherein the first electroluminescent layer 305 and conductive membrane layer 304 are combined into the conductive base of semiconductor layer 306
Body carries out the electron transmission and compound in semiconductor 306, and the combination thickness of conductive membrane layer 304 and the first electroluminescent layer 305 exists
Between 3-4 μm, while in order to improve the self-conductive rate of semiconductor layer 306, while electric current is extended, the second electroluminescent layer 310 is gentle
The combination thickness of layer 307 is rushed at 4-5 μm, wherein buffer layer is between 1-2 μm, thus the first metal dish 301 and the second metal dish
The 302 adaptability differences in height generated are conductive membrane layer 304, the first electroluminescent layer 305, the second electroluminescent layer 306 and buffer layer 307
High integrity generates, and due to the technical error and first when Sapphire Substrate 1 and conductive membrane layer 304 are removed
The difference in height that electroluminescent layer 305, the second electroluminescent layer 306 and buffer layer 307 generate when covering will all form the first metal dish 301 and the
The adaptability difference in height of two metal dish 302.
By the way that silver-colored reflecting surface is arranged in the contact surface of buffer layer 307 and the second electroluminescent layer 310, for reducing buffer layer 307
With the extinction effect of the second electroluminescent layer 310, the light that semiconductor layer 306 is generated is as far as possible by Sapphire Substrate 1
It projects, the packaging insulating layer 2 is inwardly laid between the first electroluminescent layer 305 and the first metal dish 301, the conductive film
By 308 Ohm connection of conductive microplate between layer 304 and the second electroluminescent layer 310, and the conductive microplate 308 is connected to the second gold medal
Belong on disk 302, to the contact surface for being laid in conductive microplate 308 and semiconductor layer 306 in the annular insulating layer 303.
Wherein the first electroluminescent layer 305, semiconductor layer 306 and the second electroluminescent layer 310 are divided into several by conductive microplate 308
Stripe array 7, and it is electroluminescent to pass through conductive microplate 308 connects in the previous stripe array 7 in adjacent stripe array 7 first
The second electroluminescent layer 310 in layer 305 and the latter stripe array 7, and form Ohm connection.
And it is provided with parabola microprism 309 in the corresponding Sapphire Substrate 1 of the stripe array 7, by conducting wire microplate 308
The projection light that semiconductor layer 306 in the stripe array 7 electrically separated generates will be by the micro- rib border of parabola in Sapphire Substrate 1
309 projection, and semiconductor layer 306 generate light, the projection of light be it is chaotic, the scattering effect of light is more serious, so that partly leading
The projection efficiency of body diode is not high, and the projection light for being generated aggregation semiconductor layer 306 by the micro- rib border 309 of parabola, and with
The form of concave-convex lens carries out secondary projection, seems softer under the optical path that last epoxy resin encapsulates, and light efficiency is also more
It is good.
Semiconductor layer 306 in the present invention includes electron extraction layer 3061, PN ganglionic layer 3062 and hole transmission layer 3063,
PN ganglionic layer 3062 in the stripe array 7 includes p-type contact layer 30621 and N shape contact layer 30622, to relatively independent
When main core blade unit 3 is electrically connected, wherein the PN of first main core blade unit 3 of two adjacent main core blade units 3 is saved
P-type contact layer 30621 in layer 3062 and the N-type contact layer 30622 in the PN ganglionic layer 3062 of second main core blade unit 3 pass through
Connecting bridge 5 links together, and when main core blade unit is powered on, generates in the N-type contact layer 30622 in semiconductor layer 306
Electronics can not be rapidly filled completely into the hole of p-type contact layer 30621, the electronics quilt generated in N-type contact layer 30622
5 water conservancy diversion of connecting bridge flow to the p-type contact layer in adjacent stripe array 7, and pass through the stress to electric field of microchip 6
Release mentions so that dielectric electric field weakens, while motivating the electron hole joint efficiency that the p-type in PN ganglionic layer contacts and N-type contacts
High external quantum efficiency increases the light extraction efficiency of semiconductor layer 306 to increase electric field exposure area in semiconductor layer 306, into
And improve the side light emission rate in the Sapphire Substrate 1 of 7 junction of stripe array of adjacent main core blade unit 3.
The conductive microplate 308 and the first electroluminescent 305 contact position of layer in the present invention are provided with micropore 311, and described micro-
Hole 311 sequentially passes through semiconductor layer 306, the second electroluminescent layer 310, conductive membrane layer 304 and buffer layer 307.
The substrate 8 in the present invention includes aluminum base layer 801, and 801 upper and lower surfaces of aluminum base layer are provided with
Groove 802, covering in the aluminum base layer 801 has heat-conducting layer 803, and passes through groove between the aluminum base layer 801 and heat-conducting layer 803
802 are bonded with ceramic film 804, and 803 surface of heat-conducting layer, which is covered, dielectric substance layer 805, and 805 surface of the dielectric substance layer
Covering has copper foil layer 806, and the bottom of the aluminum base layer 801, which is covered, PI film layer 807, the dielectric substance layer 805 and copper foil layer 806
Between be provided with gold thread 808, and the both ends of the gold thread 808 are provided with patch disk 809.
It is installed by aluminum base layer 801 and ceramic film 804 by the bonding of groove 802, increases aluminum base layer 801 and ceramic membrane
Contact area between layer 804, while quickly heat transmitting is carried out by the high-efficiency heat conduction property of ceramic film 804 itself, it leads
Thermosphere 803 is the insulation highly heat-conductive material of high-purity aluminium nitride.
It is wherein viscous by thermally conductive gluing between ceramic film 804 and heat-conducting layer 803, and the heat-conducting glue is filled into groove
After in 802, and the heat-conducting glue is filled into groove 802, and the semiconductor diode chip 12 is encapsulated by encapsulating structure 10
By being welded to connect on the positive and negative anodes of the copper foil layer 806 of substrate 8.
The set ring plate 901 of mounting base 9 and screw occlusion in mounting base 9 in the present invention, the setting of substrate 8 exist
The contact that is electrically connected in mounting base 901, and on the substrate 8 is welded in mounting base 901 by conducting wire, 9 bottom of mounting base
Portion is provided with cartridge type radiating fin 902, and ring layer slot 903, the ring layer slot 903 are provided among the cartridge type radiating fin 902
Inside is equipped with mini fan 904, and the surface that the set ring plate 901 and cartridge type radiating fin 902 contact is provided with through slot
905, in semiconductor diode chip work, in the heat transfer to set ring plate 901 of generation, passed simultaneously by covering ring plate 901
It is handed on cartridge type radiating fin 902, is effectively radiated by the contact area of cartridge type radiating fin 902 itself, and when heat
When amount reaches a certain level, the mini fan 904 in cartridge type radiating fin 902 works, and is located at ring layer slot 903 and lantern ring
Cartridge type radiating fin 902 between piece 901 is in sealing state, so that the surrounding in substrate 8 forms flow-guiding channel, mini fan
904 by air from being pumped into the slot 905, flow into the morphogenetic flow-guiding channel of seal shape, and from cartridge type radiating fin 902
Centre discharge, while mini fan 904 extracts the air of the cartridge type radiating fin 902 of flow-guiding channel bottom simultaneously, so that air
Along the surface flow of cartridge type radiating fin 902, to carry out effective thermally conductive cooling by cartridge type radiating fin 902.
It further remarks additionally, including semiconductor diode chip 12, package support 1002 and is mounted on encapsulation
Reflector 1003 on bracket 1002 is welded with metal heat sink on the package support surface centre of the interior bottom of reflector 1003
1004, the semiconductor diode chip 12 is mounted on metal heat sink 1004,1002 surface both ends of the package support setting
There is metal pin 1005, and one end of the metal pin 1005 is connected on package support 1002 by point layer, the gold
The other end for belonging to pin 1005 extends into metal heat sink 1004, and the metal heat sink is internally provided with electrical hole 1006, and institute
It states semiconductor diode chip 12 and is connected on metal pin 1005 by passing through the interior bonding line 1007 in electrical hole 1006, it is described
12 surface of semiconductor diode chip is provided with hemisphere silica gel 1008, is arranged between the hemisphere silica gel 1008 and reflector 1003
There is negative lens 1009, is provided with hemisphere vacuum chamber 1010 in the negative lens 1009 at the top of hemisphere silica gel 1008, described half
The top of ball vacuum chamber 1010 is provided with plane fluorescent bisque 1011, and 1011 top of plane fluorescent layering is provided with and bears
The closedtop cambered surface 1012 of 1009 integrally connected of lens.
In the present invention in the encapsulation process for carrying out semiconductor diode chip 12, by the positive and negative anodes of chip and interior bonding line
1007 connection is arranged in the electrical hole 1006 on metal heat sink 1004, and by the sealing in heat-conducting glue electrical property hole, thus
The connection structure of bonding line 1007 and metal pin 1005 in fixed, during carrying out efficient electron-transport, generation
Heat can be also rapidly performed by conduction, pass through reflector 1003, negative lens 1009, plane fluorescent bisque 10011 and closedtop
Cambered surface 1012 substitutes the packing forms of general epoxy resin, while improving positive amount of light, makes to show that light is softer, make
The form that plane fluorescent bisque 1011 substitutes silica gel and fluorescent powder mixing drop glue sealing semiconductor diode chip is obtained, is thrown in light
Penetrate fluorescent powder settlement issues simpler in the control of effect, while generating when avoidable fluorescent powder and silica gel mixing drop glue.
Supplementary explanation is also solved in the hemisphere vacuum chamber 1010 that negative lens 1009 is arranged using the light in air chamber
Loss problem is measured, semiconductor diode chip 12 passes through the conduction of negative lens 1009 and hemisphere vacuum chamber 1010, so that chip light
The distance between source and plane phosphor powder layer increase, and negative lens 1009 also can be by the throw light of chip light source with vertical angle
Degree injects plane fluorescent bisque, reduces lambert's shape distribution of chip light source.
It wherein is provided with argentum reflecting layer 1013 on the contact surface of the negative lens 1009 and reflector 1003, is reflected by silver
The reflected light of 1013 pairs of negative lens 1009 of layer carries out secondary reflex, improves the positive amount of light of semiconductor diode chip.
1004 upper surface of metal heat sink is provided with annular groove 1014 in the present invention, is capable of providing semiconductor diode core
Good location of the piece in annular groove 1014, enables semiconductor diode chip to be accurately fixed on metal heat sink 1004
Center, annular groove 1014 can welding when the reception of extra interference solder be provided.
1003 bottom of reflector is connected and fixed by the upper surface of transparent adhesive layer 1015 and package support 1002.
Embodiment 2:
As shown in Figure 10, a kind of semiconductor diode chip encapsulation manufacturing method is additionally provided in the present invention, including as follows
Step:
S100, metal heat sink is welded on to package support, and fixed chip point.
The package support feeding reflow ovens progress reflow soldering of S200, chip, when carrying out Reflow Soldering, in reflow ovens
Temperature is rapidly heated to preheating temperature, then proceedes to the fusion temperature for being warming up to solder, generates frit reaction, finally carries out quick
Cooling.
S300, it is connected with metal pin on package support with carrying out chip positive and negative anodes, metal pin is welded on encapsulation branch
On frame.
S400, carry out chip surface hemisphere silica gel dispensing, and the Integral connection structure of reflector and negative lens is installed.
Wherein include the following steps: in the step s 100
S101, before welding metal is heat sink, position of the chip on metal heat sink is pre-installed, after in chip
Positive and negative anodes bonding point position carries out point, and the point position is located at the outer peripheral surface of metal heat sink annular groove；
Before using package support, package support is placed in vacuum oven and is toasted, while in order to guarantee encapsulation branch
The overall performance of frame, temperature are no more than 100 DEG C, and baking time is 30 minutes or so, when carrying out spot printing solder, the needle of dispenser
Hole is selected in 0.2mm or so, and each chip is fixed on metal heat sink surface, carries out position by industrial CCD camera
Detection, it is ensured that semiconductor diode chip is fixed on the middle position of metal heat sink, and is soldered in semiconductor diode chip point
Cheng Hou carries out the compacting of semiconductor diode chip by concora crush, it is ensured that solder tiling；
S102 and the punching that electrical hole is carried out in the point of metal heat sink top surface, while carrying out metal heat sink
The punching of side, so that electrical hole connection；
S103, one end of metal pin is mounted in the side punching of metal heat sink, interior bonding line is respectively welded at
On the positive and negative anodes of chip.
S104, chip is fixed among the inner ring of arc groove, the spot welding carried out between chip and metal heat sink is fixed.
In step S200 step, in the spot welding of metal heat sink and package support, the solder area of spot printing is in metal fever
It sinks and accounts for about the 7/10 of chip area after being sheeted, it is ensured that can between solder and semiconductor diode chip after Reflow Soldering
The solder layer of layer is formed, while the annular groove by being arranged on the surface of metal heat sink can also flatten semiconductor two
When pole pipe chip, a degree of solder absorption is carried out, places more solder to semiconductor diode chip in sheeting operation
Middle to generate biggish change in location, caused heat sink off-centring while so that solder connection is smooth, avoids solder from entering electricity
In property hole, the opposing insulation of electrical hole and solder layer ensure that.
After Reflow Soldering, thermal plastic insulation is injected in electrotropism hole, internal bonding line and metal pin are in metal fever
Coupling part in heavy is fixed, while the setting angle of fixed metal pin, at the same to semiconductor diode chip into
When the connection of the metal pin on row positive and negative anodes and package support, generally using spun gold ball machine carry out bonding wire, interior bonding line it is straight
Diameter is between 20-25 μm, and positive and negative anodes generally respectively need both threads to be attached bonding wire, guarantees to be melt when high current input
It is disconnected, while interior bonding line in use process can also be reduced and fallen off lead to the problem of semiconductor diode chip open circuit.
In step S400, there are following steps:
S401, reflector bottom is sleeved on metal heat sink, and makes metal heat sink in reflector bottom centre position；
S402, the dispensing for carrying out hemisphere silica gel in chip surface with dispenser；
S403, after hemisphere silica gel it is cooling it is qualitative after, carry out negative lens and reflector plastotype, while in negative lens and reflector
Between contact surface fill silver-colored reflecting surface, and make holding at the top of negative lens and reflector horizontal；
S403, it is provided with metal hemisphere at the top of negative lens, after heat melts the negative lens cooling forming of shape, takes out metal
Hemisphere；
And in negative lens and reflector plastotype, the negative lens of softening is filled between reflector and metal hemisphere, together
When coat silver-colored reflecting surface in reflector inwall in advance and cover light on the hemispheroidal surface of metal when being put into metal hemisphere
Film is learned, after negative lens cooling is qualitative, optical film is also fitted in the negative lens inner cavity of metal hemisphere formation；
Phosphor powder layer, is embedded in the top of negative lens by S404, the preparation for carrying out phosphor powder layer, then carries out phosphor powder layer top
Fusion at the top of the closedtop cambered surface and negative lens in portion evacuates the sky for the cavity inside that metal hemisphere is formed while fusion
Gas；
During encapsulation, fluorescence is not layered in involvement hemisphere silica gel and carries out dispensing, but by negative lens
Top is arranged fluorescence and is layered, and on the one hand can be avoided the fluorescent powder settlement issues occurred during the dispensing of hemispherical silica gel,
Plane fluorescent bisque can be effectively projected to by the light that semiconductor diode chip issues simultaneously, to issue softer
White light, simultaneously because metal hemisphere formed hemisphere vacuum cavity wall on be provided with optical film, thus allow for managing
Think the optical filtering of white light, polarization, the projection of enhancing and change white light, and reduce reflection of the light in negative lens, passes through negative lens
Reflected light also can further be emitted by argentum reflecting layer, to improve the bright degree of encapsulating structure entirety；
It further illustrates, when carrying out the preparation of plane fluorescent bisque, can directly carry out transparent silica gel and fluorescent powder
Mix in proportion, and fluorescent powder using concentration need according to the luminous quantity and efficiency of semiconductor diode chip determine, thus
The fluorescent powder amount of the semiconductor diode chip use bright for height is in 0.3-0.4g/cm2, carry out stirring for fluorescent powder and silica gel
When mixing, the time is unsuitable too long, and 10-12 minute or so, and be molded as by dispenser progress phosphor powder layer and silica-gel mixture
Shape is in discotic after solidification.
As shown in figure 12, the present invention also provides a kind of production technology of the substrate of semiconductor diode chip, features
It is: includes the following steps
S1000, the sawing sheet for carrying out aluminum base layer and ceramic film are bonded with aluminum base layer, in the key of ceramic film and aluminum base layer
During conjunction, positioning gluing is carried out at aluminium base surface non-groove position, when ceramic film and aluminum base layer press, contact position
Heat-conducting glue will be spilled over in groove, to carry out the filling of heat-conducting glue to groove, avoid the complete in aluminium base layer surface of heat-conducting glue
The edge generated during applying overflows, and influences the subsequent encapsulation of its aluminum substrate；
S2000, dry film route clad can is carried out to the composite entity of aluminum base layer and ceramic film, and carries out heat-conducting layer, dielectric
Matter layer and copper foil layer cover, and using the electrolytic copper foil of 1OZ thickness, the thickness control of dielectric to layer is in 2.5mil-
10mil subtracts the addition step of glass cloth, and silica white filler is added when carrying out the preparation of heat-conducting layer；
S3000, aluminum base layer surface etch and positioning are practiced shooting, and carry out that black is anti-welding and white is anti-welding, are being practiced shooting
During, it carries out 7 location holes and practices shooting, and using the drill bit of 1.6mm, and position of positioning hole is staggered the angle cutting edge of a knife or a sword of groove；
Black is anti-welding to be printed using 250# web plate, and ink thickness is controlled at 5-9 μm, and baking time is not less than 20
Minute, it is less than 30 minutes, white is anti-welding, is printed using 90# web plate, and ink thickness controls between 35-40 μm, when baking
Between 30 minutes or so, rear to carry out three-stage heating baking, three sections of heating gradients are respectively 110 DEG C, 130 DEG C and 160 DEG C, when baking
Between gradient be 20-25 minute, 20-30 minutes and 35-40 minutes, and it is anti-welding more unilateral greatly than white anti-welding windowing in black
0.15mm；
S4000, to positioning, progress at target practice is golden, and carries out the drilling of gold thread guide line, adds aluminium frame envelope after carrying out V-CUT
Dress, in progress gold, Au thickness is in 3-5U, and Ni thickness control is in 120-150U.
Preferably, in step S1000, equidistantly throw slot in aluminum base layer upper and lower surface, and aluminum base layer upper surface and
It is mutually perpendicular on the groove space of lower surface dished out, i.e., shows to carry out throwing slot along its length in aluminum base layer, in aluminium base
The lower surface of layer carries out the throwing slot of groove in the width direction, selects the aluminum substrate of thermal conductivity 10-12w/mk, and the thickness of aluminum substrate
Aluminum substrate between 3-4mm, and the whole of 0.2-0.3mm is carried out to aluminum substrate upper and lower surface during throwing slot and throws layer,
So that aluminum substrate surface roughness increase to why big and ceramic film combination, the raising thermally conductive contact of contact.
Preferably, in step S2000, heat-conducting layer and dielectric substance layer pass through heat-conducting glue and glue, and copper foil layer is logical
Cross pressing adherency.
It is obvious to a person skilled in the art that invention is not limited to the details of the above exemplary embodiments, Er Qie
In the case where without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, the present embodiments are to be considered as illustrative and not restrictive, and the scope of the present invention is by appended power
Benefit requires rather than above description limits, it is intended that all by what is fallen within the meaning and scope of the equivalent elements of the claims
Variation is included within the present invention.Any reference signs in the claims should not be construed as limiting the involved claims.
Claims (10)
1. a kind of semiconductor diode chip structure, it is characterised in that: including semiconductor diode chip (12), two pole of semiconductor
The encapsulating structure (10) of tube chip and the substrate (8) for welding encapsulating structure, the semiconductor diode chip (12) include indigo plant
Jewel substrate (1), is provided with rectangular packaging insulating layer (2) on the Sapphire Substrate (1), in the packaging insulating layer (2)
It is filled with several main core blade units (3) in the Sapphire Substrate (2) in portion, and is set between the adjacent main core blade unit (3)
It is equipped with fine crack slot (4), the main core blade unit (3) includes the first metal dish (301), and the first metal dish (301) side is set
It is equipped with the second metal dish (302), is provided with annular insulating layer between second metal dish (302) and the first metal dish (301)
(303), the second metal dish (302) installation site on two adjacent main core blade units (3) is on the contrary, the annular insulating layer
(303) both ends are connected on packaging insulating layer (2), are provided with connecting bridge (5) in the fine crack slot (4), the connecting bridge (5)
On be provided with microchip (6).
2. a kind of semiconductor diode chip structure according to claim 1, it is characterised in that: the main core blade unit
(3) further include the conductive membrane layer (304) contacted with the surface of Sapphire Substrate (1), be arranged on the conductive membrane layer (304)
There is the first electroluminescent layer (305), is provided with semiconductor layer (306) on the first electroluminescent layer (305), the semiconductor layer (306)
On be provided with the second electroluminescent layer (310), be provided with buffer layer between the second electroluminescent layer (310) and the first metal dish (301)
(307), the packaging insulating layer (2) is inwardly laid between the first electroluminescent layer (305) and the first metal dish (301), and described
Pass through conductive microplate (308) Ohm connection, and the conductive microplate between conductive membrane layer (304) and the second electroluminescent layer (310)
(308) it is connected on the second metal dish (302), described annular insulating layer (303) introversion is laid in conductive microplate (308) and partly leads
The contact surface of body layer (306).
3. a kind of semiconductor diode chip structure according to claim 1, it is characterised in that: the conduction microplate
(308) the first electroluminescent layer (305), semiconductor layer (306) and the second electroluminescent layer (310) are divided into several stripe arrays (7),
And it is provided with parabola microprism (309) on the corresponding Sapphire Substrate (1) of the stripe array (7), semiconductor layer (306) packet
Include electron extraction layer (3061), PN ganglionic layer (3062) and hole transmission layer (3063).
4. a kind of semiconductor diode chip structure according to claim 3, it is characterised in that: in the stripe array
(7) the PN ganglionic layer (3062) in includes p-type contact layer (30621) and N shape contact layer (30622), wherein two adjacent main cores
P-type contact layer (30621) and second main core in the PN ganglionic layer (3062) of first main core blade unit (3) of blade unit (3)
N-type contact layer (30622) in the PN ganglionic layer (3062) of blade unit (3) is linked together by connecting bridge (5).
5. a kind of semiconductor diode chip structure according to claim 1, it is characterised in that: the conduction microplate
(308) it is provided with micropore (311) with the first electroluminescent layer (305) contact position, and the micropore (311) sequentially passes through semiconductor layer
(306), the second electroluminescent layer (310), conductive membrane layer (304) and buffer layer (307).
6. a kind of semiconductor diode chip structure according to claim 1, it is characterised in that: the substrate (8) includes
Aluminum base layer (801), aluminum base layer (801) upper and lower surfaces are provided with groove (802), on the aluminum base layer (801)
Covering has heat-conducting layer (803), and is bonded with ceramic membrane by groove (802) between the aluminum base layer (801) and heat-conducting layer (803)
Layer (804), heat-conducting layer (803) surface, which is covered, to be had dielectric substance layer (805), and cover the dielectric substance layer (805) have by surface
Copper foil layer (806), the bottom of the aluminum base layer (801), which is covered, to be had PI film layer (807), the dielectric substance layer (805) and copper foil layer
(806) it is provided between gold thread (810), and the both ends of the gold thread (808) are provided with patch disk (809).
7. a kind of semiconductor diode chip structure according to claim 6, it is characterised in that: the ceramic film
(804) viscous by thermally conductive gluing between heat-conducting layer (803), and the heat-conducting glue is filled into groove (802), and described partly lead
Body diode chip (12) by encapsulating structure (10) encapsulate after by be welded to connect substrate (8) copper foil layer (806) it is positive and negative
On extremely.
8. a kind of semiconductor diode chip structure according to claim 1, it is characterised in that: the encapsulating structure (10)
Including package support (1002) and the reflector (1003) being mounted on package support (1002), the interior bottom of reflector (1003)
It is welded with metal heat sink (1004) on the package support surface centre in portion, the semiconductor diode chip (12) is mounted on metal
On heat sink (1004), package support (1002) the surface both ends are provided with metal pin (1005), and the metal pin
(1005) one end is connected on package support (1002) by point layer, and the other end of the metal pin (1005) extends into
In metal heat sink (1004), the metal heat sink is internally provided with electrical hole (1006), and the semiconductor diode chip
(12) it is connected on metal pin (1005) by passing through the interior bonding line (1007) of electrical hole (1006), two pole of semiconductor
Tube chip (12) surface is provided with hemisphere silica gel (1008), is provided between the hemisphere silica gel (1008) and reflector (1003)
Negative lens (1009) is located in the negative lens (1009) at the top of hemisphere silica gel (1008) and is provided with hemisphere vacuum chamber (1010),
It is provided with plane fluorescent bisque (1011) at the top of the hemisphere vacuum chamber (1010), and plane fluorescent layering (1011) top
Portion is provided with the closedtop cambered surface (1012) with negative lens (1009) integrally connected.
9. a kind of lamp luminescence component using semiconductor diode chip described in claim 1, it is characterised in that: including installation
The set ring plate (901) of seat (9) and screw occlusion on mounting base (9), the substrate (8) are arranged on mounting base (901),
Mounting base (9) bottom is provided with cartridge type radiating fin (902), is provided with ring layer among the cartridge type radiating fin (902)
Slot (903), the ring layer slot (903) is internal to be equipped with mini fan (904), the set ring plate (901) and cartridge type radiating fin
(902) surface contacted is provided with through slot (905).
10. lamp luminescence component according to claim 9, it is characterised in that: be located at ring layer slot (903) and set ring plate
(901) the cartridge type radiating fin (902) between is in sealing state.
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| CN201810531313.8A CN108963048A (en) | 2018-05-29 | 2018-05-29 | A kind of semiconductor diode chip structure and its lamp luminescence component |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810531313.8A CN108963048A (en) | 2018-05-29 | 2018-05-29 | A kind of semiconductor diode chip structure and its lamp luminescence component |
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| CN101369614A (en) * | 2007-08-17 | 2009-02-18 | 刘胜 | Packaging structure and method for high power white light LED |
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