CN108962929A - 感光元件及其制造方法 - Google Patents
感光元件及其制造方法 Download PDFInfo
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- CN108962929A CN108962929A CN201810822629.2A CN201810822629A CN108962929A CN 108962929 A CN108962929 A CN 108962929A CN 201810822629 A CN201810822629 A CN 201810822629A CN 108962929 A CN108962929 A CN 108962929A
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- Nanotechnology (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
一种感光元件及其制造方法,其中感光元件的制造方法包括:连续沉积第二导电层、感光材料层以及第一顶电极材料层于基板上;形成第一图案化光致抗蚀剂层于第一顶电极材料层上;以第一图案化光致抗蚀剂层为掩模,图案化第一顶电极材料层,以形成第一顶电极;移除第一图案化光致抗蚀剂层;以第一顶电极为掩模,图案化感光材料层,以形成感光层;形成绝缘层于第一顶电极上,且绝缘层具有开口;以及形成第二顶电极于绝缘层上,第二顶电极透过开口而电性连接第一顶电极。
Description
技术领域
本发明是有关于一种电子元件及其制造方法,且特别是有关于一种感光元件及其制造方法。
背景技术
随着科技的进展,个人用电子设备的功能日益增加。举例来说,现在市面上的手机往往除了通话功能以外,更包含了照相功能、录影功能、记事功能、上网功能......等等生活中时常会使用的功能。在这些具备多功能的电子设备中,往往设置有感光元件,感光元件能检测电子产品所处环境的光线,除了能帮助使用者获得更佳的拍照、录影品质外,部分的感光元件还能检测使用者手指表面的起伏,使电子产品具备指纹辨识的功能。要如何提升感光元件的成像品质以准确的辨识使用者的指纹是目前各家厂商亟欲解决的问题。
发明内容
本发明提供一种感光元件的制造方法,能解决感光层的介面受损导致成像不佳的问题。
本发明提供一种感光元件,能解决感光层的介面受损导致成像不佳的问题。
本发明的一种感光元件的制造方法,包括连续沉积第二导电层、感光材料层以及第一顶电极材料层于基板上。接着,形成第一图案化光致抗蚀剂层于第一顶电极材料层上,再以第一图案化光致抗蚀剂层为掩模,图案化第一顶电极材料层,以形成第一顶电极。之后,移除第一图案化光致抗蚀剂层,再以第一顶电极为掩模,图案化感光材料层,以形成感光层。接着,形成绝缘层于第一顶电极上。绝缘层具有开口。再来,形成第二顶电极于绝缘层上,且第二顶电极透过开口而电性连接第一顶电极。
本发明的一种感光元件,包括底电极、感光层、第一顶电极、绝缘层以及第二顶电极。底电极、感光层以及第一顶电极依续堆叠于基板上。感光层的材料包括富硅氧化物。底电极与感光层之间具有实质平坦的介面。绝缘层设置于第一顶电极上。绝缘层覆盖第一顶电极和感光层和底电极。绝缘层具有开口。第二顶电极透过开口而电性连接第一顶电极。
基于上述,本发明的感光元件及其制造方法可以改善感光元件成像不佳的问题,提升显示品质。
以下结合附图和具体实施例对本发明进行详细描述,但不作为对本发明的限定。
附图说明
图1A至图1O是依照本发明一实施例的一种感光元件的制造流程示意图。
图2是依照本发明一实施例的一种感光元件的部分元件的上视示意图。
图3是依照本发明另一实施例的一种感光元件的剖面示意图。
图4是依照本发明另一实施例的一种感光元件的部分元件的上视示意图。
图5是根据图4的剖面线B-B’示出的感光元件的剖面示意图。
其中,附图标记:
10、20、30:感光元件
100:背光模块
A-A’、B-B’:剖面线
BE:底电极
CE:电容电极
CL:图案化导线层
D:漏极
DL:数据线
FL:平坦层
FL1:第一有机平坦层
FL2:第二有机平坦层
G:栅极
GI:栅绝缘层
IL:绝缘层
ITO:透明导电层
L:光线
M1:图案化第一导电层
M2:第二导电层
M2’:图案化电极层
M3:遮光层
O1:开口
OB:待测物
OC、OC’:欧姆接触层
PR1:第一图案化光致抗蚀剂层
PR2:第二图案化光致抗蚀剂层
PS:感光材料层
PS’:感光层
S:源极
SB:基板
SL:扫描线
SM:半导体图案层
T:开关元件
t1、t2:厚度
TE1:第一顶电极材料层
TE1’:第一顶电极
TE2:第二顶电极
具体实施方式
下面结合附图对本发明的结构原理和工作原理作具体的描述:
在下文中将参照附图更全面地描述本发明,在附图中示出了本发明的示例性实施例。如本领域技术人员将认识到的,可以以各种不同的方式修改所描述的实施例,而不脱离本发明的精神或范围。
除非另有定义,本文使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员通常理解的相同的含义。将进一步理解的是,诸如在通常使用的字典中定义的那些术语应当被解释为具有与它们在相关技术和本发明的上下文中的含义一致的含义,并且将不被解释为理想化的或过度正式的意义,除非本文中明确地这样定义。
本文参考作为理想化实施例的示意图的截面图来描述示例性实施例。因此,可以预期到作为例如制造技术及/或(and/or)公差的结果的图示的形状变化。因此,本文所述的实施例不应被解释为限于如本文所示的区域的特定形状,而是包括例如由制造导致的形状偏差。例如,示出或描述为平坦的区域通常可以具有粗糙及/或非线性特征。此外,所示的锐角可以是圆的。因此,图中所示的区域本质上是示意性的,并且它们的形状不是旨在示出区域的精确形状,并且不是旨在限制权利要求的范围。
图1A至图1O是依照本发明一实施例的一种感光元件的制造流程示意图。图2是依照本发明一实施例的一种感光元件的部分元件的上视示意图。图1O对应了图2剖面线A-A’的位置,且图2省略示出了图1O中的部分构件。
请参考图1A,提供基板SB,并于基板SB上形成图案化第一导电层M1。基板SB例如为硬质基板(rigid substrate)或柔性基板(flexible substrate)等。举例而言,基板SB的材质可为玻璃、塑胶、复合材质或其他可以提供支撑且可制作板状结构的材质。
图案化第一导电层M1包括栅极G以及电容电极CE。栅极G电性连接至扫描线。电容电极CE位于两相邻的扫描线之间。图案化第一导电层M1的材质为导电材料。举例而言,图案化第一导电层M1的材质可为单层或多层堆叠的金属材料,例如选自由铜(Copper,Cu)、钼(Molybdenum,Mo)、钛(Titanium,Ti)、铝(Aluminum,A1)、钨(Tungsten,W)、银(Silver,Ag)、金(Gold,Au)及其合金所组成的族群中的至少之一。图案化第一导电层M1可透过微影蚀刻工艺来图案化金属材料而制作,但不须以此为限。
请参考图1B,于基板SB以及图案化第一导电层M1上形成栅绝缘层GI。图案化第一导电层M1位于基板SB与栅绝缘层GI之间。栅绝缘层GI可为单层结构或多层堆叠的复合结构,且栅绝缘层GI的材质例如是氮化硅、氧化硅、氮氧化硅、其他合适的介电材料或上述的组合。
请继续参考图1B,在形成栅绝缘层GI之后,于栅绝缘层GI上形成半导体图案层SM。半导体图案层SM与栅极G重叠。半导体图案层SM与栅极G重叠藉由栅绝缘层GI彼此分隔而不接触。在本实施例中,半导体图案层SM的表面形成有欧姆接触层OC,然而本发明不以此为限。半导体图案层SM可为单层或多层结构,其包含非晶硅、多晶硅、微晶硅、单晶硅、有机半导体材料、氧化物半导体材料(例如:铟锌氧化物、铟镓锌氧化物、其它合适的材料或上述的组合)、其它合适的材料、含有掺杂物(dopant)于上述材料中或上述材料的组合。
欧姆接触层OC的材料例如是n型掺杂半导体,其形成方法例如是以化学气相沉积法沉积半导体并同步进行n型离子掺杂,然而本发明不以此为限。在其他实施例中,欧姆接触层OC的材料也可以是p型掺杂半导体。
请参考图1C,于半导体图案层SM与栅绝缘层GI上形成第二导电层M2。第二导电层M2覆盖栅绝缘层GI、半导体图案层SM、欧姆接触层OC以及电容电极CE。半导体图案层SM与欧姆接触层OC位于栅绝缘层GI与第二导电层M2之间。在本实施例中,第二导电层M2例如是钛和铝多层堆叠的Ti/Al/Ti金属结构,但本发明不限于此。第二导电层M2可以为单层结构或多层堆叠的复合结构,且其材质例如是钛、铝、钼、银、钯(Palladium,Pd)或其合金等金属材料。第二导电层M2的材料可与图案化第一导电层M1的材料相同或不同。
请参考图1D,于第二导电层M2上依序沉积感光材料层PS以及第一顶电极材料层TE1。第二导电层M2、感光材料层PS以及第一顶电极材料层TE1是连续沉积于基板SB上。在本实施例中,感光材料层PS的材料包括富硅氧化物,但不限于此,例如:PIN材料或PN材料。根据其他实施例,感光材料层PS的材料包括富硅氮化物、富硅氮氧化物、富硅碳化物、富硅碳氧化物、氢化富硅氧化物、氢化富硅氮化物、氢化富硅碳化物或其组合。
请参考图1E,于第一顶电极材料层TE1上形成第一图案化光致抗蚀剂层PR1。在本实施例中,第一图案化光致抗蚀剂层PR1与电容电极CE重叠,但本发明不以此为限。
请参考图1F,以第一图案化光致抗蚀剂层PR1为掩模,图案化第一顶电极材料层TE1,以形成第一顶电极TE1’。在本实施例中,第一顶电极TE1’与电容电极CE重叠,但本发明不以此为限。在本实施例中,第一顶电极TE1’可为透明导电材料,例如金属氧化物,例如:铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物、其它合适的氧化物或者是上述至少二者的堆叠层。
请参考图1G,移除第一图案化光致抗蚀剂层PR1。
请参考图1H,以第一顶电极TE1’为掩模,图案化感光材料层PS,以形成感光层PS’。在本实施例中,感光层PS’与电容电极CE重叠,但本发明不以此为限。在较佳的实施例中,感光层PS’以及第一顶电极TE1’于基板SB垂直投影的尺寸实质相等。需说明的是,以第一顶电极TE1’为掩模对感光材料层PS进行蚀刻工艺时,亦可能发生侧向蚀刻的情况,使蚀刻后形成的感光层PS’于接近第一顶电极TE1’处可能会有一些侧向蚀刻。感光层PS’的材料和感光材料层PS相同,在此不再赘述。
请参考图1I,于第二导电层M2上形成第二图案化光致抗蚀剂层PR2。第二图案化光致抗蚀剂层PR2具有对应半导体图案层SM的开口OP以暴露出部分的第二导电层M2。
请参考图1J,以第二图案化光致抗蚀剂层PR2为掩模,图案化第二导电层M2,以定义出图案化电极层M2’以及底电极BE。底电极BE连接图案化电极层M2’。在本实施例中,部分的欧姆接触层OC会被一并移除,以留下欧姆接触层OC’。
图案化电极层M2’覆盖部分半导体图案层SM。图案化电极层M2’包括源极S、漏极D以及数据线DL(示出于图2)。在本实施例中,源极S以及漏极D可藉由湿式蚀刻剂(etchant)蚀刻所形成,但本发明不以此为限。湿式蚀刻剂例如为硫酸、磷酸、硝酸与醋酸或至少上述二者的混合、铝酸蚀刻液或其它适合的蚀刻剂。源极S电性连接至数据线DL,漏极D电性连接至底电极BE,且源极S与漏极D电性连接至半导体图案层SM。
底电极BE与电容电极CE重叠且藉由栅绝缘层GI彼此分隔而不接触。底电极BE、感光层PS’以及第一顶电极TE1’依续堆叠于基板SB上。
图案化以形成底电极BE的第二导电层M2、图案化以形成感光层PS’的感光材料层PS以及图案化以形成第一顶电极TE1’的第一顶电极材料层TE1是连续沉积于基板SB上,也可以说底电极BE、感光材料层PS以及第一顶电极材料层TE1是连续沉积于基板SB上。举例来说,沉积第二导电层M2之后,接着再于第二导电层M2中至少底电极BE的部分上沉积感光材料层PS以及第一顶电极材料层TE1。第二导电层M2、感光材料层PS以及第一顶电极材料层TE1是连续沉积于基板SB上。在一些实施例中,底电极BE与感光层PS’之间具有实质平坦的介面。在一些实施例中,感光层PS’与第一顶电极TE1’之间具有实质平坦的介面,藉由连续沉积的方式,可以减少膜层与膜层之间的介面受到损伤,使膜层之间的介面较为平坦,解决感光元件成像不佳的问题,提升显示装置的显示品质。
在本实施例中,开关元件T例如是底部栅极型薄膜晶体管,其包括栅极G、源极S、漏极D以及半导体图案层SM,然而本发明不以此为限。在其他实施例中,开关元件T也可以是顶部栅极型薄膜晶体管,或其他适合的薄膜晶体管。开关元件T电性连接至底电极BE。
数据线DL与扫描线SL彼此交错设置(示出于图2),且数据线DL与扫描线SL之间夹有栅绝缘层GI。本发明的实施例,是以扫描线SL的延伸方向与数据线DL的延伸方向不平行为例。较佳的是,扫描线SL的延伸方向与数据线DL的延伸方向互相垂直。
请参考图1K,移除第二图案化光致抗蚀剂层PR2。
请参考图1L,于第一顶电极TE1’上形成绝缘层IL,且绝缘层IL具有开口O1。绝缘层IL覆盖第一顶电极TE1’,开口O1暴露出部分第一顶电极TE1’。绝缘层IL覆盖感光层PS’和底电极BE。底电极BE和感光层PS’之间不具有绝缘层IL。绝缘层IL的材料包含无机材料(例如:氧化硅、氮化硅、氮氧化硅、其它合适的材料或上述至少二种材料的堆叠层)、有机材料、其它合适的材料或上述的组合。
请参考图1M,于绝缘层IL上形成第二顶电极TE2,至此大致完成感光元件10。部分绝缘层IL位于第一顶电极TE1’与第二顶电极TE2之间。第二顶电极TE2透过开口O1而电性连接第一顶电极TE1’。在本实施例中,第二顶电极TE2的厚度t2大于第一顶电极TE1’的厚度t1。在本实施例中,感光层PS’是平坦的,因此可以使底电极BE与第一顶电极TE1’之间的重叠面积最大化,藉此提升两者之间的有效电场。在本实施例中,第二顶电极TE2材料可和第一顶电极TE1’相同或不同,第二顶电极TE2可为透明导电材料,材料例如金属氧化物,如:铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物、其它合适的氧化物或者是上述至少二者的堆叠层。
请参考图1N,于第二顶电极TE2上形成遮光层M3。遮光层M3与栅极G重叠。遮光层M3的材质可为单层或多层堆叠的金属材料(例如选自由铜、钼、钛、铝、钨、银、金及其合金所组成的族群中的至少之一)、树脂材料(例如聚酰亚胺、丙烯酸酯或其他合适的树脂材料)、石墨或其他合适的材料。
请参考图1O,于第二顶电极TE2上形成平坦层FL。平坦层FL覆盖第二顶电极TE2。在本实施例中,平坦层FL的材料为有机材料,例如聚酯类(PET)、聚烯类、聚丙酰类、聚碳酸酯类、聚环氧烷类、聚苯烯类、聚醚类、聚酮类、聚醇类、聚醛类、其它合适的材料或上述的组合,然而本发明不以此为限。根据其他实施例,平坦层FL的材质也可以是无机材料(例如氧化硅、氮化硅、氮氧化硅、其它合适的材料或上述至少二种材料的堆叠层)、其它合适的材料或上述的组合。
平坦层FL的厚度大于2微米(μm)且小于或等于25微米。在较佳的实施例中,平坦层FL的厚度大于12微米(μm)且小于或等于25微米。在本实施例中,提高平坦层FL的厚度可以增加电子元件对静电放电(electrostatic discharge;ESD)的耐受度。在本实施例中,平坦层FL的厚度大于25微米时,容易造成感光元件感应不良。
在本实施例中,平坦层的介电强度大于200MV/m。增强平坦层的介电强度可以提升电子元件对静电放电(electrostatic discharge;ESD)的耐受度。进一步地,可以增加电子元件的使用年限。
基于上述,底电极BE、感光层PS’以及第一顶电极TE1’藉由连续沉积形成,可以减少感光元件10中的膜层与膜层之间的介面受到损伤,解决感光元件成像不佳的问题,提升显示装置的显示品质。
图3是依照本发明另一实施例的一种感光元件的剖面示意图。在此必须说明的是,图3的实施例沿用图1A~1O、图2的实施例的元件标号与部分内容,其中采用相同或近似的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,在此不赘述。
请参考图3,在本实施例中,形成平坦层FL的方法包括先形成第一有机平坦材料层于第二顶电极TE2上,固化第一有机平坦材料层以形成第一有机平坦层FL1,再形成第二有机平坦材料层于第一有机平坦层FL1上,固化第二有机平坦材料层以形成第二有机平坦层FL2。两层有机平坦层,每一次涂布的有机平坦材料可以较薄,固化时可使材料固化较完全,避免固化不完全而使感光元件品质不良。也就是说,在本实施例中,平坦层FL包括两层有机平坦层,但不以此为限。在其他实施例中,平坦层FL可以包括一层或超过两层的有机平坦层。
在本实施例中,形成平坦层FL之后,于平坦层FL上形成透明导电层ITO。透明导电层ITO例如是全面地覆盖于平坦层FL上。透明导电层ITO电性连接至接地电压。透明导电层ITO的材质包括金属氧化物,例如是镓锌氧化物、铟锡氧化物或者是铟锌氧化物。
在本实施例中,感光元件20还包括背光模块100。背光模块100位于基板SB下方。当背光模块100射出的光线L照射到位于透明导电层ITO上方的待测物OB,并被待测物OB反射至感光层PS’。于一实施例中,待测物OB例如为手指,感光元件20可检测手指上指纹的情况。
基于上述,藉由连续沉积底电极BE、感光层PS’以及第一顶电极TE1’,可以减少感光元件20中的膜层与膜层之间的介面受到损伤,解决感光元件成像不佳的问题,提升显示装置的显示品质。
图4是依照本发明另一实施例的一种感光元件的上视示意图。图5是根据图4的剖面线B-B’示出的感光元件的剖面示意图。在此必须说明的是,图4与图5的实施例沿用图3的实施例的元件标号与部分内容,其中采用相同或近似的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,下述实施例不再重复赘述。
图5的实施例与图3的实施例的区别的特点在于:以图案化导线层CL取代透明导电层ITO。
请参考图4及图5,在本实施例的感光元件30中,于第二顶电极TE2上形成平坦层FL。虽然本实施例仅形成一层平坦层,但本发明不以此为限。在其他实施例中,平坦层FL可以是两层以上。
在形成平坦层FL之后,于平坦层FL上形成图案化导线层CL。图案化导线层CL位于平坦层FL上且与开关元件T重叠。在本实施例中,图案化导线层CL还重叠于扫描线SL及数据线DL,可以避免降低开口率。图案化导线层CL电性连接至接地电压。在本实施例中,图案化导线层CL具有抗静电的功能,可以提升电子元件对静电放电的耐受度。进一步地,可以增加电子元件的使用年限。
基于上述,底电极BE、感光层PS’以及第一顶电极TE1’藉由连续沉积形成,可以减少感光元件中的膜层与膜层之间的介面受到损伤,解决感光元件成像不佳的问题,提升显示装置的显示品质。此外,感光元件30藉由具有抗静电功能的图案化导线层CL,可以提升电子元件对静电放电的耐受度。
综上所述,本发明的感光元件及其制造方法,藉由连续沉积底电极、感光材料层以及第一顶电极材料层,可以减少感光元件中的膜层与膜层之间的介面受到损伤,解决感光元件成像不佳的问题,提升显示装置的显示品质。此外,藉由具有高介电强度的平坦层或是具有抗静电功能的图案化导线层,可以提升电子元件对静电放电的耐受度,并且增加电子元件的使用年限。
当然,本发明还可有其它多种实施例,在不背离本发明精神及其实质的情况下,熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形,但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
Claims (19)
1.一种感光元件的制造方法,其特征在于,包括:
连续沉积一第二导电层、一感光材料层以及一第一顶电极材料层于一基板上;
形成一第一图案化光致抗蚀剂层于该第一顶电极材料层上;
以该第一图案化光致抗蚀剂层为掩模,图案化该第一顶电极材料层,以形成一第一顶电极;
移除该第一图案化光致抗蚀剂层;
以该第一顶电极为掩模,图案化该感光材料层,以形成一感光层;
形成一绝缘层于该第一顶电极上,且该绝缘层具有一开口;以及
形成一第二顶电极于该绝缘层上,该第二顶电极透过该开口而电性连接该第一顶电极。
2.如权利要求1所述的制造方法,其特征在于,其中于连续沉积该第二导电层、该感光材料层以及该第一顶电极材料层于该基板上之前更包括:
形成一图案化第一导电层于该基板上;
形成一栅绝缘层于该图案化第一导电层上;以及
形成一半导体图案层于该栅绝缘层上,其中该第二导电层形成于该半导体图案层与该栅绝缘层上;且
于形成该感光层之后且形成该绝缘层之前更包括:
形成一第二图案化光致抗蚀剂层于该第二导电层上;以及
以该第二图案化光致抗蚀剂层为掩模,图案化该第二导电层,以定义出一图案化电极层以及一底电极,其中该底电极连接该图案化电极层,该图案化电极层覆盖部分该半导体图案层。
3.如权利要求2所述的制造方法,其特征在于,其中该图案化第一导电层包括与该半导体图案层重叠的一栅极以及与该底电极重叠的一电容电极。
4.如权利要求2所述的制造方法,其特征在于,更包括:
形成一平坦层于该第二顶电极上;以及
形成一图案化导线层于该平坦层上,且该图案化导线层重叠于该图案化第一导电层及该图案化电极层,其中该图案化导线层电性连接至一接地电压。
5.如权利要求1所述的制造方法,其特征在于,更包括:
形成一平坦层于该第二顶电极上,其中该平坦层的介电强度大于200MV/m。
6.如权利要求1所述的制造方法,其特征在于,更包括:
形成一平坦层于该第二顶电极上,其中该平坦层为一有机材料,且该平坦层厚度大于2微米(μm)且小于或等于25微米。
7.如权利要求1所述的制造方法,其特征在于,更包括:
形成一平坦层于该第二顶电极上,其中形成该平坦层包括先形成一第一有机平坦材料层于该第二顶电极上,固化该第一有机平坦材料层以形成一第一有机平坦层,再形成一第二有机平坦材料层于该第一有机平坦层上,固化该第二有机平坦材料层以形成一第二有机平坦层。
8.如权利要求1所述的制造方法,其特征在于,更包括:
形成一平坦层于该第二顶电极上;以及
形成一透明导电层于该平坦层上,且该透明导电层电性连接至一接地电压。
9.如权利要求1所述的制造方法,其特征在于,其中该感光层的材料包括富硅氧化物。
10.一种感光元件,其特征在于,包括:
一底电极、一感光层以及一第一顶电极依续堆叠于一基板上,其中该感光层的材料包括富硅氧化物,其中该底电极与该感光层之间具有实质平坦的介面;
一绝缘层,设置于该第一顶电极上,且覆盖该第一顶电极和该感光层和该底电极,且该绝缘层具有一开口;以及
一第二顶电极,透过该开口而电性连接该第一顶电极。
11.如权利要求10所述的感光元件,其特征在于,其中该感光层以及该第一顶电极于该基板垂直投影的尺寸实质相等。
12.如权利要求10所述的感光元件,其特征在于,其中该第二顶电极的厚度大于该第一顶电极的厚度。
13.如权利要求10所述的感光元件,其特征在于,其中部分该绝缘层位于该第一顶电极与该第二顶电极之间。
14.如权利要求10所述的感光元件,其特征在于,其中该底电极和该感光层之间不具有该绝缘层。
15.如权利要求10所述的感光元件,其特征在于,更包括:
一平坦层,覆盖该第二顶电极。
16.如权利要求15所述的感光元件,其特征在于,其中该平坦层的介电强度大于200MV/m。
17.如权利要求15所述的感光元件,其特征在于,其中该平坦层为一有机材料且厚度大于2微米(μm)且小于或等于25微米。
18.如权利要求15所述的感光元件,其特征在于,更包括:
一开关元件,电性连接至该底电极;以及
一图案化导线层,位于该平坦层上,且与该开关元件重叠,其中该图案化导线层电性连接至一接地电压。
19.如权利要求15所述的感光元件,其特征在于,更包括:
一透明导电层,位于该平坦层上,且电性连接至一接地电压。
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