CN108962742A - 半导体结构的制造方法 - Google Patents

半导体结构的制造方法 Download PDF

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CN108962742A
CN108962742A CN201710377242.6A CN201710377242A CN108962742A CN 108962742 A CN108962742 A CN 108962742A CN 201710377242 A CN201710377242 A CN 201710377242A CN 108962742 A CN108962742 A CN 108962742A
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amorphous carbon
etched
mask
semiconductor
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CN108962742B (zh
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郑二虎
齐金和
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

本申请公开了一种半导体结构的制造方法，涉及半导体技术领域。所述方法包括：在基底上的待刻蚀材料层的表面上形成半导体层；在所述半导体层上形成非晶碳层；在所述非晶碳层上形成图案化的掩模层；以及以所述掩模层为掩模对所述非晶碳层、所述半导体层和所述待刻蚀材料层进行刻蚀。本申请可以提高非晶碳层的均匀性，从而使得在刻蚀待刻蚀材料层后形成的图形的位置不会偏离期望的位置，并且使得图形的形状为期望的形状。

Description

半导体结构的制造方法
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构的制造方法。
背景技术
非晶碳由于具有独特的特性，例如相对硅的氧化物、硅的氮化物和多晶硅高的刻蚀选择性，低反射率的紫外线吸收等，因此被广泛应用在先进技术节点的半导体制造工艺中。例如，非晶碳可以作为接触孔刻蚀、栅极图案化等刻蚀工艺的掩模，或者可以作为自对准双重曝光(SADP)的牺牲层。
然而，本申请的发明人发现，在现有的应用中，所形成的非晶碳厚度的均匀性差，这会使得以非晶碳作为掩模刻蚀的图形不能满足要求，例如接触孔的位置偏离期望的位置、接触孔的形状不能满足要求等。
因此，有必要提出一种技术方案，使得非晶碳厚度的均匀性更好。
发明内容
本申请的一个目的在于提高非晶碳层厚度的均匀性。
根据本申请的一方面，提供了一种半导体结构的制造方法，包括：在基底上的待刻蚀材料层的表面上形成半导体层；在所述半导体层上形成非晶碳层；在所述非晶碳层上形成图案化的掩模层；以及以所述掩模层为掩模对所述非晶碳层、所述半导体层和所述待刻蚀材料层进行刻蚀。
在一个实施例中，所述半导体层包括硅层。
在一个实施例中，所述硅层包括单晶硅层或非晶硅层。
在一个实施例中，通过直流叠加等离子体工艺形成所述硅层；或对所述待刻蚀材料层的表面进行离子注入以形成所述硅层；或通过原子层沉积工艺来形成所述硅层。
在一个实施例中，所述直流叠加等离子体工艺采用的源气体包括氮气、氩气、氦气、氢气或羟基流气体。
在一个实施例中，所述待刻蚀材料层包括层间电介质层；所述层间电介质层被刻蚀以形成具有贯穿所述层间电介质层的接触孔。
在一个实施例中，所述方法还包括：去除所述掩模层；沉积金属材料以填充所述接触孔；以及执行平坦化工艺，以去除剩余的非晶碳层、剩余的半导体层，从而使得剩余的金属材料的上表面与剩余的待刻蚀材料层的上表面基本齐平。
在一个实施例中，所述待刻蚀材料层包括栅极材料层；所述栅极材料层被刻蚀以形成栅极。
在一个实施例中，所述方法还包括：去除所述掩模层、剩余的非晶碳层和剩余的半导体层。
在一个实施例中，所述半导体层的厚度范围为1-5nm；所述非晶碳层的厚度范围为10-1000nm。
根据本申请的另一方面，提供了一种半导体结构的制造方法，包括：在基底上的待刻蚀材料层的表面上形成半导体层；在所述半导体层上形成非晶碳层；在所述非晶碳层上形成图案化的第一掩模层；以所述第一掩模层为掩模、以所述半导体层为蚀刻停止层对所述非晶碳层进行刻蚀；去除所述第一掩模层；在剩余的非晶碳层的侧壁上形成第二掩模层；去除所述剩余的非晶碳层；以及以所述第二掩模层为掩模对所述半导体层和所述待刻蚀材料层进行刻蚀。
在一个实施例中，所述半导体层包括硅层。
在一个实施例中，所述硅层包括单晶硅层或非晶硅层。
在一个实施例中，通过直流叠加等离子体工艺形成所述硅层；或对所述待刻蚀材料层的表面进行离子注入以形成所述硅层；或通过原子层沉积形成所述硅层。
在一个实施例中，所述直流叠加等离子体工艺采用的源气体包括氮气、氩气、氦气、氢气或羟基流气体。
在一个实施例中，所述半导体层的厚度范围为1-5nm；
所述非晶碳层的厚度范围为10-1000nm。
本申请实施例在形成非晶碳层之前，先在待刻蚀材料层的表面上形成了半导体层，这有利于提高非晶碳层的均匀性。由于非晶碳层更均匀，这使得在以掩模层为掩模对非晶碳层进行刻蚀后形成的掩模图形的位置不会偏离期望的位置，而且掩模图形的形状也为期望的形状。进而，可以使得在刻蚀待刻蚀材料层后形成的图形的位置不会偏离期望的位置，并且使得图形的形状为期望的形状。
通过以下参照附图对本申请的示例性实施例的详细描述，本申请的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本申请的示例性实施例，并且连同说明书一起用于解释本申请的原理，在附图中：
图1是根据本申请一个实施例的半导体结构的制造方法的流程示意图；
图2A-图2F示出了根据本申请一个实施例的半导体结构的制造方法的各个阶段的示意图；
图3A-图3E示出了根据本申请另一个实施例的半导体结构的制造方法的各个阶段的示意图；
图4是根据本申请又一个实施例的半导体结构的制造方法的流程示意图；
图5A-图5H示出了图4所示半导体结构的制造方法的各个阶段的示意图。
具体实施方式
现在将参照附图来详细描述本申请的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本申请范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本申请及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
本申请的发明人针对非晶碳层厚度不均匀的问题进入了深入研究，发现：在待刻蚀材料层上形成非晶碳层时，待刻蚀材料的不同会导致非晶碳层厚度的均匀性的差异。如果在形成非晶碳层之前形成一层半导体层，则能改善非晶碳层厚度均匀性差的问题。据此，发明人提出了如下技术方案。
图1是根据本申请一个实施例的半导体结构的制造方法的流程示意图。
在步骤102，在基底上的待刻蚀材料层的表面上形成半导体层。优选地，半导体层可以包括硅层。
在步骤104，在半导体层上形成非晶碳层。
在步骤106，在非晶碳层上形成图案化的掩模层。这里，掩模层的图案定义了待刻蚀材料最终要形成的图形的位置和形状。
在步骤108，以掩模层为掩模对非晶碳层、半导体层和待刻蚀材料层进行刻蚀。这里，刻蚀可以停止在待刻蚀材料层之中，或者，也可以停止在基底的表面。
上述实施例中，在形成非晶碳层之前，先在待刻蚀材料层的表面上形成了半导体层，这有利于提高非晶碳层的均匀性。由于非晶碳层更均匀，这使得在以掩模层为掩模对非晶碳层进行刻蚀后形成的掩模图形的位置不会偏离期望的位置，而且掩模图形的形状也为期望的形状。进而，可以使得在刻蚀待刻蚀材料层后形成的图形的位置不会偏离期望的位置，并且使得图形的形状为期望的形状。
下面介绍两个不同的实施例来分别详细介绍图1所示的半导体结构的制造方法。
图2A-图2F示出了根据本申请一个实施例的半导体结构的制造方法的各个阶段的示意图。该实施例中的待刻蚀材料层可以是层间电介质层。
首先，如图2A所示，在基底201上的待刻蚀材料层202的表面上形成半导体层203。
基底201可以包括硅基底、锗基底等元素半导体基底，或者可以包括砷化镓等化合物半导体基底等。基底201中可以形成有半导体器件，例如CMOS器件等。待刻蚀材料层202可以为层间电介质层，例如硅的氧化物或硅的氮化物等。
半导体层203的厚度优选比较小，厚度范围优选为约1-5nm，例如2nm、3nm等。优选地，半导体层203可以包括硅层。在一个实施例中，硅层可以是单晶硅层、非晶硅层或多晶硅层。优选地，硅层为单晶硅层或非晶硅层。
可以通过不同的方式来形成硅层，下面介绍三种优选的方式。
在一个实施例中，可以通过直流叠加(direct current superposition)等离子体工艺形成硅层。这种方式更容易形成比较薄的硅层。优选地，直流叠加等离子体工艺采用的源气体可以包括氮气、氩气、氦气、氢气或羟基流气体等。
在另一个实施例中，可以对待刻蚀材料层302的表面进行离子注入以形成硅层。这里，可以调整离子注入的能量和注入的硅的剂量来控制所形成的硅层的厚度。
在又一个实施例中，可以通过原子层沉积(ALD)工艺形成硅层。
然后，如图2B所示，在半导体层203上形成非晶碳层204。
例如，可以通过化学气相沉积(CVD)或ALD形成非晶碳层204。又例如，可以通过对石墨靶材进行溅射的方式形成非晶碳层204。
非晶碳层204的厚度范围可以为约10nm-1000nm，例如，30nm、50nm、100nm、500nm、800nm等。在半导体层203的厚度为约1-5nm的情况下，非晶碳层的厚度为约10nm-1000nm之间时更均匀。
接下来，如图2C所示，在非晶碳层204上形成图案化的掩模层205，例如光致抗蚀剂。优选地，还可以在非晶碳层204与掩模层205之间形成底部抗反射层(图中未示出)。这里，掩模层205具有开口215，开口215的位置和形状定义了后续刻蚀形成的接触孔206的位置和形状。
之后，如图2D所示，以掩模层205为掩模对非晶碳层204、半导体层203和待刻蚀材料层202进行刻蚀。待刻蚀材料层202，也即层间电介质层被刻蚀后，形成了具有贯穿层间电介质层的接触孔206。
在形成接触孔206之后，如图2E所示，还可以去除掩模层205。然后沉积金属材料207以填充接触孔206。金属材料207例如可以包括铜等。
之后，如图2F所示，执行平坦化工艺，例如化学机械平坦化工艺，以去除剩余的非晶碳层204A、剩余的半导体层203A，从而使得剩余的金属材料207A的上表面与剩余的待刻蚀材料层202A的上表面基本齐平，也即在工艺偏差范围内的齐平。如此形成了接触件207A。
如上介绍了根据本申请一个实施例的半导体结构的制造方法。上述实施例的制造方法在形成非晶碳层之前先形成了半导体层，从而使得非晶碳层的均匀性更好。由于非晶碳层更均匀，这使得在以掩模层为掩模对非晶碳层进行刻蚀后形成的掩模图形的位置不会偏离期望的位置，而且掩模图形的形状也为期望的形状。从而，可以使得待刻蚀材料层被刻蚀后形成的接触孔的位置不会偏离期望的位置，并且使得接触孔的形状为期望的形状。进而，可以使得在接触孔中填充金属材料后形成的接触件的位置不会偏离期望的位置，并且使得接触件的形状为期望的形状。
图3A-图3E示出了根据本申请另一个实施例的半导体结构的制造方法的各个阶段的示意图。该实施例中的待刻蚀材料层可以是栅极材料层。下面仅重点介绍该实施例与图2A-图2F所示实施例的不同之处，其他相关之处可以参照上面的描述。
首先，如图3A所示，在基底301上的待刻蚀材料层302的表面上形成半导体层303。
基底301中可以形成有阱区、浅沟槽隔离区、半导体鳍片等。待刻蚀材料层302为栅极材料层，例如多晶硅等。半导体层303优选可以包括硅层，例如，单晶硅层或非晶硅层。硅层的形成方式可以参照上面的描述，在此不再赘述。
然后，如图3B所示，在半导体层303上形成非晶碳层304。
接下来，如图3C所示，在非晶碳层304上形成图案化的掩模层305，例如光致抗蚀剂。这里，掩模层305的位置和形状定义了后续刻蚀形成的栅极302A的位置和形状。
之后，如图3D所示，以掩模层305为掩模对非晶碳层304、半导体层303和待刻蚀材料层302进行刻蚀。待刻蚀材料层302，也即栅极材料层被刻蚀后形成了栅极302A。
之后，可选地，如图3E所示，还可以去除掩模层305、剩余的非晶碳层304A和剩余的半导体层303A。
如上介绍了根据本申请另一个实施例的半导体结构的制造方法。上述实施例的制造方法在形成非晶碳层之前先形成了半导体层，从而使得非晶碳层的均匀性更好。由于非晶碳层更均匀，这使得在以掩模层为掩模对非晶碳层进行刻蚀后形成的掩模图形的位置不会偏离期望的位置，而且掩模图形的形状也为期望的形状。从而，可以使得待刻蚀材料层被刻蚀后形成的栅极的位置不会偏离期望的位置，并且使得栅极的形状为期望的形状。
需要说明的是，虽然上面以待刻蚀材料层为层间电介质层和栅极材料层为例对半导体结构的制造方法进行了说明，但是，这并不用于限制本申请的范围。
应理解，在其他的实施例中，待刻蚀材料层也可以其他要被刻蚀的材料，本申请不再一一列举。
图4是根据本申请又一个实施例的半导体结构的制造方法的流程示意图。图5A-图5H示出了图4所示半导体结构的制造方法的各个阶段的示意图。下面结合图4、图5A-图5H对根据本申请又一个实施例的半导体结构的制造方法进行详细说明。
首先，在步骤402，在基底501上的待刻蚀材料层502的表面上形成半导体层503，如图5A所示。
待刻蚀材料层502例如可以是栅极材料层。半导体层503的厚度优选比较小，厚度范围优选为1-5nm，例如2nm、3nm等。优选地，半导体层503可以包括硅层，例如单晶硅层或非晶硅层。硅层的形成方式可以参照上面介绍的方式，在此不再做详细介绍。
接下来，在步骤404，在半导体层503上形成非晶碳层504，如图5B所示。非晶碳层204的厚度范围可以为约10nm-1000nm，例如，30nm、50nm、100nm、500nm、800nm等。
然后，在步骤406，在非晶碳层504上形成图案化的第一掩模层505，例如光致抗蚀剂，如图5C所示。
之后，在步骤408，以第一掩模层505为掩模、以半导体层503为蚀刻停止层对非晶碳层504进行刻蚀，如图5D所示。这里，刻蚀后剩余的非晶碳层504A作为牺牲层，之后会被去除。
之后，在步骤410，去除第一掩模层，如图5E所示。
之后，在步骤412，在剩余的非晶碳层504A的侧壁上形成第二掩模层506，如图5F所示。第二掩模层506例如可以是硅的氮化物等。
在一个实现方式中，可以在剩余的非晶碳层504A的上表面和侧壁上、以及半导体层503的表面上形成第二掩模材料层，然后通过各向异性刻蚀去除剩余的非晶碳层504A的上表面以及半导体层503的表面上的第二掩模材料层，剩余的第二掩模材料层作为第二掩模层506。
之后，在步骤414，去除剩余的非晶碳层504A，如图5G所示。
之后，在步骤416，以第二掩模层506为掩模对半导体层503和待刻蚀材料层502进行刻蚀，如图5H所示。
例如，可以以基底501为刻蚀停止层进行刻蚀，或者，也可以对待刻蚀材料层502的一部分进行刻蚀，从而使得刻蚀停止在待刻蚀材料层502之中。
例如，待刻蚀材料层502被刻蚀后形成了半导体鳍片。这种方式可以形成尺寸更小的半导体鳍片。
之后可以去除第二掩模层506。也可以视情况去除剩余的半导体层503A。
如上介绍了根据本申请又一个实施例的半导体结构的制造方法。上述实施例的制造方法在形成非晶碳层之前先形成了半导体层，从而使得非晶碳层的均匀性更好。由于非晶碳层更均匀，这使得在非晶碳层的侧壁上形成的第一掩模层的掩模图形的位置不会偏离期望的位置，而且掩模图形的形状也为期望的形状。进而，可以使得待刻蚀材料层被刻蚀后形成的图形的位置不会偏离期望的位置，并且使得图形的形状为期望的形状。
至此，已经详细描述了根据本申请实施例的半导体结构的制造方法。为了避免遮蔽本申请的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本申请的精神和范围。

Claims (16)

1.一种半导体结构的制造方法，其特征在于，包括：
在基底上的待刻蚀材料层的表面上形成半导体层；
在所述半导体层上形成非晶碳层；
在所述非晶碳层上形成图案化的掩模层；以及
以所述掩模层为掩模对所述非晶碳层、所述半导体层和所述待刻蚀材料层进行刻蚀。
2.根据权利要求1所述的方法，其特征在于，所述半导体层包括硅层。
3.根据权利要求2所述的方法，其特征在于，所述硅层包括单晶硅层或非晶硅层。
4.根据权利要求2所述的方法，其特征在于，
通过直流叠加等离子体工艺形成所述硅层；或
对所述待刻蚀材料层的表面进行离子注入以形成所述硅层；或
通过原子层沉积工艺来形成所述硅层。
5.根据权利要求4所述的方法，其特征在于，所述直流叠加等离子体工艺采用的源气体包括氮气、氩气、氦气、氢气或羟基流气体。
6.根据权利要求1所述的方法，其特征在于，所述待刻蚀材料层包括层间电介质层；
所述层间电介质层被刻蚀以形成具有贯穿所述层间电介质层的接触孔。
7.根据权利要求6所述的方法，其特征在于，还包括：
去除所述掩模层；
沉积金属材料以填充所述接触孔；以及
执行平坦化工艺，以去除剩余的非晶碳层、剩余的半导体层，从而使得剩余的金属材料的上表面与剩余的待刻蚀材料层的上表面基本齐平。
8.根据权利要求1所述的方法，其特征在于，所述待刻蚀材料层包括栅极材料层；
所述栅极材料层被刻蚀以形成栅极。
9.根据权利要求8所述的方法，其特征在于，还包括：
去除所述掩模层、剩余的非晶碳层和剩余的半导体层。
10.根据权利要求1所述的方法，其特征在于，
所述半导体层的厚度范围为1-5nm；
所述非晶碳层的厚度范围为10-1000nm。
11.一种半导体结构的制造方法，其特征在于，包括：
在基底上的待刻蚀材料层的表面上形成半导体层；
在所述半导体层上形成非晶碳层；
在所述非晶碳层上形成图案化的第一掩模层；
以所述第一掩模层为掩模、以所述半导体层为蚀刻停止层对所述非晶碳层进行刻蚀；
去除所述第一掩模层；
在剩余的非晶碳层的侧壁上形成第二掩模层；
去除所述剩余的非晶碳层；以及
以所述第二掩模层为掩模对所述半导体层和所述待刻蚀材料层进行刻蚀。
12.根据权利要求11所述的方法，其特征在于，所述半导体层包括硅层。
13.根据权利要求12所述的方法，其特征在于，所述硅层包括单晶硅层或非晶硅层。
14.根据权利要求12所述的方法，其特征在于，
通过直流叠加等离子体工艺形成所述硅层；或
对所述待刻蚀材料层的表面进行离子注入以形成所述硅层；或
通过原子层沉积形成所述硅层。
15.根据权利要求14所述的方法，其特征在于，所述直流叠加等离子体工艺采用的源气体包括氮气、氩气、氦气、氢气或羟基流气体。
16.根据权利要求11所述的方法，其特征在于，
所述半导体层的厚度范围为1-5nm；
所述非晶碳层的厚度范围为10-1000nm。
CN201710377242.6A 2017-05-25 2017-05-25 半导体结构的制造方法 Active CN108962742B (zh)

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