CN108899363A - 能降低导通压降和关断损耗的沟槽栅igbt器件 - Google Patents

能降低导通压降和关断损耗的沟槽栅igbt器件 Download PDF

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CN108899363A
CN108899363A CN201810993078.6A CN201810993078A CN108899363A CN 108899363 A CN108899363 A CN 108899363A CN 201810993078 A CN201810993078 A CN 201810993078A CN 108899363 A CN108899363 A CN 108899363A
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杨晓鸾
许生根
张金平
姜梅
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Jiangsu CAS IGBT Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01ELECTRIC ELEMENTS
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    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract

本发明涉及一种能降低导通压降和关断损耗的沟槽栅IGBT器件,其在第二导电类型基区内设置第一导电类型源区,所述第一导电类型源区与第一导电类型杂质区分别位于元胞沟槽的两侧,元胞沟槽内填充有栅极导电多晶硅,所述栅极导电多晶硅通过元胞沟槽内的绝缘栅氧化层与元胞沟槽的侧壁、底壁绝缘隔离;在第一导电类型漂移区的上方设置源极金属以及栅极金属,所述源极金属与第一导电类型源区、第二导电类型基区以及第二导电类型杂质区欧姆接触,栅极金属与栅极导电多晶硅以及第一导电类型杂质区欧姆接触。本发明结构紧凑,能同时降低导通压降和关断损耗,优化IGBT器件的折衷特性,安全可靠。

Description

能降低导通压降和关断损耗的沟槽栅IGBT器件
技术领域
本发明涉及一种沟槽栅IGBT器件,尤其是一种能降低导通压降和关断损耗的沟槽栅IGBT器件,属于IGBT器件的技术领域。
背景技术
IGBT是功率半导体器件中具有代表性的一类三端器件,因其同时具有高耐压、低导通压降、易驱动、开关速度快等优点,在开关电源、变频调速、逆变器等许多功率领域有重要的应用。
IGBT是在同一半导体区建立起双极电流导通机制和MOSFET栅电流控制机制。IGBT在导通和开关过程中均存在着功率损耗,而且其导通损耗、开关损耗以及安全工作区三者之间存在着折衷关系。为了追求最优的IGBT特性,降低IGBT的功率损耗,拓宽其安全工作区,IGBT的技术发展路线为:结构逐渐由平面栅结构发展为沟槽栅结构,并进而发展为软沟槽型结构(电子增强注入与扩散、载流子存储);其纵向结构逐渐由穿通型发展为非传统型,进而发展为场截止型。
目前主流的IGBT结构为沟槽栅场截止型IGBT,这种IGBT具有较优的开通关断折衷特性,但因其具有较高的电流密度,短路特性欠佳。为了进一步优化短路特性,继而出现了具有P型浮置dummy结构的沟槽栅场截止型IGBT,在器件导通的过程中,dummy区的P型浮置区底部有空穴载流子积累效应,所以该结构既可以降低沟道密度进而提升短路特性,又可以有效降低导通压降。
但现有的具有P型浮置dummy结构的沟槽栅场截止型IGBT,因为在器件导通的过程中,dummy结构的P型浮置区底部具有空穴积累效应,这部分空穴在器件关断的过程中会降低关断速度,增大关断损耗。
发明内容
本发明的目的是克服现有技术中存在的不足,提供一种能降低导通压降压降和关断损耗的沟槽栅IGBT器件,其结构紧凑,能同时降低导通压降和关断损耗,优化IGBT器件的折衷特性,安全可靠。
按照本发明提供的技术方案,所述能降低导通压降和关断损耗的沟槽栅IGBT器件,包括半导体基板以及位于所述半导体基板中心的元胞区,所述半导体基板包括第一导电类型漂移区以及位于所述第一导电类型漂移区内上部的第二导电类型基区;
元胞区包括若干元胞,每个元胞内包括两个元胞沟槽,所述元胞沟槽位于第二导电类型基区内且元胞沟槽的深度伸入第二导电类型基区下方的第一导电类型漂移区内;在所述第一导电类型漂移区内还设置第二导电类型杂质区,所述第二导电类型杂质区的底部与元胞沟槽的槽底接触;
在所述第二导电类型杂质区内还设置对称分布的第一导电类型杂质区,所述第一导电类型杂质区邻近元胞沟槽;
在所述IGBT器件的截面上,在第二导电类型基区内设置第一导电类型源区,所述第一导电类型源区与第一导电类型杂质区分别位于元胞沟槽的两侧,元胞沟槽内填充有栅极导电多晶硅,所述栅极导电多晶硅通过元胞沟槽内的绝缘栅氧化层与元胞沟槽的侧壁、底壁绝缘隔离;
在第一导电类型漂移区的上方设置源极金属以及栅极金属,所述源极金属与第一导电类型源区、第二导电类型基区以及第二导电类型杂质区欧姆接触,栅极金属与栅极导电多晶硅以及第一导电类型杂质区欧姆接触。
所述第二导电类型杂质区的底部位于第二导电类型基区的下方,第二导电类型杂质区覆盖元胞沟槽的距离大于绝缘栅氧化层的厚度。
在所述第一导电类型漂移区的背面设置第二导电类型集电区,在所述第二导电类型集电区上设置集电极金属,所述集电极金属与第二导电类型集电区欧姆接触。
所述元胞沟槽的深度为5μm~8μm,栅极导电多晶硅的宽度为0.5μm~2μm,第二导电类型基区的深度为3μm~7μm。
所述“第一导电类型”和“第二导电类型”两者中,对于N型功率IGBT器件,第一导电类型指N型,第二导电类型为P型;对于P型功率IGBT器件,第一导电类型与第二导电类型所指的类型与N型半导体器件正好相反。
本发明的优点:在第二导电类型杂质区内设置对称分布的第一导电类型杂质区,第二导电类型杂质区、第一导电类型源区以及第二导电类型基区均与源极金属欧姆接触,第一导电类型杂质区、栅极导电多晶硅均与栅极金属欧姆接触;当IGBT器件导通过程中,第二导电类型杂质区与其内部的第一导电类型杂质区形成反偏结,耗尽层可阻挡空穴载流子经第二导电类型杂质区中流出,使得空穴载流子在第二导电类型杂质区底部积累,从而有效降低器件的导通损耗;在器件关断时,第二导电类型杂质区与其内部的第一导电类型杂质区等电位,可使积累在第二导电类型杂质区的空穴迅速经第二导电类型杂质区的源极接触孔抽出,从而有效降低器件的关断损耗,结构紧凑,安全可靠。
附图说明
图1为本发明的结构示意图。
图2为本发明导通时载流子的流通路径图。
图3为本发明关断时载流子的流通路径图。
附图标记说明:1-P型基区、2-N+源区、3-P型杂质区、4-N型杂质区、5-源极接触孔、6-绝缘栅氧化层、7-栅极导电多晶硅、8-N型漂移区、9-P+集电区以及10-集电极金属。
具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
如图1所示:为了同时降低导通压降和关断损耗,优化IGBT器件的折衷特性,以N型IGBT器件为例,本发明包括半导体基板以及位于所述半导体基板中心的元胞区,所述半导体基板包括N型漂移区8以及位于所述N型漂移区8内上部的P型基区1;
元胞区包括若干元胞,每个元胞内包括两个元胞沟槽,所述元胞沟槽位于P型基区1内且元胞沟槽的深度伸入P型基区1下方的N型漂移区8内;在所述N型漂移区8内还设置P型杂质区3,所述P型杂质区3的底部与元胞沟槽的槽底接触;
在所述P型杂质区3内还设置对称分布的N型杂质区4,所述N型杂质区4邻近元胞沟槽;
在所述IGBT器件的截面上,在P型基区1内设置N+源区2,所述N+源区2与N型杂质区4分别位于元胞沟槽的两侧,元胞沟槽内填充有栅极导电多晶硅7,所述栅极导电多晶硅7通过元胞沟槽内的绝缘栅氧化层6与元胞沟槽的侧壁、底壁绝缘隔离;
在N型漂移区8的上方设置源极金属以及栅极金属,所述源极金属与第N+源区2、P型基区6以及P型杂质区3欧姆接触,栅极金属与栅极导电多晶硅7以及N型杂质区4欧姆接触。
具体地,半导体基板的材料可以为硅或其他常用的材料,具体可以根据需要进行选择,此处不再一一列举。元胞区位于半导体基板的中心区,当然,在元胞区的外圈还设置终端保护区,元胞区与终端保护区之间的配合关系为本技术领域人员所熟知,此处不再赘述。P型基区1位于N型漂移区8内的上部,P型基区1的深度小于N型漂移区8的厚度。
元胞区内包括若干元胞,元胞区内的元胞并联成一体,每个元胞内包括两个元胞沟槽,元胞沟槽在N型漂移区8内穿过P型基区1,即元胞沟槽的槽底位于P型基区1的下方,P型基区1与元胞沟槽的侧壁接触。在N型漂移区8内还设置P型杂质区3,P型杂质区3的主体部分位于元胞沟槽之间,P型杂质区3的底部位于P型基区1的下方,P型杂质区3的底部与元胞沟槽的槽底接触。
本发明实施例中,在P型杂质区3内还设置N型杂质区4,N型杂质区3在P型杂质区3内呈对称分布,N型杂质区4邻近元胞沟槽的侧壁(N型杂质区4可以与元胞沟槽的侧壁接触),N型杂质区4的在P型杂质区3内的深度小于元胞沟槽的高度,N型杂质区4的掺杂浓度大于P型杂质区3的掺杂浓度。在P型杂质区3内,两N型杂质区4之间具有间距,该间距可以作为Vge负偏压时的空穴通道,该间距的宽度由P型杂质区3与N型杂质区4形成的PN结在Vge正偏压下的耗尽层宽度决定,间距小于等于P型杂质区3与N型杂质区4形成的PN结在Vge正偏压下耗尽层宽度的两倍,以满足在Vge正偏压时,P型杂质区3与两N型杂质区4形成的耗尽层宽度可以将空穴通道夹断。Vge为IGBT器件的栅电极与源电极之间的电压。
在P型基区1内设置N+源区2,N+源区2与元胞沟槽的侧壁接触。在元胞沟槽内填充栅极导电多晶硅7,元胞沟槽的侧壁以及底壁设置绝缘栅氧化层6,利用绝缘栅氧化层6能使得栅极导电多晶硅7与元胞沟槽的侧壁以及底壁绝缘隔离。
为了能形成IGBT器件的源电极以及栅电极,需要在N型漂移区8的上方制备源极金属以及栅极金属,源极金属与N+源区2、P型基区6以及P型杂质区3与源极金属欧姆接触,栅极金属与栅极导电多晶硅7以及N型杂质区4欧姆接触,从而利用源极金属、栅极金属能形成所需的源电极、栅电极。源极金属、栅极金属间相互隔离,并均在N型漂移区8的上方,图1中并未示出源极金属、栅极金属以及在N型漂移区8上方的位置关系,源极金属、栅极金属在N型漂移区8上方的位置关系等情况为本技术领域人员所熟知,此处不再赘述。为了能实现源极金属与N+源区2、P型基区1以及P型杂质区3的欧姆接触,需要制备源极接触孔5,源极金属填充在源极接触孔5内后,源极金属能实现与N+源极2、P型基区1以及P型杂质区3的欧姆接触,具体制备源极接触孔5的过程以及源极金属填充在源极接触孔5的具体情况均为本技术领域人员所熟知,此处不再赘述。
进一步地,所述P型杂质区3的底部位于P型基区1的下方,P型杂质区3覆盖元胞沟槽槽底的距离大于绝缘栅氧化层6的厚度。
本发明实施例中,P型杂质区3在N型漂移区8的深度大于P型基区1在N型漂移区8内的深度,P型杂质区3覆盖元胞沟槽槽底的距离大于绝缘栅氧化层6的厚度,一般地,P型杂质区3覆盖元胞沟槽槽底的距离可以为元胞沟槽宽度的一半,即能使得P型杂质区3能包覆元胞沟槽相应的端角。此外,所述元胞沟槽的深度为5μm~8μm,栅极导电多晶硅7的宽度为0.5μm~2μm,P型基区1的深度为3μm~7μm。P型杂质区3的浓度、深度以及宽度与IGBT元胞耐压相关,具体为本技术领域根据需要进行选择设定,此处不再详述。
进一步地,在所述N型漂移区8的背面设置P+集电区9,在所述P+集电区9上设置集电极金属10,所述集电极金属10与P+集电区9欧姆接触。
本发明实施例中,P+集电区9位于N型漂移区8的背面,源极金属、栅极金属等元胞结构位于N型漂移区8的正面,集电极金属10与P+集电区9欧姆接触后,能得到IGBT器件的集电极。
具体地,当IGBT器件导通过程中,P型杂质区3与其内部的N型杂质区4形成反偏结,耗尽层可阻挡空穴载流子经P型杂质区3中流出,使得空穴载流子在P型杂质区3底部积累,从而有效降低器件的导通损耗;
在器件关断时,P型杂质区3与其内部的N型杂质区4等电位,可使积累在P型杂质区3的空穴迅速经P型杂质区3的源极接触孔5抽出,从而有效降低器件的关断损耗。

Claims (4)

1.一种能降低导通压降和关断损耗的沟槽栅IGBT器件,包括半导体基板以及位于所述半导体基板中心的元胞区,所述半导体基板包括第一导电类型漂移区以及位于所述第一导电类型漂移区内上部的第二导电类型基区;
元胞区包括若干元胞,每个元胞内包括两个元胞沟槽,所述元胞沟槽位于第二导电类型基区内且元胞沟槽的深度伸入第二导电类型基区下方的第一导电类型漂移区内;在所述第一导电类型漂移区内还设置第二导电类型杂质区,所述第二导电类型杂质区的底部与元胞沟槽的槽底接触;其特征是:
在所述第二导电类型杂质区内还设置对称分布的第一导电类型杂质区,所述第一导电类型杂质区邻近元胞沟槽;
在所述IGBT器件的截面上,在第二导电类型基区内设置第一导电类型源区,所述第一导电类型源区与第一导电类型杂质区分别位于元胞沟槽的两侧,元胞沟槽内填充有栅极导电多晶硅,所述栅极导电多晶硅通过元胞沟槽内的绝缘栅氧化层与元胞沟槽的侧壁、底壁绝缘隔离;
在第一导电类型漂移区的上方设置源极金属以及栅极金属,所述源极金属与第一导电类型源区、第二导电类型基区以及第二导电类型杂质区欧姆接触,栅极金属与栅极导电多晶硅以及第一导电类型杂质区欧姆接触。
2.根据权利要求1所述的能降低导通压降和关断损耗的沟槽栅IGBT器件,其特征是:所述第二导电类型杂质区的底部位于第二导电类型基区的下方,第二导电类型杂质区覆盖元胞沟槽的距离大于绝缘栅氧化层的厚度。
3.根据权利要求1所述的能降低导通压降和关断损耗的沟槽栅IGBT器件,其特征是:在所述第一导电类型漂移区的背面设置第二导电类型集电区,在所述第二导电类型集电区上设置集电极金属,所述集电极金属与第二导电类型集电区欧姆接触。
4.根据权利要求1所述的能降低导通压降和关断损耗的沟槽栅IGBT器件,其特征是:所述元胞沟槽的深度为5μm~8μm,栅极导电多晶硅的宽度为0.5μm~2μm,第二导电类型基区的深度为3μm~7μm。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110444588A (zh) * 2019-08-21 2019-11-12 江苏中科君芯科技有限公司 能降低正向导通压降的沟槽igbt器件
CN113764510A (zh) * 2021-07-30 2021-12-07 西安电子科技大学 一种新型低关断损耗的电子注入效应增强igbt器件
CN116884996A (zh) * 2023-09-08 2023-10-13 深圳芯能半导体技术有限公司 一种降低关断损耗的igbt芯片及其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060071217A1 (en) * 2004-10-01 2006-04-06 Takasumi Ohyanagi Semiconductor device
CN106653836A (zh) * 2016-12-01 2017-05-10 无锡新洁能股份有限公司 具有低导通压降的绝缘栅双极型晶体管器件及其制造方法
CN107611179A (zh) * 2017-10-24 2018-01-19 贵州芯长征科技有限公司 降低栅源电容的屏蔽栅mosfet结构及其制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060071217A1 (en) * 2004-10-01 2006-04-06 Takasumi Ohyanagi Semiconductor device
CN106653836A (zh) * 2016-12-01 2017-05-10 无锡新洁能股份有限公司 具有低导通压降的绝缘栅双极型晶体管器件及其制造方法
CN107611179A (zh) * 2017-10-24 2018-01-19 贵州芯长征科技有限公司 降低栅源电容的屏蔽栅mosfet结构及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
黄建伟;杨鑫著;刘根;罗海辉;余伟;谭灿健;: "沟槽栅IGBT关键技术研究", 大功率变流技术, no. 02 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110444588A (zh) * 2019-08-21 2019-11-12 江苏中科君芯科技有限公司 能降低正向导通压降的沟槽igbt器件
CN113764510A (zh) * 2021-07-30 2021-12-07 西安电子科技大学 一种新型低关断损耗的电子注入效应增强igbt器件
CN113764510B (zh) * 2021-07-30 2022-09-09 西安电子科技大学 一种低关断损耗的电子注入效应增强igbt器件
CN116884996A (zh) * 2023-09-08 2023-10-13 深圳芯能半导体技术有限公司 一种降低关断损耗的igbt芯片及其制作方法

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