CN108886017A - 通过氢退火恢复钴电阻 - Google Patents

通过氢退火恢复钴电阻 Download PDF

Info

Publication number
CN108886017A
CN108886017A CN201780017732.3A CN201780017732A CN108886017A CN 108886017 A CN108886017 A CN 108886017A CN 201780017732 A CN201780017732 A CN 201780017732A CN 108886017 A CN108886017 A CN 108886017A
Authority
CN
China
Prior art keywords
interconnection piece
sedimentary
layer
interlayer interconnection
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201780017732.3A
Other languages
English (en)
Other versions
CN108886017B (zh
Inventor
尼古劳斯·贝基亚里斯
梅裕尔·奈克
吴志远
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/075,039 external-priority patent/US9570345B1/en
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN108886017A publication Critical patent/CN108886017A/zh
Application granted granted Critical
Publication of CN108886017B publication Critical patent/CN108886017B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832Multiple layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883Post-treatment or after-treatment of the conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

因在从钴互连件上去除表面氧化物和在钴互连件上沉积含氮膜期间发生的氮化作用而造成的钴互连件的电阻增大通过氢热退火或等离子体处理解决。穿过薄覆盖层去除氮化物,薄覆盖层可以是介电阻挡层或蚀刻终止层。

Description

通过氢退火恢复钴电阻
技术领域
本公开内容涉及一种形成分层结构的方法,分层结构具有用于在集成电路(诸如互补金属氧化物半导体(CMOS)结构)中的层间连接的导电钴互连件。
背景技术
随着CMOS装置的临界尺寸(CD)减小,导电互连件的线电阻增大。导电互连件典型地是铜。为了解决增大线电阻的问题,导电互连件可以由钴而不是铜形成。
在化学机械抛光(CMP)之后,钴互连件的暴露表面倾向于形成覆盖的薄氧化钴层,必须将之去除。一种用于去除薄氧化钴层的方法是用氨等离子体(由NH3形成的等离子体)来处理结构。此处理可增强结构的时间相关介电击穿(TDDB)行为。在不损坏下方的层的情况下去除氧化钴层是有挑战性的。
发明内容
根据第一方面,一种处理工件的方法包括:在工件上形成介电层和延伸穿过介电层的层间互连件;通过在由含氮气体形成的等离子体中处理工件来从层间互连件的暴露表面上去除氧化物;和在层间互连件上沉积厚度不超过、例如小于例如100埃的阈值厚度的沉积层。方法进一步包括:通过从穿过介电阻挡层的层间互连件上去除氮来减小层间互连件的电阻;和将介电阻挡层的厚度增大到高于阈值厚度。
在一个实施方式中,含氮气体包括氨。在一个实施方式中,层间互连件包括钴。
在一个实施方式中,阈值厚度不超过50埃,并且可以为约20埃。
在一个实施方式中,从层间互连件上去除氮包括将工件暴露于氢等离子体、自由基或氢热退火。
在一个实施方式中,介电阻挡层包括硅和以下中的一种或多种:碳、氧或氮。
在一个实施方式中,阈值厚度小至足以允许通过氢等离子体、自由基或氢热退火穿过介电阻挡层去除氮。
根据第二方面,一种处理工件的方法包括:在工件上形成介电层和延伸穿过介电层的层间互连件;和通过在由含氮气体形成的等离子体中处理工件或氢等离子体、自由基或氢热退火来从层间互连件的暴露表面上去除氧化物。方法进一步包括:在层间互连件上沉积厚度小于阈值厚度的蚀刻终止层;通过从穿过蚀刻终止层的层间互连件中去除氮,减小层间互连件的电阻;和将蚀刻终止层的厚度增大到高于阈值厚度。
在一个实施方式中,层间互连件包括钴。
在一个实施方式中,阈值厚度小于50埃,或可以为约20埃。
在一个实施方式中,从层间互连件上去除氮包括将工件暴露于氢等离子体、自由基或氢热退火。
在一个实施方式中,蚀刻终止层包括含氮材料,诸如AlN。
在一个实施方式中,含氮气体包括氨。
在一个实施方式中,阈值厚度小至足以允许通过氢等离子体、自由基或氢热退火穿过蚀刻终止层去除氮。
附图说明
为了获得并且可详细地理解本发明的示例性实施方式,上文简要地概述的本发明的更特别的描述可以参考本发明的实施方式进行,实施方式示出在随附附图中。将了解,本文中不讨论某些所熟知的工艺,以便不模糊本发明。
图1A、图1B、图1C、图1D和图1E描绘了集成电路结构的连续的侧视图,连续的侧视图对应于一系列的工艺操作。
图2是对应于图1A至图1E的连续性的工艺操作序列的流程框图。
图3A、图3B、图3C、图3D和图3E描绘了集成电路结构的连续的侧视图,连续的侧视图对应于一系列的工艺操作。
图4是对应于图3A至图3E的连续性的工艺操作序列的流程框图。
为了促进理解,已经尽可能地使用相同的元件符号标示各图共有的相同要素。将构想,一个实施方式的要素和特征可有益地并入在其他实施方式中,不再赘述。然而,应注意,附图仅示出了本发明的示例性的实施方式,并且因此不应视为限制本发明的范围,因为本发明可允许其他等效实施方式。
具体实施方式
如前所述,去除氧化钴层而不损坏下方的层是有挑战性的。我们发现钴互连件有一个问题是暴露于氮或含氮物质(诸如氨等离子体)会导致钴互连件的电阻增大。我们认为这是由于钴互连件的氮化造成的。这种增大可能是显著的,例如约5%至25%,这取决于结构大小和装置密度。因此,一个问题是如何避免因氮化而造成的增大的电阻。
在一些情况下,在去除氧化钴之后,在钴互连件上沉积介电阻挡层。这样的介电阻挡层含有硅与其他材料(诸如碳、氧和/或氮)的组合。钴互连件与含硅阻挡层的接触引起钴互连件的硅化。这样的硅化增大钴互连件的线电阻。因此,第二个问题是如何在钴互连件的顶部提供含硅阻挡层而不会因来自蚀刻终止层的硅对钴互连件的硅化而导致电阻增大。
在其他情况下,在去除氧化钴之后,在钴互连件上沉积蚀刻终止层。蚀刻终止层典型地是含氮材料,诸如氮化铝(AlN),并且留在适当位置至少直到工艺中的后续蚀刻操作完成。即使使用非氨工艺去除氧化钴(例如氢等离子体,自由基或气体退火),含氮蚀刻终止层与钴互连件的接触也会导致钴互连件的氮化,这增大钴互连件的线电阻。因此,第三个问题是如何在钴互连件的顶部提供含氮蚀刻终止层而不会因来自蚀刻终止层的氮对钴互连件的氮化而导致电阻增大。
参考图1A以及图2A的框200,介电层90是形成在诸如半导体晶片的工件92上的多层半导体结构的多个层中的一个。介电层90可以包括具有低介电常数的材料的底部介电层100。钴互连件104从底部介电层100延伸穿过介电层90到介电层90的顶表面90a。结构包括大量的钴互连件,在附图中仅示出其中一个。因此,钴互连件104是延伸穿过介电层90的多个互连件中的一个。工件92通过化学机械抛光进行处理,这使钴互连件104的顶表面104a暴露。顶表面104a在暴露时氧化以形成氧化钴层106。工件92放置在等离子体反应腔室107中(以虚线表示),其中它可以在图2的其余工艺中保留。或者,工艺的不同操作可以在不同腔室中进行,而不一定在一个腔室中。
如图1B描绘,通过采用氨等离子体的氧化物还原工艺去除氧化钴层106(图2的框205)。来自氨等离子体的一些氮积聚在顶表面104a下方并在钴互连件104中形成含氮区108。这可以被称为氮化。钴互连件104中氮的存在增大了钴互连件的电阻。
含氮区108对硅化具有抗性或不受硅化作用,并且暂时留在原位以防止在随后的含硅介电阻挡层沉积期间的硅化,如现在将描述。
如图1C所示,沉积介电阻挡层110(图2的框210)。此沉积可使用等离子体增强化学气相沉积(PECVD)工艺、或使用物理气相沉积(PVD)工艺、或使用例如原子层沉积(ALD)工艺来执行。介电阻挡层110很薄(约20埃)。介电阻挡层110可以是包括诸如碳、氧和/或氮的其他材料的含硅材料和/或可以以低介电常数为特征。
如图1D所示,钴互连件104中的氮通过在腔室中采用氢的氢等离子体、自由基或氢热退火去除(图2的框215)。介电阻挡层110足够薄(例如,在5-100埃的范围内,例如小于100埃,或小于50埃,诸如20埃),以通过氢等离子体、自由基或氢热退火从钴互连件104穿过介电阻挡层110去除氮。氮的这种去除消除氮化,否则会增大钴互连件104的电阻。我们发现通过氢的这种处理使钴互连件的电阻恢复到钴互连件暴露于氨等离子体之前的原始(较小)值。
此后,如图1E所示,通过沉积附加的介电阻挡层材料112,可以将介电阻挡层110的厚度增大到期望的厚度(例如,高达300埃,例如,100埃)(图2的框220)。例如,此沉积可使用等离子体增强化学气相沉积(PECVD)工艺或使用物理气相沉积(PVD)工艺或使用原子层沉积(ALD)工艺来执行。
现在将描述第二实施方式。参考图3A以及图4的框400,介电层190是形成在诸如半导体晶片的工件192上的多层半导体结构的多个层中的一个。介电层190可以包括低介电常数的底部介电层300。钴互连件304从底部介电层300延伸穿过介电层190到介电层190的顶表面190a。结构包括大量的钴互连件,在附图中仅示出其中一个。因此,钴互连件304是延伸穿过介电层190的多个互连件中的一个。工件192通过化学机械抛光进行处理,这使钴互连件304的顶表面304a暴露。顶表面304a在暴露时氧化以形成氧化钴层106。工件192放置在等离子体反应腔室307中(以虚线表示),并且它可以在图4的其余工艺中保留在那里。或者,工艺的不同操作可以在不同腔室中执行。
如图3B描绘,通过在反应腔室中产生氨等离子体来去除氧化钴层306(图4的框405)。或者,可以在活性预清洁工艺中进行氧化钴去除,该工艺采用了活性物质,诸如(但不限于)氢自由基。如果使用氨等离子体去除氧化钴,那么来自氨等离子体的氮积聚在顶表面304a下方以在钴互连件304中形成含氮区域308。钴互连件304中氮的存在增大了钴互连件的电阻。
如图3C所示,沉积蚀刻终止层310(图4的框410)。蚀刻终止层310很薄(约20埃)。蚀刻终止层310可以是含氮材料,诸如氮化铝(AlN),并且因此其沉积有助于钴互连件304的氮化。这是重要的特征,其中使用活性预清洁工艺来执行氧化钴去除,因为活性预清洁工艺不提供钴互连件的氮化。在这种情况下,通过AlN蚀刻终止层沉积提供氮化。例如,可以在CVD工艺或PECVD工艺或物理气相沉积(PVD)工艺中或使用原子层沉积(ALD)工艺来执行AlN蚀刻终止层310的沉积。
如图3D所示,使用氢气(H2)通过腔室中的氢等离子体、自由基或氢热退火去除钴互连件中的氮(例如,在含氮区308中)(图4的框415)。蚀刻终止层310足够薄(例如,在5-100埃的范围内,例如小于100埃,或小于50埃,诸如20埃),以通过氢等离子体、自由基或氢热退火从钴互连件304穿过蚀刻终止层310去除氮。氮的这种去除消除氮化,否则会增大钴互连件304的电阻。氢热退火可以在200-500摄氏度的温度范围内进行。我们发现通过氢的这种处理使钴互连件的电阻恢复到钴互连件通过氨等离子体或含氮蚀刻终止暴露于钴氮化之前的原始(较小)值。
此后,如图3E所示,通过在薄蚀刻终止层310上沉积附加的蚀刻终止材料312,可以将蚀刻终止层310的厚度增大到期望的厚度(例如,高达300埃,例如100埃)(图4的框420)。薄蚀刻终止层310保护钴互连件免受附加的蚀刻终止材料312中的氮的影响。例如,此沉积可通过CVD或PVD工艺或ALD工艺来执行。
优点:
上述实施方式通过氮化和硅化解决了钴互连件的电阻增大的问题。在通过氨等离子体从钴互连件中去除表面氧化物期间发生氮化。通过穿过介电层的氢处理来去除氮化,并防止硅化。通过在沉积含硅层的同时暂时将氮化物留在适当位置来利用钴互连件的氮化。在沉积含硅层期间,氮化物阻挡钴互连件的硅化。通过初始的含硅层去除氮,初始含硅层足够薄以使氢能够穿过初始的含硅层抽出钴互连件中的氮。此后,可以通过进一步沉积含硅材料而不使钴互连件硅化来增大含硅层的厚度,因为初始的含硅材料薄层保护钴互连件。等离子体反应腔室107可以是能够执行上述过程或操作中的每一个而不从等离子体反应器(集成工具)107移除工件的集成工具。在一个实施方式中,集成工具在相同腔室中执行前述操作。在另一实施方式中,集成工具在不同腔室中执行不同操作。在另一实施方式中,在不同工具中执行不同操作。
上述实施方式通过从含氮蚀刻终止层(例如,AlN)的氮化解决了钴互连件的电阻增大的问题。在这种情况下,通过将钴暴露于含氮膜而发生氮化。通过穿过初始AlN层的氢处理去除氮化。初始的AlN层足够薄以使氢能够穿过初始AlN层抽出钴互连件中的氮。此后,可通过进一步沉积AlN材料而不氮化钴互连件来增大AlN层的厚度,因为初始的薄AlN层保护钴互连件。等离子体反应腔室107可以是能够执行上述过程或操作中的每一个而不从等离子体反应腔室(集成工具)107移除工件的集成工具。在一个实施方式中,集成工具在相同腔室中执行前述操作。在另一实施方式中,集成工具在不同腔室中执行不同操作。在另一实施方式中,在不同工具中执行不同操作。
尽管上述内容涉及本发明的实施方式,但也可在不脱离本发明的基本范围的情况下设计本发明的其他以及另外实施方式,并且本发明的范围是由随附权利要求书来确定。

Claims (18)

1.一种处理工件的方法,包括:
在所述工件上形成介电层和延伸穿过所述介电层的层间互连件;
从所述层间互连件的暴露表面上去除氧化物;
在所述层间互连件上沉积厚度小于阈值厚度的沉积层,所述沉积层包括介电阻挡层或蚀刻终止层中的一个;
通过从穿过所述沉积层的所述层间互连件中去除氮,减小所述层间互连件的电阻;和
将所述沉积层的厚度增大到高于所述阈值厚度。
2.如权利要求1所述的方法,其中所述层间互连件包括钴。
3.如权利要求1所述的方法,其中所述阈值厚度不超过100埃。
4.如权利要求3所述的方法,其中所述阈值厚度不超过50埃。
5.如权利要求4所述的方法,其中所述阈值厚度为约20埃。
6.如权利要求1所述的方法,其中去除所述氧化物包括在由含氮气体形成的等离子体中处理所述工件。
7.如权利要求6所述的方法,其中所述含氮气体包括氨。
8.如权利要求1所述的方法,其中所述从所述层间互连件上去除氮包括用氢等离子体、自由基或氢热退火中的一种处理所述层间互连件。
9.如权利要求1所述的方法,其中所述沉积层是介电阻挡层。
10.如权利要求9所述的方法,其中所述介电阻挡层包括硅。
11.如权利要求10所述的方法,其中所述介电阻挡层进一步包括碳、氧或氮中的一种或多种。
12.如权利要求1所述的方法,其中所述沉积层是包括含氮材料的蚀刻终止层。
13.如权利要求12所述的方法,其中所述蚀刻终止层包括氮化物。
14.如权利要求13所述的方法,其中所述蚀刻终止层包括AlN。
15.如权利要求1所述的方法,其中所述阈值厚度小至足以允许通过氢等离子体、自由基或氢热退火穿过所述沉积层去除氮。
16.如权利要求15所述的方法,其中所述氢热退火在200-500摄氏度的温度范围内进行。
17.一种处理工件的方法,包括:
提供集成工具;
在所述工件上形成介电层和延伸穿过所述介电层的层间互连件;
在所述集成工具的相应腔室中执行以下相应操作:
(a)从所述层间互连件的暴露表面上去除氧化物;
(b)在所述层间互连件上沉积厚度小于阈值厚度的沉积层,所述沉积层包括介电阻挡层或蚀刻终止层中的一个;
(c)通过从穿过所述沉积层的所述层间互连件中去除氮,减小所述层间互连件的电阻;和
(d)将所述沉积层的厚度增大到高于所述阈值厚度。
18.一种处理工件的方法,包括:
提供工具;
在所述工件上形成介电层和延伸穿过所述介电层的层间互连件;
在所述工具的一个腔室中执行以下相应操作:
(a)从所述层间互连件的暴露表面上去除氧化物;
(b)在所述层间互连件上沉积厚度小于阈值厚度的沉积层,所述沉积层包括介电阻挡层或蚀刻终止层中的一个;
(c)通过从穿过所述沉积层的所述层间互连件中去除氮,减小所述层间互连件的电阻;和
(d)将所述沉积层的厚度增大到高于所述阈值厚度。
CN201780017732.3A 2016-03-18 2017-03-16 通过氢退火恢复钴电阻 Active CN108886017B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US15/075,039 2016-03-18
US15/075,039 US9570345B1 (en) 2016-03-18 2016-03-18 Cobalt resistance recovery by hydrogen anneal
US15/140,955 US9711397B1 (en) 2016-03-18 2016-04-28 Cobalt resistance recovery by hydrogen anneal
US15/140,955 2016-04-28
PCT/US2017/022758 WO2017161147A1 (en) 2016-03-18 2017-03-16 Cobalt resistance recovery by hydrogen anneal

Publications (2)

Publication Number Publication Date
CN108886017A true CN108886017A (zh) 2018-11-23
CN108886017B CN108886017B (zh) 2023-06-06

Family

ID=59297864

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780017732.3A Active CN108886017B (zh) 2016-03-18 2017-03-16 通过氢退火恢复钴电阻

Country Status (5)

Country Link
US (1) US9711397B1 (zh)
JP (1) JP6981991B2 (zh)
KR (1) KR102327446B1 (zh)
CN (1) CN108886017B (zh)
WO (1) WO2017161147A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4009359A1 (en) * 2020-12-01 2022-06-08 Imec VZW Method of manufacturing a semiconductor structure

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006287022A (ja) * 2005-04-01 2006-10-19 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
US20070292603A1 (en) * 2005-08-31 2007-12-20 Lam Research Corporation Processes and systems for engineering a barrier surface for copper deposition
US20080233734A1 (en) * 2007-03-19 2008-09-25 Fujitsu Limited Method of manufacturing a semiconductor device
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
JP2009010016A (ja) * 2007-06-26 2009-01-15 Fujitsu Microelectronics Ltd 配線の形成方法及び半導体装置の製造方法
US20140227462A1 (en) * 2011-09-28 2014-08-14 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel. Ltd.) Wiring structure for display device
US20150021779A1 (en) * 2013-07-19 2015-01-22 Taiwan Semiconductor Manufacturing Company Limited Hard mask for back-end-of-line (beol) interconnect structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8455352B1 (en) * 2012-05-24 2013-06-04 Applied Materials, Inc. Method for removing native oxide and associated residue from a substrate

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
JP2006287022A (ja) * 2005-04-01 2006-10-19 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
US20070292603A1 (en) * 2005-08-31 2007-12-20 Lam Research Corporation Processes and systems for engineering a barrier surface for copper deposition
US20080233734A1 (en) * 2007-03-19 2008-09-25 Fujitsu Limited Method of manufacturing a semiconductor device
JP2009010016A (ja) * 2007-06-26 2009-01-15 Fujitsu Microelectronics Ltd 配線の形成方法及び半導体装置の製造方法
US20140227462A1 (en) * 2011-09-28 2014-08-14 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel. Ltd.) Wiring structure for display device
US20150021779A1 (en) * 2013-07-19 2015-01-22 Taiwan Semiconductor Manufacturing Company Limited Hard mask for back-end-of-line (beol) interconnect structure

Also Published As

Publication number Publication date
US9711397B1 (en) 2017-07-18
KR20180117639A (ko) 2018-10-29
JP2019509641A (ja) 2019-04-04
JP6981991B2 (ja) 2021-12-17
KR102327446B1 (ko) 2021-11-17
WO2017161147A1 (en) 2017-09-21
CN108886017B (zh) 2023-06-06

Similar Documents

Publication Publication Date Title
US10727119B2 (en) Process integration approach of selective tungsten via fill
KR101696973B1 (ko) 진보된 상호 접속을 위한 하이브리드 구리 구조를 포함하는 집적 칩 및 금속화층을 형성하는 방법
CN104934409B (zh) 后道工序互连层上的通孔预填充
TWI548031B (zh) 導電結構之形成方法
TW541659B (en) Method of fabricating contact plug
CN107658289A (zh) 半导体器件及其制造方法
WO2007060640A2 (en) Method of forming a self aligned copper capping layer
US20150255330A1 (en) Barrier-seed tool for fine-pitched metal interconnects
US9318383B2 (en) Integrated cluster to enable next generation interconnect
TW201426869A (zh) 於通孔底部具有自形成阻障層之半導體設備
US9349689B2 (en) Semiconductor devices including conductive features with capping layers and methods of forming the same
US20230361038A1 (en) Topological semi-metal interconnects
CN108886017A (zh) 通过氢退火恢复钴电阻
EP1401015B1 (en) Selective dry etching of tantalum nitride
CN109216320B (zh) 半导体装置
TWI438865B (zh) 半導體裝置及其製造方法
US6174793B1 (en) Method for enhancing adhesion between copper and silicon nitride
US9570345B1 (en) Cobalt resistance recovery by hydrogen anneal
US9502264B2 (en) Method for selective oxide removal
KR20160098502A (ko) 진보된 배선들을 위한 유전체 캡핑 배리어로서의 금속-함유 필름들
JP2008091863A (ja) 半導体素子の製造方法
CN109003939B (zh) 一种半导体器件的制作方法
CN109841512A (zh) 半导体装置的制造方法
US7553736B2 (en) Increasing dielectric constant in local regions for the formation of capacitors
JP2005197710A (ja) 半導体装置製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant